LSI Logic Japan Semiconductor
description
Transcript of LSI Logic Japan Semiconductor
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LSI LOGIC
LSI Logic Japan Semiconductor
Manufacturing Process
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LSI LOGIC
LSI Logic Japan Semiconductor
CustomerAssembly
Si wafer
Patterned wafer
LSI Logic Japan
Sorted wafer
What part at LLJS ?
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LSI LOGIC
LSI Logic Japan Semiconductor
CMOS Cross Section
Silicon N-Well
N+ S/D P+ S/D
Field OxideField Oxide
P-Well
Poly Si Gate
Gate OxideN-MOS Tr. P-MOS Tr.
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LSI LOGIC
LSI Logic Japan Semiconductor
CMOS 3LM Cross Section
Metal-1
Metal-2
Meatl-3W Plug
Insulator
Silicon
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LSI LOGIC
LSI Logic Japan Semiconductor
P-Sub.
P-Sub.
SiO2 Pad
Si3N4
SiO2
Oxidation
Bird’s beak
Cross Section of Process Flow- Field Oxidation -
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LSI LOGIC
LSI Logic Japan Semiconductor
Impla
Well
Diff (Anneal at ~900℃ )
P-Sub.
P-Sub.
Resist
SiO2
Cross Section of Process Flow- Implantation, Diffusion -
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LSI LOGIC
LSI Logic Japan Semiconductor
PVD
Etching
Cleaning
Masking
CVD
CMP
Ion ImplantDiffusion
Process Cycle
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LSI LOGIC
LSI Logic Japan Semiconductor
Photo Resist
Si Wafer
Mask
Mercury Arc LampProjection Lens
Elliptic Mirror
Fly’s Eye Lens
Masking Process- Stepper Optics -
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LSI LOGIC
LSI Logic Japan Semiconductor
DeveloperResist
Sub.
Sub. Etching
Sub.
Exposure
Masking Process- Development -
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LSI LOGIC
LSI Logic Japan Semiconductor
Masking Process- Projected Image -
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LSI LOGIC
LSI Logic Japan Semiconductor
HF bathOxide Strip
IPA vapor bathDrying
OR bathDI water Rinse
SC-1 bathOrganic Remove
QDR bathDI water Rinse
SC-2 bathMetal Remove
H-QDR bathHot DI water Rinse
FR bathDI water Rinse
DIW
DIWCooling tube
Fil
ter
P
Fil
ter
P
Fil
ter
P
Cleaning Process - RCA Wet Station -
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LSI LOGIC
LSI Logic Japan Semiconductor
TC
Quartz TubeQuartz Boat
Wafer
Heater
Silicon chip
LampExhaust
H2, N2
O2, N2, HCl
Oxidation Process- Vertical Furnace -
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LSI LOGIC
LSI Logic Japan Semiconductor
Ion SourcePower Supply
Analyzer MagnetY-Scanning Plate
Disk
Wafer
X-Scanning PlateGas Source
Slit
Accelerator
Ion Beam
Ion Implatation Process
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LSI LOGIC
LSI Logic Japan Semiconductor
Heater
Outer Tube
Boat
Wafer
Inner TubeQuartz Cap
Reactive Gas Vacuum
LP-CVD Process( Hot Wall Type Vertical Furnace )
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LSI LOGIC
LSI Logic Japan Semiconductor
#7#6
#5
#4
#3
#2
#1
ReactorChamber
LoadlockChamber
PE-CVD Process (Dual Frequency, Multi-station Sequential Deposition)
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LSI LOGIC
LSI Logic Japan SemiconductorAP-CVD Process (Wafer Face Down, Multi-D/H Sequential Deposition)
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LSI LOGIC
LSI Logic Japan SemiconductorPVD Process- DC Magnetron Sputtering -
PowerSupply
+
Magnet
Ar+
VacuumPump
Shield
Target
Wafer
Ar+
Al or Ti
Ar Gas
Plasma Area
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LSI LOGIC
LSI Logic Japan Semiconductor
Process chamber
ANODE
CATHODE
WAFER
VACUUM PUMP
GAS [ CF4, CHF3 , Cl2 ]
RF POWER
Etching Process
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LSI LOGIC
LSI Logic Japan Semiconductor
CMP (Chemical Mechanical Polishing)
The surface of the wafer is polished by the slurry.
Wafer Carrier
Wafer
Slurry
Polishing Pad
Table
Force
Process Principle
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LSI LOGIC
LSI Logic Japan Semiconductor
Inspection Tool
Laser ParticleMonitor
Die to DieWafer Inspection
KLA2132
KLA2138
Review ToolMicroscope
KLA2608
UltrapointeLIS-1010
Leica INS-3000
In-Line SEM
JFS-9815
JWS-7500
HITACHIIS-3270
etc.
In-Line Monitoring Tools
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LSI LOGIC
LSI Logic Japan Semiconductor
Wafer Inspection
Defect Classification
Microscope SEM
Defect Map
Contact Mask
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
07/3
0 Z
8310
83X
#01
07/3
0 Z
8310
83X
#24
07/3
0 Z
8311
34X
#12
07/3
1 Z
8311
70X
#01
07/3
1 Z
8311
70X
#24
08/0
2 Z
8312
06X
#12
08/0
2 Z
8312
44X
#01
08/0
2 Z
8312
44X
#24
08/0
4 Z
8320
01X
#12
08/0
4 Z
8320
39X
#01
08/0
4 Z
8320
39X
#24
08/0
6 Z
8320
90X
#12
08/0
7 Z
8321
30X
#01
08/0
7 Z
8321
30X
#24
08/1
0 Z
8322
48X
#12
08/1
1 Z
8330
02X
#01
08/1
1 Z
8330
02X
#24
08/1
1 Z
8330
32X
#12
08/1
7 Z
8331
80X
#01
08/1
7 Z
8331
80X
#03
08/1
8 Z
8340
01X
#12
08/1
9 Z
8340
36X
#01
08/1
9 Z
8340
36X
#24
08/1
9 Z
8340
64X
#12
08/2
0 Z
8340
96X
#01
08/2
0 Z
8340
96X
#24
Date Lot Wafer
Def
ect
Den
sity
(cm
-2)
Trend Chart
In-Line Monitoring Flow 1
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LSI LOGIC
LSI Logic Japan Semiconductor
Analysis & Investigatio
n
Feedback to Root Cause
Electron Mode Ion Mode
Elemental Analysis (EDX)
Cross-Section (FIB)
In-Line Monitoring Flow 2
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LSI LOGIC
LSI Logic Japan Semiconductor
Process Trend
Lithography : KrF, ArF, F2, EUV
Metallization : Cu, Low-K
Manufacturing : 300mm, Single Wafer
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LSI LOGIC
LSI Logic Japan Semiconductor
Semiconductor Business
226.5 B$ ~ World / yr 2000
2.7 B$ ~ LSI / yr 2000