Low Voltage, Scalable Nanocrystal FLASH Memory Fabricated by Templated Self Assembly Sung Hyun Jo...

Low Voltage, Scalable Nanocrystal Low Voltage, Scalable Nanocrystal FLASH Memory Fabricated by FLASH Memory Fabricated by

Templated Self AssemblyTemplated Self Assembly

Sung Hyun JoPh.D. Student, Dept. of Electrical Engineering & Computer Science

Ken LohPh.D. Student, Dept. of Civil & Environmental Engineering

EECS 598 Nanoelectronics

October 11, 2005

Nonvolatile MemoriesNonvolatile MemoriesEECS 598 Nanoelectronics – Tuesday, Oct 11, 2005

Research MotivationResearch Motivation Nanocrystal FLASH memory offers potential advantages over

traditional FLASH devices. Improved scalability Retention Cyclability

Introduce new method for building nanocrystal FLASH memory devices that achieves precise control of nanocrystal size and position.

Dimensions are defined via polymer self assembly

Device exhibit low voltage memory operation with promising retention and endurance properties.


Background on Conventional FLASHBackground on Conventional FLASH What is FLASH memory?

Form of non-volatile EEPROM that allows multiple memory locations to be erased or written within one programming cycle

Unlike EEPROM that only allows one location to be erased/written at one time

Significant problem of limited, short lifetime for read and access Erase operation causes wear and tear of insulating oxide layer around the charge

storage mechanism

Table: Conventional FLASH Memory

Pros: Cons: Non-volatile 10,000 erase operation lifetime

Fast read/access time Size limitation

Shock resistant High power consumption


Two Main Types of Conventional FLASHTwo Main Types of Conventional FLASH NOR Flash

Each cell looks like a MOSFET transistor, except having two gates instead of one

One gate is the control gate (CG) like in other MOS transistors Second gate is the floating gate (FG) that is insulated by the oxide layer

Because the FG is insulated in an oxide layer, any electrons placed on it gets trapped and retains information

Programming the NOR flash involves starting the flow of electrons from source to drain and then applying a large enough electric field to suck them up to the FG through quantum tunneling

NAND Flash Programming methodology is different

Tunnel injection to write Tunnel release to erase

Right: iPod Nano using two 2-Gb Samsung FLASH chips


Background (1)Background (1) The trend of nonvolatile memories

Storage capability enhancement High speed Low power

Problems of conventional Flash memory scaling down

Tunneling oxide Very sensitive to defects Cycling induced defects

High operation voltage (~10V) The length scaling

Scale down

Control Gate

Source DrainChannel

Flash

Defect

ContinuousFG

e-

e-e-

e-


Background (2)Background (2) Solution for scaling down of nonvolatile memory devices

High quality tunneling oxide High-K material New nonvolatile memory technologies

FeRAM, MRAM, PCRAM … Discrete-trap memory devices

Relatively insensitive to oxide defects

Control Gate

Source DrainChannel

Discrete-Trap Memory

e-

e-

e-

e-

e-

Distributed Nodes

Defect

Control Gate

Source Drain

Channel

SONOS

e- e- e- e- e- e-

Control Gate

Source Drain

Channel

NFGM

e- e- e- e- e- e-

Nanocrystals


Background (3)Background (3)

The Advantages of Discrete-Trap Memory Scaling down of tunneling oxide (<<8nm) Low W/E voltage & low power Fast write time High endurance/reliability (reduced hot carrier effect) Long retention time (relatively insensitive to defects)

Issues Retention time versus Write time optimization Large window of threshold voltage (∆VTH)


Discrete-Trap Memory DeviceDiscrete-Trap Memory Device

Source DrainTunnel oxide

Control oxideNanocrystals

Fast read time Long retention time Low power

Compared to flash EEPROM

Case 1 : Tiwari’s structure The first proposed nanocrystal based memory device. Dot density: ~1011/cm2

Tiwari, IEDM Tech. Dig 521 1995


Discrete-Trap Memory DeviceDiscrete-Trap Memory Device

Noble E-beam lithography SOI technology Unfavorable for mass production at present

Case 2 : Guo’s structure

Si substrate

Buried oxide

Si channel

Control gate

Dot Oxide

L. J. Guo, Science, vol. 275, pp. 649-651, 1997.


Case 3 The film growth

Photo-CVD Low growth rate No plasma damage


Formation of Si NanocyrtalFormation of Si Nanocyrtal Si Nanocrystal

The TEM image

5 nm


The Variable: Deposition Time

Formation of Si NanocyrtalFormation of Si Nanocyrtal

t : 2min

t : 3min

t : 5min

Size Density

Increased depositiontime


Formation of Si NanocyrtalFormation of Si Nanocyrtal The Variable: Hydrogen dilution ratio (R = H2/SiH4)

R = 15

R = 20

R = 25

R

Size Density


A breakthrough improvement of the nanocrystal memory is expected with a material that incorporates ordered Si nano-dots of equal sizes and equal distances between them!!!


IntroductionIntroduction What Nanocrystal FLASH memory has to offer

In addition to the previously mentioned advantages… The floating gate is composed of discrete, electrically-isolated particles

Compared to a continuous film in conventional FLASH Typically formed by CVD or aerosol deposition Such nanocrystals have a wide distribution of size and position, leading to

limitations on device performance, scalability, and manufacturability

Solution: New fabrication method for building nanocrystal memories Based on a polymer self assembly process

Sets nanocrystal dimensions, density, and uniformity


Device FabricationDevice Fabrication Define Si nanocrystals using diblock copolymer thin film self-

assembly Involves spin coating a dilute polymer solution Diblock copolymer consists of:

Polystyrene (PS) Poly(methyl methacrylate) (PMMA) Molecular weight ratio produces hexagonally-close packed PMMA

cylinders in a PS matrix Annealing to promote phase separation into nanometer-scale polymer

domains PMMA is removed with an organic solvent, leaving a porous PS film Thin film used as sacrificial layer to define nanocrystals at sub-lithographic

dimensions


The Diblock CopolymerThe Diblock Copolymer Diblock copolymer composed of

polystyrene (PS) and poly(methyl methacrylate) (PMMA) – What are they?

Diblock copolymer are composed of two chemically distinct polymers

When films of diblock copolymer are annealed, nanometer-scale patterns form due to phase separation

Separations called “microdomains” can be observed

The stripe pattern is formed from repulsion between the two halves of the polymer molecules

PS / PMMA The MW ratio produces hexagonally-close

packed PMMA cylinders in a PS matrix


The PolymersThe Polymers PMMA – Poly(Methyl Methacrylate)

Form acrylic plastics used in many common products

PS – Polystyrene A liquid hydrocarbon that is commercially manufactured from petroleum


An ExampleAn Example

Example of structures produced by block copolymer nanolithographyLeft: SEM image of an array of holes (aspect ratio near unity) in a Si wafer.

Right: TM-AFM image of an array of metallic Au dots fabricated in a trilayer process.


Outline of Fabrication StepsOutline of Fabrication Steps

1) Form the porous PS film on a thermal oxide hardmask.

2) Etch PS pattern into oxide

3) Grow program oxide (2-3 nm) and conformally deposit a:Si

4) Etch a:Si using an anisotropic reactive ion etching (RIE) process


Fabrication Process IFabrication Process I Top Figure

200x200 nm SEM image of porous polymer film on silicon oxide

Indicates polymer molecules are made to self-assemble in hexagonal arrangements

Size of arrangement set by size of polymer molecules

Bottom Figure Porous polymer film on silicon oxide (after

etching of PMMA) Benefits:

This polymer is more rugged to withstand higher temperatures during fabrication

Polymer material can be easily removed


Fabrication Process IIFabrication Process II Top Figure

Si nanocrystal array Combination of depositing silicon material

and etching leaves Si nanocrystals Embedded within 20 nm region defined by

self assembled polymer matrix

Bottom Figure Dotted curve (a): dimensions of hexagonal

pattern of initial polymer layer maintained throughout

Gray curve (b): dimensions of hexagonal pattern during intermediate process

Solid curve (c): final silicon nanocrystal dimensions


Resulting a:Si NanocrystalsResulting a:Si Nanocrystals A:Si nanocrystals reproduce dimension of the original self-assembled

polymer film Diameter: 20 nm ± 10% Center-to-center spacing: 40 nm (hexagonal close-packed) Nanocrystal density: 6.5x1010/cm2

Smaller nanocrystals can be formed by employing lower molecular weight polymers

Potential source for future device scaling

Left: Example of nanocrystal formation on substrate.


How it WorksHow it Works Devices are programmed by injecting charge erased by expelling

charge from the nanocrystals Process of quantum tunneling as before Simply speaking, if the potential of the electrons are high enough, the electron

particles can tunnel through the potential energy barrier instead of being insulated by the oxide


Experimental Results


Device PerformanceDevice Performance The stored charge shifts the device flat band voltage, VFB


Device PerformanceDevice Performance A write voltage, VW, of -4 V shifts VFB by > 0.5 V. Larger VFB shifts are achieved with higher VW.

Magnitude and slope of ΔVFB vs. VW depend on the program and control oxide thicknesses


Device PerformanceDevice Performance ΔVFB saturates at high VW, when charge begins to leak through the

control oxide


Device PerformanceDevice Performance Devices with tprog = 3 nm show larger ΔVFB than tprog = 2 nm at long

write times due to larger voltage on the floating gate for the same VW


Device PerformanceDevice Performance ΔVFB increases with write time for a fixed VW

Minimum write time of 50 micro-s provides ~0.2 VFB at VW = -6 V Device A

Fully erase the devices with a 100 micro-s erase voltage (VE) pulse of +4 V


Device PerformanceDevice Performance Evaluate stability of the written and erase memory

Using VW = -6 V, VE = +4 V Measure signal capacitance at -2 V as a function of time


Device PerformanceDevice Performance Measuring device endurance

For tctrl = 2 nm

Measured using VW = -6 V, 50 micro-s, and VE = +4 V, 50 micro-s Capacitance in the two memory states was read at -2 V

Device write/erase window remains unchanged out to 109 cycles


DiscussionDiscussion Describe first nanocrystal FLASH that utilizes self-assembled

polymer film to build Si nanocrystals

This is a manufacturable solution to achieve uniformly-sized and –spaced nanocrystals

Device functions as a nonvolatile memory element ΔVFB > 0.5 V for VW < 4 V

Retention time > 106 s for program oxide as thin as 2 nm

Endurance > 109 cycles

Status and Outlook of Emerging Status and Outlook of Emerging Nonvolatile Memory TechnologiesNonvolatile Memory Technologies

Ken LohPh.D. Student, Dept. of Civil & Environmental Engineering

Sung Hyun JoPh.D. Student, Dept. of Electrical Engineering & Computer Science

EECS 598 Intro. To NanoelectronicsOct 11, 2005


Emerging Nonvolatile Memory TechnologiesEmerging Nonvolatile Memory Technologies Category

Reversible Conductance Change Conductive Bridging RAM (CBRAM)

The state change (amorphous, crystalline)

The Magneto-resistive RAM (MRAM) The magneto resistance

Phase Change RAM (PCRAM) The state change (amorphous, crystalline)

Other Ferro-electric RAM (FeRAM)

The Residual polarization in ferroelectrics


Conductive Bridging RAM (CBRAM)Conductive Bridging RAM (CBRAM) Based on a polarity-dependent resistive switching Metal/a-Si:H/Metal structure Electroforming process

Sufficient applied voltage causes atoms from the top contact to enter the a-Si:H, and leave metallic inclusions (*still controversial)

The forming process operate by diffusion

M. Jafar Phy. Rev. B vol. 49, 19, 1994

Top Metal

Bottom Metal

a-si:H


CBRAMCBRAM Voltage-current characteristic

M. Jafar Phy. Rev. B vol. 49, 19, 1994


CBRAMCBRAM Performance improvement by replacing a-Si:H as chalcogenide

glass (Ge2Sb2Te5, GST) Small device size (~100nm) High Roff/Ron ratio Retention time


Ferro-electric RAM (FeRAM)Ferro-electric RAM (FeRAM) FeRAM stores data as remnant polarization in a ferroelectric

capacitor

The hysteresis in ferroelectrics


FeRAMFeRAM Capacitor Type RAM

Destructive Read Small size is the most challenging issue


FeRAM - Scaling downFeRAM - Scaling down Conventional Problem

To obtain certain amount of polarization, the size of the capacitor is limited

(as for the planar FeRAM, size of the capacitor is ~10F2)

The capacitor on plug structure (~4F2) High aspect ratio required


Magneto-resistive RAM (MRAM)Magneto-resistive RAM (MRAM) MRAM uses magnetic moments, rather than an electric charge, to

determine the on-off state of the memory bit cell.


MRAMMRAM TMR (Tunneling Magneto Resistance)

Current

The ferromagnetic layer (Fe, Ni, Co)

The insulator layer (Al2O3 –pin hole free )

The direction of magnetic field

(a) Small Resistance (b) Large Resistance

An electron with a given spin direction can only tunnel into an empty state with the same spin direction


MRAMMRAM Magneto Tunnel Current

S. Tehrani, Proceeding of IEEE, 91, 2003, p.703


MRAMMRAM Read & Write principle

TMR (on)TMR selection (off)

Write PulseSensing Voltage


MRAMMRAM

S. Tehrani, Proceeding of IEEE, 91, 2003, p.703

The free layer of the bit is elongated in shape : Magnetic shape anisotropy creates an energy barrier


MRAMMRAM Scaling Issue

To maintain or increase the readout speed even if the bit size is reduced, it is essential that the MTJ resistance dose not increase

Decrease of barrier thickness & the barrier height (lower resistance-area)

Ferromagnetic material Today’s alloys can produce MR of 50% Replacing one electrode with a material having polarization over 90%

would increase MR to 150%


Phase Change RAM (PCRAM)Phase Change RAM (PCRAM) Based on a thermally induced reversible phase change between the

amorphous (high R) and the crystalline (small R) phase of a chalcogenide (Ge2Sb2Te5, GST)

High current & fast quenching freezes the material to amorphous state (10~30ns). Medium current for longer pulse time is used for re-crystallization

The Conceptual PRAM

GST

Vcc


PCRAMPCRAM I-V curves for the crystalline and amorphous chalcogenide

* A. Pirovano, IEEE Trans. On Elec. Dev. 51 p. 452 2004

* G.Muller, IEEE


PCRAMPCRAM Reliability

Over heating of a cell degrades the endurance

*S. Lai, IEDM Tech. Dig., 2003, p. 256


PCRAMPCRAM Issues Switching current reduction: power consumption, switching time

Reducing the contact area is essential

*S. Lai, IEDM Tech. Dig., 2003, p. 256


ComparisonComparisonFlash CBRAM FeRAM MRAM PCRAM

Maturity Product Single Cells Product Product Samples

ProductSample

Density 4Gb - 32Mb 16Mb 64Mb

Cell Size[um2] 0.025 - 0.6 1.4 0.5

Nonvolatile Yes Yes Yes Yes Yes

Random Read Access

80ns <200ns 50ns 30ns 50ns

Random Write Access

~10us

(erase 100ms)

<200ns 70ns 30ns 50ns

Destructive Read

No No Yes No No

Write Endurance

106 >105 >1012 1015 >1012

Write Voltage Vdd+~10V Vdd Vdd Vdd Vdd


ConclusionsConclusions Fabrication of Si nanocrystals feasible using diblock copolymer

PS-PMMA diblock copolymer Self-assembly technique Scalable Memory retention and endurance verified through experiments

Smaller nanocrystals can be fabricated using a similar fashion by employing different diblock copolymers

Potential technique for future scalable operations Potential candidates for emerging nonvolatile memory storage

devices CBRAM MRAM PCRAM FeRAM

Programming & Erasing MechanismProgramming & Erasing Mechanism of the Floating gate memory deviceof the Floating gate memory device

Ken Loh

Sung Hyun Jo

EECS 598 Intro. To Nanoelectronics

Oct 11, 2005


Basic Programming MechanismBasic Programming Mechanism Fowler-Nordheim (FN) tunneling

Uniform tunneling Drain side tunneling

Hot carrier injection Hot electrons (CHE) Hot holes (CHH) Modeling method

e.g. Lucky-electron model (by Shockley)


Fowler-Nordheim (FN) tunnelingFowler-Nordheim (FN) tunneling N-type on p-sub

Energy band diagram of a floating gate memory during programming by FN tunneling.


FN tunneling (during the programming)



Hot carrier injection (HCI)Hot carrier injection (HCI) Hot electron injection

Hot-hole injection is slow due to large mass and energy barrier of 4.7eV

Hot-electron injection mechanism for programming in NVM's.


Hot Carrier Injection ModelingHot Carrier Injection Modeling Lucky-electron Model (by Shockley)

A-B: The hot electron momentum has to be re-directed towards the interface. (with probability PA)

B-C: The hot electron must not suffer any energy robbing collision (PB)

C-D: The electron must not suffer any scattering due to the oxide image potential (PC)

0

effective channel length

Momentum redirection scattering mean free path

92nm

effL A B Cg ds

r

eff

r

P P PI I dx

L


Basic Erasing MechanismBasic Erasing Mechanism The net negative charge confined in the floating gate shifts the VT to

a positive value

Two methods of erasing UV emission (EPROM) FN tunneling



UV EmissionUV Emission The typical time it takes to change the VT from programmed state to

neutral or erased state is 10 minutes (EPROM)


FN tunnelingFN tunneling N-type on p-sub

Energy band diagram of a floating gate memory during erasing by FN tunneling.


FN tunneling (during the erasing)



Threshold Voltage WindowThreshold Voltage Window


Summary (1)Summary (1)


Summary (2)Summary (2)

Low Voltage, Scalable Nanocrystal FLASH Memory Fabricated by Templated Self Assembly Sung Hyun Jo...

Documents

Transcript of Low Voltage, Scalable Nanocrystal FLASH Memory Fabricated by Templated Self Assembly Sung Hyun Jo...