Asisa Kumar PanigrahyDepartment of Electronics Engineering,

National Chiao Tung University,

Hsinchu 300, Taiwan

e-mail: asisa.nist@gmail.com

Kuan-Neng Chen1

Professor

Department of Electronics Engineering,

National Chiao Tung University,

Hsinchu 300, Taiwan

e-mail: knchen@mail.nctu.edu.tw

Low Temperature Cu–CuBonding Technology in Three-Dimensional Integration: AnExtensive ReviewArguably, the integrated circuit (IC) industry has received robust scientific and techno-logical attention due to the ultra-small and extremely fast transistors since past four dec-ades that consents to Moore’s law. The introduction of new interconnect materials aswell as innovative architectures has aided for large-scale miniaturization of devices, buttheir contributions were limited. Thus, the focus has shifted toward the development ofnew integration approaches that reduce the interconnect delays which has been achievedsuccessfully by three-dimensional integrated circuit (3D IC). At this juncture, semicon-ductor industries utilize Cu–Cu bonding as a key technique for 3D IC integration. Thisreview paper focuses on the key role of low temperature Cu–Cu bonding, renaissance ofthe low temperature bonding, and current research trends to achieve low temperatureCu–Cu bonding for 3D IC and heterogeneous integration applications.[DOI: 10.1115/1.4038392]

1 Introduction

The concealed force behind the successful journey from infor-mation technology toward internet of things is the rapid progress inaccommodating more functionality with a single silicon chip. Thisimprovement in integrated circuit (IC) performance was primarilyachieved by continuously scaling down the device dimensions asper Moore’s law. ICs have essentially remained as a planar plat-form throughout the period of rigorous scaling, in the sense that thedevices and interconnects are in the same planar. Due to the fabri-cation of billions of transistors in an IC, the problem of intercon-necting has become more complex. Increase in the number ofmetal interconnect layers was a viable solution till recent past.Owing to the high density interconnects, their parasitic capacitan-ces started dominating in ICs, and this resulted in an increasedinterconnect delay which significantly reduces the system perform-ance. Off late, the interconnect delay has become on par with thetransistor delay, if not more it has become a bottleneck in furtherscaling. The need of the hour is to look for an alternative in orderto minimize the interconnect delay. One such prominent technol-ogy relies on exploring the third dimension, and it is popularlyreferred to as three-dimensional integrated circuit (3D IC) [1]. Theconcept of 3D IC integration was first anticipated in the year of1980s [2]. It offers many benefits for future deep-submicrondesigns. Such benefits include: (1) resistance–capacitance delay isimproved by vertical interconnection between adjacent stackinglayers instead of wiring different functional blocks on a planar sub-strate; (2) interconnect wire length reduction results in enhancedperformance and reduction in power consumption ability; (3)improved memory bandwidth leads to handling large amounts ofmultimedia data between packaged processors and memory; (4)realization of heterogeneous integration results in various newdesigns of high-end technologies like logic, memory, radio fre-quency, etc.; and (5) smaller form factor, which results in higherpacking density, is also able to provide more functionalities withina smaller footprint which in-turn reduces the size, power consump-tion, interconnect resistance–capacitance delay, and manufacturingcosts [3–7].

The third dimension can be achieved in various stackingoptions like wafer-on-wafer bonding, chip-on-chip bonding, andchip-on-wafer bonding [8]. These integration schemes using verti-cal bonding along with through silicon via (TSV) become the pre-ferred integration technique because of its ability to easily achieveprecise alignment [9]. It can be achieved by metal-to-metal bond-ing, oxide-to-oxide bonding, polymer-to-polymer bonding, hybridbonding, and flexible substrate-to-flexible substrate bonding[10–12]. Metal-to-Metal bonding is most preferable as it uses met-als for stacking wafers, which helps in achieving an excellentelectrical conductivity without compromising on the mechanicalstrength aspects. Among all the suitable materials for bondingmedium, Cu is the potential choice due to its impressive electro-migration resistance [13]. Besides that, it is a standard comple-mentary metal oxide semiconductor compatible material, and ifutilized as a bonding medium it can give enhanced electrical con-ductivity and ensures solid mechanical strength [14]. Furthermore,Cu–Cu thermocompression bonding is the preferred integrationtechnique, which is simple and most preferable [13,14]. The basicmechanism of bond formation in Cu–Cu thermocompressionbonding is the interdiffusion of Cu atoms and grain growth at thebonding interface due to simultaneous application of temperatureand pressure [15]. In spite of all these advantages, the main bottle-neck of Cu being a suitable bonding material for Cu–Cu is that itis easily reactive with ambient oxygen and hence it gets oxidized.Then, the oxide layer on Cu interconnects act as barrier for inter-diffusion of Cu atoms and drastically reduces the contact resist-ance after bonding. Hence, for enhancing the diffusion of Cuatoms at the interface oxide layer on top of Cu surface needs to beremoved prior to bonding. Apart from diffusion, surface rough-ness of Cu surface is also a critical requirement for high qualityCu–Cu bonding. Uneven Cu surface at the interface leads to voidand mechanically unstable grain growth during Cu–Cu bonding.Hence, both the surfaces must be flat enough for intimate contactwith mated wafers.

Instantaneous formation of oxide layer on top of Cu surface isone of the main reasons to accomplish high quality Cu–Cu bond-ing [16–18]. Above 200 �C, the oxide layer on top of the Cu sur-face becomes thermodynamically unstable and allows Cu atomsto diffuse during thermocompression cycle which leads to suc-cessful formation of grain growth at the bonding interface [19].Furthermore, the impact of postbond annealing at various temper-ature was analyzed using cross-sectional transmission electron

1Corresponding author.Contributed by the Electronic and Photonic Packaging Division of ASME for

publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received August31, 2017; final manuscript received October 28, 2017; published online March 2,2018. Assoc. Editor: Yi-Shao Lai.

Journal of Electronic Packaging MARCH 2018, Vol. 140 / 010801-1Copyright VC 2018 by ASME

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use

microscopy (TEM) analysis. The key inference from the postbondannealing enhances the interdiffusion which leads to enlargementof the grain growth up to 500 nm observed (Fig. 1) [19]. Therequirement of high temperature and pressure not only enhancesgrain growth at the interface but also increases the bond strength.However, the need of high temperature and pressure during bond-ing cycle destructs the delicate Cu interconnects and reduces the ICinterconnect performance. Therefore, there is a strong motivation toaccomplish Cu–Cu thermocompression bonding at low tempera-ture, and low pressure. This review paper focuses on variousattempts made by researchers to achieve low temperature bonding,new methodologies to achieve low temperature and low pressurebonding, mechanism of bond formation, and current trends toachieve Cu–Cu bonding at lower thermocompression cycle.

2 Low Temperature Cu–Cu Bonding Development

2.1 Surface Activated Cu–Cu Bonding. Attempts have beenmade to prevent/modify the Cu surface in order to passivate fromoxidation or remove oxide layer prior to Cu–Cu bonding. Sugaand coworkers have proposed a novel technique to modify the Cusurface in order to remove oxide layer prior to room temperatureCu–Cu surface-activated bonding (SAB) [20]. Argon (Ar) bom-bardment by the use of Ar ion beam on the Cu surface cleans theoxide content on it, and SAB can be performed at lower thermalstress even at room temperature under ultra-high vacuum (UHV)[21]. However, the critical requirement of UHV during SABmakes the process complex and not manufacturing worthy. Inaddition, the need of high energetic Ar bombardment toclean/activate Cu surface may degrade the quality of underlyingactive devices. Besides, the physical bombardment of Ar ion toactivate the Cu surface prior to bonding may damage the Cu sur-face and increase the surface roughness.

In order to overcome these issues, an additional chemicalmechanical polishing (CMP) step prior to room temperature

Cu–Cu bonding was proposed elsewhere [22,23]. For which theprerequisite is atomically smooth surface and additional CMP stepthat makes the process complicated and costly.

2.2 Cu–Cu Bonding Based on Chemical Pretreatment.Again, Suga and coworkers suggested an alternative surfaceactivation method to clean/modify the Cu surface using fluorinecontaining plasma prior to room temperature Cu–Cu bonding[24,25]. In this surface activation technique, O2 or [O2þCF4 mix-ture] gas plasma was used to activate Cu surface in a speciallydesigned reactor (Fig. 2) [24]. The major concern of this activa-tion technique is formation of quick oxidation of Cu surface due

Fig. 1 Cross-sectional TEM images of bonded interfaces at different process conditions ofannealing time [19]

Fig. 2 Plasma reactor for Cu surface pretreatment [24]

010801-2 / Vol. 140, MARCH 2018 Transactions of the ASME

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use

to the presence of oxygen gas for the creation of plasma. Currentchallenge of this technique is to make industry adoptable for lowtemperature Cu–Cu bonding.

Some researchers have proposed a technique of removal ofnative oxide from Cu surface by prebond cleaning step via wetchemistry. Employed chemistry for prebond wet cleaningincludes: acetic acid [26,27], citric acid [28], sulfuric acid [29],hydrochloric acid [30,31], and also some other combinations.However, continued immersion of the Cu interconnect sampleinside acidic solution may degrade the performance of underneathactive devices. Therefore, wet chemical pretreatment may not bean ideal mechanism to clean Cu surface as per the standards ofCMOS industry.

Based on the above reports, all the Cu–Cu bonding methodolo-gies described so far have drawbacks. Precise prerequisite ofatomically clean Cu surface and the stringent requirement ofUHV are the major concerns of SAB. Further, wet chemicaltreatment of Cu surface is not always suitable for CMOS gradedevices. Also requirement of specially designed plasma reactorfor Cu surface treatment prior to bonding is more costly and notworthy manufacturing. At the end of the day, the main objectiveis to explore a simple CMOS compatible low temperature and lowpressure Cu–Cu bonding technique.

2.3 Cu–Cu Thermocompression Bonding Using PassivationMechanisms. The key factor in ensuring successful implementa-tion of 3D IC technology is to explore a simple CMOS compatiblelow temperature and low pressure Cu–Cu bonding technique.Among all the methods, Cu–Cu thermocompression bonding ishighly favored due to feasible postbond low contact resistance,better mechanical strength, and excellent hermetic seal. It can beachieved by properly passivating the Cu surface prior to bonding.The major issue associated with Cu–Cu thermocompression bond-ing is the formation of oxide layer on Cu surface at ambient condi-tion as well as at higher temperatures. During bonding process,this native oxide acts a barrier and prevents interdiffusion of Cuacross the interface, thus necessitating higher temperature and/orpressure for achieving a reliable bonding [32–35]. However, such

higher temperature or pressure requirements for achieving qualityCu–Cu bonding may cause performance degradation, damage ofunderneath sensitive devices, and could potentially lead to reli-ability issues. Therefore, there is a strong need of low temperatureand low pressure Cu–Cu stable and reliable bonding. Variousresearchers across the globe have suggested several techniques toprevent the Cu surface in order to passivate from oxidation priorto bonding.

2.3.1 Cu–Cu Thermocompression Bonding Using SAMPassivation. The necessary condition to attain reliable low tem-perature, low pressure Cu–Cu bonding primarily lies in the degreeof preventing Cu surface from oxidation. One such technique pro-posed in the literature is to remove the surface oxide with high

Fig. 3 An illustration of the diffusion behavior and the possi-ble structure of co-sputtered Cu/Ti-bonded interconnectedunder thermal compression bonding in atmospheric bondingambient [40]

Fig. 4 Electrical characteristic comparison of bonded Cu inter-connects with Pd and Ti passivation under unbiased highlyaccelerated stress test [48]

Fig. 5 Schematic diagram of Cu-based bonding layer withmetal passivation [48]

Journal of Electronic Packaging MARCH 2018, Vol. 140 / 010801-3

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use

energetic atom bombardment and bond the Cu surface immedi-ately after the bombardment process at ultra-high vacuum at7.5� 10�8 torr. These stringent requirements make the processcomplex and costly. Another method for achieving high qualityCu–Cu bonding is by smoothening the surface (<1 nm) usingCMP. Ensuring such a low roughness every run is a highlydemanding task.

Tan et al. proposed a non-UHV and noncorrosive method topassivate the Cu surface with self-assembled monolayer (SAM)of alkane thiol and its subsequent desorption just prior to bond-ing [36]. SAM is an organic monolayer which not only passivatesthe Cu surface completely but also enhances the efficiency ofpassivation [37]. SAM formed by linear alkane-thiol atoms(CH3–(CH2)n�1–SH, n¼ number of carbon) are readily absorbedonto the Cu surface. The thiol (–SH) head bind to Cu and formpacked monolayer on the Cu surface. The methyl (–CH3) tailmakes the surface hydrophobic. Another advantage of thiol-basedSAM is to reduce already oxidized Cu layers to pure Cu alongwith passivation of the Cu surface from further oxidation. Butcomplete removal of SAM layer may require temperature near to250 �C [38]. This high temperature desorption is a major con-straint to use further reduction of bonding temperature. Further-more, room temperature desorption of SAM was also proposed toachieve bonding at 200 �C [39]. Indigenously designed nonther-mal plasma reactor was used to create Ar plasma for complete

desorption of the SAM just prior to Cu–Cu bonding. Plasma wasgenerated at room temperature under atmospheric pressure. Oneconcern of all SAM-based passivation mechanisms are ex situ andcannot be easily integrated with in-line CMOS process flow.

2.3.2 Cu–Cu Bonding Using Metal Passivation. The searchfor in-line CMOS flow compatible passivation process that isdevoid of any wet processing or surface activation technique hasled to the use of suitable metal as passivation layer. Chen et al.proposed co-sputtered Cu/Ti as bonded interconnects for 3D ICintegrations [40,41]. Also diffusion mechanism of co-sputteredCu/Ti-bonded structure was investigated. Ti was mostly found onthe sidewalls and near to the substrate surface, after wafer levelbonding at 400 �C and postbonding annealing at 400 �C for 1 h asshown in Fig. 3. However, high bonding temperature with aperiod of time does not meet the low temperature bondingrequirement.

Inspiring from the co-sputtered concept, Chen and coworkersproposed a novel bonding method at 180 �C using Ti as the passi-vation layer on Cu surface [42]. Moreover, the interdiffusionbehavior of Cu through Ti passivation layer was explained anddemonstrated using Auger electron spectroscopy [43]. Cu isknown to have the lower activation energy at the surface and thesmaller atomic volume (72 bohr3) compared to Ti vacancy volume(75.48 bohr3) [44,45]. Thus, Cu has a tendency to diffuse toward

Fig. 6 (a) XTEM imaging of bonded Cu layers with constantan passivation thickness of 2 nm,(b) substantial grain growth with no distinguishable interface and clear evidence of grainboundaries at the bonded interface (dashed white line), and (c) Atomic level XTEM imaging ofmarked region in (b) [50]

010801-4 / Vol. 140, MARCH 2018 Transactions of the ASME

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use

the bonding interface through Ti vacancies. If two wafers havingCu protected by ultra-thin Ti are brought together, the unoxidizedcopper diffuses through Ti toward the interface resulting in aCu–Cu bonding. The thickness of Ti plays a key role in the

complete process. Although a thicker Ti film can fully cover Cusurface, it may decrease the diffusivity of Cu in Ti thus requireincreased pressure conditions to achieve the bonding. Alterna-tively, very thin film may not able to passivate Cu. An optimum

Fig. 7 (a) Modified Kelvin structure fabricated for electrical characterization and (b) performed specific contactresistance curve at room temperature

Fig. 8 (a) FIB image of two (111) nt-Cu films bonded at 150 �C for 1 h, (b) FIB image of a ran-domly oriented Cu film bonded with a (111) nt-Cu film at 150 �C for 1 h, (c) FIB image of two(111) nt-Cu films bonded at 200 �C for 30 min, (d) FIB image of a randomly oriented Cu filmbonded with a (111) nt-Cu at 200 �C for 30 min, (e) FIB image of two (111) nt-Cu films bondedat 250 �C for 10 min, and (f) FIB image of a randomly oriented Cu film bonded with a (111) nt-Cu film at 250 �C for 10 min

Journal of Electronic Packaging MARCH 2018, Vol. 140 / 010801-5

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use

Ti thickness needs to be chosen that would passivate Cu andallows Cu to diffuse through Ti and reach the interface at thesame time. Recently, Panigrahi et al. demonstrated the effect ofpassivation layer thickness on Cu–Cu bonding quality, and subse-quent bonding was performed with optimized Ti passivationthickness of 3 nm at 160 �C and nominal contact pressure of2.5 bar [46,47].

Owing to the nature of fast formation of Ti oxides on surface,the contact resistance of Cu-bonded structure with Ti passivationcannot be kept as low as that from pure Cu�Cu bonding. There-fore, searching for suitable metal species for Cu passivation withsame diffusion behavior as Ti atoms becomes important. Chenand coworkers further reported that Cu–Cu bonding with Pdpassivation could be demonstrated at low temperature (150 �C)with superior electrical performance compared to Ti passivation[48,49], as shown in Fig. 4. Furthermore, reliability assessments,including current stressing, temperature cycling, and unbiasedhighly accelerated stress test were demonstrated along with inter-diffusion behavior [48]. All the metal-based passivation techni-ques proposed across the globe not only help in reducing thebonding temperature to below 200 �C but also provides reliableand quality Cu–Cu bonding. While the major concern in theTi-based passivation techniques is its fast formation of oxides onsurface, Pd passivation is a better option as metal-based passiva-tion material. The schematic diagram of Cu-based bonding layerwith metal passivation is shown in Fig. 5 [48].

2.3.3 Low Temperature Cu–Cu Bonding Using Metal-AlloyPassivation. For the passivation material on Cu surface, it is thebest if the physical properties of passivation material can be closeto Cu. Recently, authors have reported a novel passivation mecha-nism in order to passivate the Cu surface using Cu reach metalalloy, Constantan (copper–nickel alloy) and subsequent bondingwas performed at sub 150 �C with nominal contact pressure of4 bar [50]. The advantage of Constantan is that its density is lowerthan that of pure Cu (Ni has higher atomic radius of 1.49 A thanCu (1.41 A)). Added to this, Cu is known to have lower activationenergy at the surface [43]. Thus, under external stimulus such astemperature and pressure, constantan is not a hindrance for Cudiffusion. Mainly, passivation thickness plays major role toachieve high quality reliable bonding at thermal stress. The authorhas optimized the thickness of alloy on Cu surface and foundto be 2 nm for high quality bonding. Furthermore, efficacy of Cusurface passivation using constantan alloy was demonstrated thor-oughly. In addition, postbonding microstructure imaging analysiswas demonstrated using cross-sectional TEM (XTEM) imaging.Presence of fine, indifferentiable bonding, and disappearance ofinterface clearly suggests Cu–Cu bonding with optimized constantanmetal-alloy passivation is high quality and reliable [50] (Fig. 6).

Besides, specific contact resistance was measured by a modifiedKelvin structure in order to reduce possible misalignment during

bonding as shown in Fig. 7(a). The metal contact area of theCu/constantan–constantan/Cu-bonded interface is 40 lm� 40 lmwith a pitch of 70 lm. The average specific contact resistancehas been found to be 2� 10�8 X cm2 (Fig. 7(b)). Stability of thepassivated Cu-bonded structure was demonstrated using currentstressing, temperature cycling test, and relative humidity test,which suggest excellent stable bonding without electrical per-formance degradation [50].

2.4 Cu–Cu Bonding by Texturing Cu Crystal Orientation.It is reported that Cu surface diffusion coefficient on h111i ori-ented plane is faster (3–4 orders) as compared to other orientedplane at bonding interface [51]. Recently, Panigrahi et al. demon-strated an optimized Cu rich metal-alloy (Manganin) passivationtechnique that not only helps in passivate the Cu surface but alsoinherently enhanced Cu (111) oriented plane at the interfacewhich results in high quality reliable bonding at 140 �C [52].Besides, Liu et al. proposed a novel surface modification tech-nique to form nanotwinned Cu surface at the interface in order toenhance the diffusion capability during thermocompression cycleand subsequent bonding was performed at 150 ˚C with a nominalcompressive stress of 0.69 MPa [53]. Also, microstructure behav-ior of the bonded Cu–Cu interface was examined using FIB imag-ing for different deposition conditions at different bondingconditions and different deposition conditions as shown in Fig. 8.It is very much evident from the figure that bonding time dependson bonding quality which means that bonding time can be furtherreduced by increasing the bonding temperature.

Fig. 9 Scanning electron microscope (SEM) micrograph of Cu–Cu micro bump bond pads(Lannon et al. [54])

Fig. 10 Modified flip chip bonder [56]

010801-6 / Vol. 140, MARCH 2018 Transactions of the ASME

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use

3 Fine Pitch Cu–Cu Bonding

3.1 General Requirements. In actual multilayer integration,we require copper pad-to-pad bonding with intermetal dielectricinstead of simple blanket bonding. On-chip local interconnectsrequire high density interconnects which needs to be realized byvertical bonding. Cu–Cu bonding has a promising scalability, andit can give <20 lm of pitch size. Lannon et al. reported a highdensity (50 lm pitch) Cu–Cu microbump bonding at 300 �C and340 MPa of mechanical pressure using flip-chip bonder [54]. Thesamples were subjected to wet chemical pretreatment using sulfu-ric acid for surface oxide removal prior to bonding. There is aclear evidence of continuous connectivity between Cu bumps ofboth the wafers at 300 �C as shown in Fig. 9. They have also com-pared electrical and mechanical characterizations of both Cu–Cumicrobump-bonded structure with Cu–Cu/Sn microbump-bondedstructures. It was clearly proven that Cu–Cu bonds possess highermechanical strength and electrical performance as compared toCu–Cu/Sn microbump-bonded structures. The key message hereis that Cu–Cu bonding is the right direction to proceed for finepitching bonding as well. Flip chip bonding with bumps may notbe an ideal solution due to their high temperature and pressurerequirements.

3.2 Modified Tooling. Room temperature high dense bump-less Cu–Cu bonding was demonstrated using modified Flip chip

bonder [55] under UHV condition (10�7 torr) with contact load of20–25 kgf. Modified flip chip bonder was combined with the SABprocess with 0.3 lm alignment accuracy for high dense andsmaller pitch Cu–Cu bond pads. Further, Wang et al. exploredthat using a modified flip chip bonder to complete bonding pro-cess, which was performed in two steps using custom made sepa-rate chambers for each step [56]. As shown in Fig. 10, initially, Arplasma pretreatment of the Cu surface was used in order toremove the native oxide in the pretreatment chamber. Subse-quently, the samples were transferred into the bonding chamberfor flip chip bonding. The complexity in this process is quiteobvious and may be scalable to achieve high density intercon-nects. Moreover, flip chip bonding has a limitation of the numberof layers which can be stacked vertically as bumps were used forinterconnection [57].

3.3 Surface Passivation. Bump-less Cu–Cu bonding usingdamascene process flow as illustrated in Fig. 11 using SAMpassivation was demonstrated at 350 �C temperature with6.6–38.5 MPa pressure [16]. Prior to bonding, desorption of theSAM passivation layer was carried out at 250 �C. Finally, demon-stration of high density Cu–Cu bonding daisy chain with 15 lmpitch is shown in Fig. 12.

Thermocompression bonding can achieve higher density andhas minimal misalignment issues. Thus, achieving Cu–Cu finepitch bonding using low temperature and low pressure thermo-compression bonding is of great value addition. Panigrahi et al.demonstrated a novel optimized Cu rich metal-alloy (Manganin)surface passivation technique to protect the Cu surface from ambi-ent oxygen and subsequent bonding was performed at low temper-ature (190 �C) and low pressure (4 bar) [58]. The obtained highquality infrared (IR) imaging of the bonded sample signifies goodquality bonding between the Cu pads present on both the wafers,as shown in Fig. 13 [58]. Also, stability of the Cu/Manganin–Manganin/Cu pad-to-pad-bonded structure was using modifiedkelvin structure, and reliability assessment of this bonded struc-ture was investigated under multiple current stressing, temperaturecycling test, and the results indicate excellent stability withoutelectrical performance degradation

3.4 Concave-Pillar Design. Chen and coworkers recentlyreported a novel design to achieve low temperature Cu–Cu bond-ing utilizing pillar and concave on silicon substrate with and with-out polymer layer [59]. As shown in Fig. 14, during bonding, Cupillar and Cu concave initially align and then first contact only ata tiny area, resulting in plastic deformation of the Cu structure.After the plastic deformation starts, bonding involved processes,such as recrystallization and grain growth happen until the wholebonded structure achieves a well-bonded and stable one. Asshown in Fig. 15, this approach can successfully implement at sub200 �C under atmospheric pressure. The latest published resultsfrom Chen and coworkers have demonstrated this structure can be

Fig. 12 (a) Cu–Cu bonding daisy chain with 15 lm pitch and (b) cross-sectional view of daisychain using focused ion beam (FIB) imaging [16]

Fig. 11 Schematic diagram of bump-less Cu–Cu bondingusing damascene process flow [16]

Journal of Electronic Packaging MARCH 2018, Vol. 140 / 010801-7

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use

achieved by Cu–Cu bonding at 100 �C for a short time of 10 min[60].

4 Applications and Outlook for Low Temperature

Ultra-Fine-Pitch Cu–Cu Bonding

Table 1 summarizes various Cu–Cu bonding technologiesproposed/adopted by researchers and engineers. Current trend ofCu–Cu bonding is to decrease the pitch and the interconnect siz-ing for future 3D IC and heterogeneous integration technology.The target envisioned is to achieve the fine-pitch bonding for fea-ture sizes less than 10 lm. Fine tuning of the entire process maybe required to achieve low temperature and low pressure Cu–Cubond having excellent electrical characteristics. One of the criticalstudies at that juncture would be to look at electromigration inaddition to all the reliability tests. All the metal/metal-alloy-basedpassivation techniques may be extended to achieve wafer levelultra-fine-pitch Cu–Cu bonding with through silicon via integra-tion. Again the process may need a fine or coarse tuning depend-ing on the methodology adapted for TSV formation. Therequirements and constraints of the both the technologies ought tobe understood thoroughly before applying the proposed methodol-ogy for achieving vertical integration. In addition, a good align-ment approach is important to achieve fine pitch Cu–Cu bonding[61]. Recently, for example, Sony has successfully fabricated a

CMOS image sensor using Cu–Cu bonding technology [62]. TheCu–Cu-bonded vias are 3.0 lm wide and have a 14-lm pitch inthe peripheral regions. Furthermore, Tezzaron semiconductorfabricated a next generation memory device, DiRAM4TM 3Dmemory which uses die-to-wafer Cu thermal diffusion bondingtechnology [63,64]. The 3D memory is low leakage, and veryhigh density which makes memory device to operate much fasterspeed with lower power consumption in high performance logicprocess [65]. The above-mentioned applications using Cu–Cubonding technology enables the benefits of small form factor,high-density pixels, and heterogeneous integration. It is believedthat these goals will be the future trend of Cu–Cu bonding tech-nology development as well.

5 Conclusions

In conclusion, this review paper describes the need for low tem-perature Cu–Cu bonding, new methodologies to achieve low tem-perature bonding, and current research trends to achieve lowtemperature Cu–Cu bonding for 3D IC and heterogeneous integra-tion applications. Various techniques, such as surface passivation,surface cleaning, crystal orientation modification, and structuraldesign, for low temperature Cu–Cu bonding blanket, and pat-terned structures are discussed. This review paper also discussesthe current development trend and applications of Cu–Cu

Fig. 14 (a) Pillar-concave structure used in the future applica-tion of heterogeneous integration, (b) enlarged part of (a) withRDL layer linked to pillar-concave structure and TSV, and (c)the Cu pillar and Cu concave bonding process [59]

Fig. 15 SEM image of (a) Cu pillar, (b) Cu concave, (c) pillar-concave structure during bonding on silicon with polymerlayer, and (d) pillar-concave-bonded structure demonstrationon silicon with polymer layer [59]

Fig. 13 IR imaging of the bonded sample [58]

010801-8 / Vol. 140, MARCH 2018 Transactions of the ASME

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use

Table 1 Comparison among various Cu–Cu bonding technologies

Referencepaper

Bondingtemperature

Bondingpressure

Bondingvacuum Approach Short-comings

Takagi et al. [20] Roomtemperature

1 MPa 2� 10�6 Pa SAB Complex process and notmanufacturing worthy;atomically smooth surfacerequired

Tan andcoworkers [26]

250 �C 0.6 MPa 1.8� 10�4 torr Acetic acid wetprebond cleaning

Non-CMOS compatible andprolonged immersion can etchthe Cu layer

Jang et al. [27] 350 �C 2.5 MPa 10�3 torr Acetic acid wetprebond cleaning

Non-CMOS compatible,application high pressure degradethe underneath deviceperformance

Swinnen et al. [28] Notmentioned

Notmentioned

Citric acid wetprebond cleaning

Non-CMOS compatible

Huffman et al. [29] Notmentioned

Notmentioned

— Sulfuric acid wetprebond cleaning

Non-CMOS compatible

Chen et al. [30] 400 �C 0.4 MPa 10�7 torr HCl prebondcleaning

Non-CMOS compatible andprolonged immersion maycorrode the Cu layer

Chen et al. [31] 400 �C 0.4 MPa 10�7 torr Native oxide cleanby HCl

High temperature and pressurecan have a detrimental effect onactive devices also may causeperformance degradation

Peng et al. [32] 350 �C 200 KPa Not mentioned Diffusion High temperature can damagethe underneath CMOS devices

Saeidi et al. [33] 450 �C 1.55 MPa 10�4 mbar Formic gas in situpreprocessing

High temperature and pressureprocess

Wei et al. [34] 300 �C 3280 MPa Not mentioned Diffusion Excessive high pressure

Tan et al. [36,37] 250 �C 0.25 MPa 7.5� 10�5 torr SAM temporaryPassivation

High temperature process maycause damage to active devicesduring multilayer integration

Ghosh et al. [39] 200 �C 0.45 MPa 5� 10�6 mbar Nonthermalplasma-baseddesorption ofSAM

Residues of monolayer stillobserved

Chen and coworkers [42] 180 �C 1.91 MPa Not mentioned Permanent passi-vation using Ti

High contact resistance

Panigrahi et al. [46] 160 �C 0.25 MPa 5� 10�5 torr Engineered Per-manent ultra-thinTi passivation

Patterning using conventionaletching technique (plasmaetcher) and damascene process isdifficult during real multilayer3D IC integration

Chen and coworkers [48,49] 150 �C 1.91 MPa Not mentioned Permanent passi-vation using Pd

Comparably low contactresistance than Ti; LimitedApplications

Panigrahi et al. [50] 150 �C 0.4 MPa 5� 10�5 torr Engineered metalalloy (Constantan)

Very low contact resistance;Need more study prior toheterogamous

Surface passivation Integrationapplications

Panigrahi et al. [52] 140 �C 0.5 MPa 5� 10�5 torr Engineered metalalloy (Manganin)surfacepassivation

Low temperature process;need more study prior toheterogamous integrationapplications

Suga et al. [55] Room temperature 2.45 MPa 10�7 torr Modified Flip chipbonderFine-pitchbonding

Flip chip bonding approach

Peng et al. [16] 350 �C 6.6–38.5 MPa Not mentioned Ultra-fine-pitchbonding; SAMpassivation

High temperature and highpressure process may causedamage to active devices duringmultilayer integration

Chen and coworkers [59,60] Sub 200 �C Notmentioned

Atmosphericpressure

Concave-pillardesign prior to dif-fusion bonding

—

Journal of Electronic Packaging MARCH 2018, Vol. 140 / 010801-9

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use

bonding. The implementation of Cu–Cu bonding using techniquesdescribed in this review paper could have a promising impact onexisting 3D IC and heterogeneous integration.

References[1] Tan, C. S., Gutmann, R. J., and Reif, L. R., 2009, Wafer Level 3-D ICs Process

Technology, Springer Science & Business Media, New York, p. 3.[2] Akasaka, Y., 1986, “Three-Dimensional IC Trends,” Proc. IEEE, 74(12), pp.

1703–1714.[3] Chen, K. N., Chang, S. M., Fan, A., Tan, C. S., Shen, S. C., and Reif, R., 2005,

“Process Development and Bonding Quality Investigations of Silicon LayerStacking Based on Copper Wafer Bonding,” Appl. Phys. Lett., 87(3), p. 031909.

[4] Jang, E. J., Pfeiffer, S., Kim, B., Matthias, T., Hyun, S., Lee, H. J., and Park,Y. B., 2008, “Effect of Post-Annealing Conditions on Interfacial AdhesionEnergy of Cu-Cu Bonding for 3-D IC Integration,” Korean J. Mater. Res.,18(4), pp. 204–210.

[5] Chen, K. N., Tan, C. S., Fan, A., and Reif, R., 2005, “Abnormal Contact Resist-ance Reduction of Bonded Copper Interconnects in Three-Dimensional Integra-tion During Current Stressing,” Appl. Phys. Lett., 86(1), p. 011903.

[6] Ruythooren, W., Beltran, A., and Labie, R., 2007, “Morphology and BondStrength of Copper Wafer Bonding,” Ninth Electronics Packaging TechnologyConference, Singapore, Dec. 10–12.

[7] Chen, K. N., Fan, A., and Reif, R., 2004, “Morphology and Bond Strength ofCopper Wafer Bonding,” Electrochem. Solid St. Lett., 7(1), pp. G14–G16.

[8] Tan, C. S., Gutmann, R. J., and Reif, L. R., 2008, Overview of Wafer Level 3DICs, in Wafer Level 3-D ICs Process Technology, Springer, New York, pp. 1–11.

[9] Peng, L., Li, H., Lim, D. F., Gao, S., and Tan, C. S., 2008, “High-Density 3-DInterconnect of Cu–Cu Contacts With Enhanced Contact Resistance by Self-Assembled Monolayer (SAM) Passivation,” IEEE Trans. Electron. Devices,58(8), pp. 2500–2506.

[10] Lee, K. W., Nakamura, T., Sakuma, K., Park, K. T., Shimazutsu, H., Miyakawa,N., Kim, K. Y., Kurino, H., and Koyanagi, M., 2000, “Development of Three-Dimensional Integration Technology for Highly Parallel Image-ProcessingChip,” Jpn. J. Appl. Phys., 39(4S), pp. 2473–2477.

[11] Fan, A., Chen, K. N., and Reif, R., 2001, “Three-Dimensional Integration WithCopper Wafer Bonding,” Electrochemical Society Spring Meeting 2001–2002:ULSI Process Integration Symposium, Washington, DC, Mar. 24–31, pp. 124–128.

[12] Hu, Y. C., and Chen, K. N., 2016, “A Novel Bonding Approach and Its Electri-cal Performance for Flexible Substrate Integration,” IEEE J. Electron. DevicesSoc., 4(4), pp. 185–188.

[13] Save, D., Braud, F., Torres, J., Binder, F., Muller, C., Weidner, J. O., and Hasse,W., 1997, “Electromigration Resistance of Copper Interconnects,” Microelec-tron. Eng., 33(1–4), pp. 75–84.

[14] Huffman, A., Lannon, J., Lucck, M., Gregory, C., and Temple, D., 2009,“Fabrication and Characterization of Metal-to-Metal Interconnect Structures for3-D Integration,” Materials and Technologies for 3-D Integration Symposium,Warrendale, PA, Dec. 1–3, pp. 107–119.

[15] Tan, C. S., and Reif, R., 2005, “Silicon Multilayer Stacking Based on CopperWafer Bonding,” Electrochem. Solid-State Lett., 8(6), pp. G147–G149.

[16] Peng, L., Li, H., Lim, D., Lo, G., Kwong, D., and Tan, C., 2011, “High DensityBump-Less Cu–Cu Bonding With Enhanced Quality Achieved by Pre-BondingTemporary Passivation for 3D Wafer Stacking,” IEEE International Sympo-sium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu,Taiwan, Apr. 25–27, pp. 1–2.

[17] Li, Y. A., Bower, R. W., and Bencuya, I., 1998, “Low Temperature Copper toCopper Direct Bonding,” Jpn. J. Appl. Phys., 37(9A), pp. L1068–L1069.

[18] Made, R. I., Lan, P., Li, H. Y., Gan, C. L., and Tan, C. S., 2011, “Study of theEvolution of Cu-Cu Bonding Interface Imperfection Under Direct CurrentStressing for Three Dimensional Integrated Circuits,” IEEE International Inter-connect Technology Conference and Materials for Advanced Metallization(IITC/MAM), Dresden, Germany, May 8–12.

[19] Moriceau, H., Rieutord, F., Fournel, F., Di Cioccio, L., Moulet, C., Libralesso,L., Gueguen, P., Taibi, R., and Deguet, C., 2012, “Low Temperature DirectBonding: An Attractive Technique for Hetero Structures Build-Up,” Microelec-tron. Reliab., 52(2), pp. 331–341.

[20] Takagi, H., Kikuchi, K., Maeda, R., Chung, T., and Suga, T., 1996, “SurfaceActivated Bonding of Silicon Wafers at Room Temperature,” Appl. Phys. Lett.,68(16), pp. 2222–2224.

[21] Shigetou, A., Itoh, T., and Suga, T., 2006, “Bumpless Interconnect of Cu Elec-trodes in Millions-Pins Level,” IEEE 56th Electronic Components and Technol-ogy Conference (ECTC), San Diego, CA, May 30–June 2, pp.1223–1226.

[22] Tsukamoto, K., Higurashi, E., and Suga, T., 2010, “Evaluation of SurfaceMicroroughness for Surface Activated Bonding,” IEEE CPMT SymposiumJapan, Tokyo, Japan, Aug. 24–26, pp. 1–4.

[23] Wakamatsu, T., Suga, T., Akaike, M., Shigetou, A., and Higurashi, E., 2007,“Effect of SAB Process on GaN Surfaces for Low Temperature Bonding,”IEEE 6th International Conference on Polymers and Adhesives in Microelec-tronics and Photonics (Polytronic), Tokyo, Japan, Jan. 15–18, pp. 41–44.

[24] Wang, C., and Suga, T., 2010, “A Novel Room-Temperature Wafer DirectBonding Method by Fluorine Containing Plasma Activation,” IEEE 60th Elec-tronic Components and Technology Conference (ECTC), Las Vegas, NV, June1–4, pp. 303–308.

[25] Shigetou, A., Itoh, T., Sawada, K., and Suga, T., 2008, “Bumpless Interconnectof 6-lm-Pitch Cu Electrodes at Room Temperature,” IEEE Trans. Adv.Packag., 31(3), pp. 473–478.

[26] Fan, J., Lim, D. F., and Tan, C. S., 2013, “Effects of Surface Treatment on theBonding Quality of Wafer-Level Cu-to-Cu Thermo-Compression Bonding for3D Integration,” J. Micromech. Microeng., 23, p. 045025.

[27] Jang, E.-J., Hyun, S., Lee, H.-J., and Park, Y.-B., 2009, “Effect of Wet Pretreat-ment on Interfacial Adhesion Energy of Cu–Cu Thermocompression Bond for3D IC Packages,” J. Electron. Mater., 38, pp. 2449–2454.

[28] Swinnen, B., Ruythooren, W., Moor, P. D., Bogaerts, L., Carbonell, L., Munck,K. D., Eyckens, B., Stoukatch, S., Sabuncuoglu Tezcan, D., Tokei, Z., Vaes, J.,Van Aelst, J., and Beyne, E., 2006, “3D Integration by Cu–Cu Thermo-Compression Bonding of Extremely Thinned Bulk-Si Die Containing 10 lmPitch Through-Si Vias,” International Electron Devices Meeting (IEDM), SanFrancisco, CA, Dec. 11–13, pp. 1–4.

[29] Huffman, A., Lannon, J., Lueck, M., Gregory, C., and Temple, D., 2009,“Fabrication and Characterization of Metal-to-Metal Interconnect Structures for3-D Integration,” J. Instrum., 4(3), p. P03006.

[30] Chen, K., Tan, C., Fan, A., and Reif, R., 2005, “Copper Bonded Layers Analy-sis and Effects of Copper Surface Conditions on Bonding Quality for ThreeDimensional Integration,” J. Electron. Mater., 34(12), pp. 1464–1467.

[31] Chen, K., Fan, A., Tan, C., and Reif, R., 2006, “Bonding Parameters of BlanketCopper Wafer Bonding,” J. Electron. Mater., 35(2), pp. 230–234.

[32] Peng, L., Li, H. Y., Lim, D. F., Made, R. I., Lo, G.-Q., Kwong, D.-L., and Tan,C. S., 2010, “Fine-Pitch Bump-Less Cu–Cu Bonding for Wafer-on-WaferStacking and Its Quality Enhancement,” IEEE International 3D Systems Inte-gration Conference (3DIC), Munich, Germany, Nov. 16–18, pp. 1–5.

[33] Saeidi, N., Rogers, T., Draisey, A., Davies, R., Casey, D., Colinge, C., Demos-thenous, A., and Donaldson, N., 2012, “The Effects of In-Situ Formic AcidTreatment on Oxide Reduction for Copper Wafer Bonding,” AML Micro Engi-neering Ltd., Kowloon, Hong Kong.

[34] Wei, J., Nai, S. M. L., Ang, X. F., and Yung, K. P., 2009, “Advanced HighDensity Interconnect Materials and Techniques,” International Conference onElectronic Packaging Technology and High Density Packaging (ICEPT-HDP),Beijing, China, Aug. 10–13, pp. 6–13.

[35] Ang, X., Lin, A., Wei, J., Chen, Z., and Wong, C., 2008, “Low TemperatureCopper–Copper Thermocompression Bonding,” Tenth IEEE Electronics Pack-aging Technology Conference (EPTC), Singapore, Dec. 9–12, pp. 399–404.

[36] Tan, C. S., Lim, D. F., Ang, X. F., Wei, J., and Leong, K. C., 2012, “Low Tem-perature Cu–Cu Thermo-Compression Bonding With Temporary Passivation ofSelf-Assembled Monolayer and Its Bond Strength Enhancement,” Microelec-tron. Reliab., 52(2), pp. 321–324.

[37] Tan, C. S., Lim, D. F., Singh, S. G., Goulet, S. K., and Bergkvist, M., 2009,“Cu–Cu Diffusion Bonding Enhancement at Low Temperature by SurfacePassivation Using Self-Assembled Monolayer of Alkane-Thiol,” Appl. Phys.Lett., 95(19), p. 192108.

[38] Tan, C. S., and Lim, D. F., 2013, “Cu Surface Passivation With Self-AssembledMonolayer (SAM) and Its Application for Wafer Bonding at Moderately LowTemperature,” ECS Trans., 50(7), pp. 115–123.

[39] Ghosh, T., Krushnamurthy, K., Panigrahi, A. K., Dutta, A., Subrahmanyam, C., Van-jari, S. R. K., and Singh, S. G., 2015, “Facile Non Thermal Plasma Based Desorptionof Self Assembled Monolayers for Achieving Low Temperature and Low PressureCu–Cu Thermo-Compression Bonding,” RSC Adv., 5(125), pp. 103643–103648.

[40] Chen, H. Y., Hsu, S. Y., and Chen, K. N., 2013, “Electrical Performance andReliability Investigation of Co-Sputtered Cu/Ti Bonded Interconnects,” IEEETrans. Electron. Devices, 60(10), pp. 3521–3526.

[41] Chen, H. Y., Hsu, S. Y., and Chen, K. N., 2013, “Co-Sputtered Cu/Ti BondedInterconnects for 3D Integration Applications,” IEEE International Symposiumon VLSI Technology, Systems, Applications (VLSI-TSA), Hsinchu, Taiwan,Apr. 22–24, pp. 1–2.

[42] Huang, Y. P., Chien, Y. S., Tzeng, R. N., Shy, M. S., Lin, T. H., Chen, K. H.,Chiu, C. T., Chiou, J. C., Chuang, C. T., Hwang, W., Tong, H. M., and Chen,K. N., 2013, “Novel Cu-to-Cu Bonding With Ti Passivation at 180 �C in 3-DIntegration,” IEEE Electron. Dev. Lett., 34(12), pp. 1551–1553.

[43] Huang, Y. P., Chien, Y. S., Tzeng, R. N., Shy, M. S., Lin, T. H., Chen, K. H.,Chuang, C. T., Hwang, W., Chiu, C. T., Tong, H. M., and Chen, K. N., 2013,“Low Temperature (<180 �C) Bonding for 3D Integration,” IEEE International3D System Integration Conference (3DIC), San Francisco, CA, Oct. 2–4, pp. 2–4.

[44] Korzhavyi, P. A., Abrikosov, I. A., and Johansson, B., 1999, “First-PrinciplesCalculations of the Vacancy Formation Energy in Transition and Noble Met-als,” Phys. Rev. B, 59(18), p. 11693.

[45] Machlin, E. S., 2010, An Introduction to Aspects of Thermodynamics and KineticsRelevant to Materials Science, Giro Press, Croton-on-Hudson, NY, p. 251.

[46] Panigrahi, A. K., Bonam, S., Ghosh, T., Singh, S. G., and Vanjari, S. R. K., 2016,“Ultra-Thin Ti Passivation Mediated Breakthrough in High Quality Cu–Cu Bond-ing at Low Temperature and Pressure,” Mater. Lett., 169, pp. 269–272.

[47] Panigrahi, A. K., Bonam, S., Ghosh, T., Vanjari, S. R. K., and Singh, S. G.,2015, “Low Temperature, Low Pressure CMOS Compatible Cu–CuThermo-Compression Bonding With Ti Passivation for 3D IC Integration,”IEEE 65th Electronic Components and Technology Conference (ECTC), SanDiego, CA, May 26–29, pp. 2205–2210.

[48] Huang, Y. P., Chien, Y. S., Tzeng, R. N., and Chen, K. N., 2015,“Demonstration and Electrical Performance of Cu–Cu Bonding at 150 �C withPd Passivation,” IEEE Trans. Electron. Devices, 62(8), pp. 2587–2592.

[49] Huang, Y.-P., Chien, Y.-S., Tzeng, R.-N., and Chen, K.-N., 2015, “Low Tem-perature Bonding of Cu/Pd–Pd/Cu Interconnects for Three-Dimensional Inte-gration Applications,” IEEE International Interconnect Technology Conference(IITC), Grenoble, France, May 18–21.

[50] Panigrahi, A. K., Ghosh, T., Vanjari, S. R. K., and Singh, S. G., 2017,“Oxidation Resistive, CMOS Compatible Copper Based Alloy Ultrathin Films

010801-10 / Vol. 140, MARCH 2018 Transactions of the ASME

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use

as a Superior Passivation Mechanism for Achieving 150 �C Cu–Cu Wafer onWafer Thermocompression Bonding,” IEEE Trans. Electron. Dev., 64(3), pp.1239–1245.

[51] Agrawal, P. M., Rice, B. M., and Thompson, D. L., 2002, “Predicting Trends inRate Parameters for Self-Diffusion on FCC Metal Surfaces,” Surf. Sci., 515(1),pp. 21–35.

[52] Panigrahi, A. K., Ghosh, T., Vanjari, S. R. K., and Singh, S. G., 2017,“Demonstration of Sub 150 �C Cu–Cu Thermocompression Bonding for 3D ICApplications, Utilizing an Ultra-Thin Layer of Manganin Alloy as an EffectiveSurface Passivation Layer,” Mater. Lett., 194, pp. 86–89.

[53] Liu, C. M., Lin, H. W., Huang, Y. S., Chu, Y. C., Chen, C., Lyu, D. R., Chen,K. N., and Tu, K. N., 2015, “Low-Temperature Direct Copper-to-CopperBonding Enabled by Creep on (111) Surfaces of Nanotwinned Cu,” Sci. Rep.,5, p. 9734.

[54] Lannon, J. M., Jr., Gregory, C., Lueck, M., Huffman, A., Temple, D., Moll,A. J., and Knowlton, W. B., 2010, “Recent Advances in High DensityArea Array Interconnect Bonding for 3D Integration,” Proc. SPIE, 7663,p. 766305.

[55] Suga, T., Itoh, T., Zhonghua, X., Tomita, M., and Yamauchi, A., 2002, “SurfaceActivated Bonding for New Flip Chip and Bumpless Interconnect Systems,”52nd IEEE Electronic Components and Technology Conference (ECTC), SanDiego, CA, May 28–31, pp. 105–111.

[56] Wang, Y. H., and Suga, T., 2008, “20-lm-Pitch Au Micro-Bump Interconnec-tion at Room Temperature in Ambient Air,” 58th IEEE Electronic Componentsand Technology Conference (ECTC), Lake Buena Vista, FL, May 27–30, pp.944–949.

[57] Elenius, P., and Levine, L., 2000, “Comparing Flip-Chip and Wire-Bond Inter-connection Technologies,” Chip Scale Rev., 4, p. 81.

[58] Panigrahi, A. K., Kumar, C. H., Ghosh, T., Vanjari, S. R. K., and Singh, S. G.,2017, “Optimized Ultra-Thin Manganin Alloy Passivated Fine-Pitch Dama-scene Compatible Cu–Cu Bonding at Sub 200 �C for 3D IC Integration,” IEEE5th International Workshop on Low Temperature Bonding for 3D Integration(LTB-3D), Tokyo, Japan, May 16–18, p.35.

[59] Yang, Y.-T., Chou, T.-C., Yu, T.-Y., Chang, Y.-W., Huang, T.-Y., Yang,K.-M., Ko, C.-T., Chen, Y.-H., Tseng, T.-J., and Chen, K.-N., 2017, “Low Tem-perature Cu–Cu Direct Bonding Using Pillar-Concave Structure in Advanced3D Heterogeneous Integration,” IEEE Trans. Compon., Packag. Manuf. Tech-nol., 7(9), pp. 1560–1566.

[60] Ko, C.-T., Yang, K.-M., Lin, J.-W., Wang, C.-L., Chou, T.-C., Yang, Y.-T., Yu,T.-Y., Chen, Y.-H., Chen, K.-N., and Tseng, T.-J., 2017, “Study on Low Tem-perature Cu Bonding and Temporary Bond/De-Bond for RDL-First Fan-outPanel Level Package,” IEEE 5th International Workshop on Low TemperatureBonding for 3D Integration (LTB-3D), Tokyo, Japan, May 16–18.

[61] Qin, Y., Howlader, M. M. R., and Deen, M. J., 2015, “Low-Temperature Bondingfor Silicon-Based Micro-Optical Systems,” Photonics, 2(4), pp. 1164–1201.

[62] Chipworks, 2016, “Samsung Galaxy S7 Edge Teardown,” Chipworks, Ottawa,ON, Canada, accessed Nov. 15, 2017, http://www.chipworks.com/about-chip-works/overview/blog/samsung-galaxy-s7-edge-teardown

[63] Tezzaron, 2014, “2.5/3D Integrated Circuit Technology,” Tezzaron Semicon-ductor, Naperville, IL, accessed Nov. 15, 2017, https://tezzaron.com/media/Tezzaron-Presentation-Pixel-090414-for-posting.pdf

[64] AZONANO, 2015, “Tezzaron and Novati Introduce Eight-Layer 3D IC WaferStack Containing Active Logic,” AZoNetwork UK Ltd., Manchester, UK,accessed Nov. 15, 2017, https://www.azonano.com/news.aspx?newsID=33588

[65] Tezzaron, 2017, “DiRAM4TM 3D Memory,” Tezzaron Semiconductor, Naperville,IL, accessed Nov. 15, 2017, https://tezzaron.com/products/diram4-3d-memory/

Journal of Electronic Packaging MARCH 2018, Vol. 140 / 010801-11

Downloaded From: https://electronicpackaging.asmedigitalcollection.asme.org on 12/05/2018 Terms of Use: http://www.asme.org/about-asme/terms-of-use