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Low Temperature Co-fired Ceramic

(LTCC) Design Guidelines for RF 3D

Package Module Design

Purpose The purpose of this document is to give an overview of design guidelines for LTCC (Low

Temperature Co-fired Ceramic) material set.

Scope This document covers assembly and substrate design guidelines for LTCC and substrates for use

with SMD, chip and wire, and flip chip assembly.

Process Overview The ceramic modules are built by first placing the chip components using an SMT line. After the

surface mount devices are mounted to the module, the final assembly is done on the ceramic

back-end manufacturing line. The ceramic back-end process capability includes:

-chip attach and underfill

arking

Depending on the module design, some or all of these process steps may be required. For many

features, both standard and advanced design rules are given. The standard rules are generally

applicable to designs using LTCC materials. The advanced design rules may not apply to all

types of materials and approval by Amkor product management is required before advanced

rules are used.

Material Properties The following table lists typical material properties for LTCC substrates

MATERIAL CTE THERMAL

CONDUCTIVITY

[ 10-6/K]

SPECIFIC

HEAT

YOUNG'S

MODULUS

[GPa]

SHRINKAGE

(X, Y)

SHRINKAGE

(Z)

Yamamula

GCS71EAS

5.3 2.2 17% 23%

Hereaus

51555W

5.2 TBD 17% 23%

MATERIAL BENDING

STRENGTH

[MPa]

DIELECTRIC

CONSTANT

@

1MHz,R.T.

DIELECTRIC

CONSTANT

@

10GHz,R.T.

DIELECTRIC

LOSS

@

1MHz,R.T.

DIELECTRIC

LOSS

@

10GHz,R.T.

VOLUME

RESISTIVITY

[Ohmm]

Yamamula

GCS71EAS

250 7.1 TBD <30 TBD

Hereaus

51555W

TBD 7.5 TBD <10 TBD

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The coefficient of the thermal change of dielectric constant for GCS series is approximately 50ppm.

The following table lists resistivity values for common conductor materials. Ag and PdAg are

typically used for conductor traces in LTCC substrates. Au is used in plating of the co-fired top

and bottom metallization layers.

RESISITIVITY Ag PdAg Au

PATTERN METALLIZATION ≤4mΩ/sq 3.2±0.8mΩ/sq ≤10mΩ/sq

VIA METALLIZATION ≤0.02mΩ cm TBD TBD

Standard Panel Formats

MATERIAL PANEL

SIZE(A)

MAXIMUM

QUADARNT

SIZE (B)

BOARDER

MINIMUM ( C )

BOARDER

MINIMUM ( C )

LTCC 120 mm

(4.7inch)

60 mm

(2.36inch) 4 mm 4 mm

CERAMIC

DIMENSION

TOLERANCES

OUTER

PANEL

DIMENSION

PATTER

PITCH THICKNESS CAVIT

STANDARD 0.50% 0.50% 10% 2%

ADVANCED 0.25 0.25% 5% 1%

CAMBER STANDARD 0.5% / ADVANCED 0.25%

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THICKNESS AND SCORE LINE REQUIREMENTS

A B C

Unit : um DIAMOND

SCRIBE LINE DEPTH

DIAMOND

SCRIBE LINE WIDTH

SUBSTRATE

THICKNESS

GUIDELINES 0.5 C ~ 0.6 C < 50 um 200 ~ 3000

CASTELLATION SMT type packages with a side conductor stripe to facilitate inspection of the board assembly are

produced using a castellation notch on the side of the part.

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Exposed Conductor Layers

A B C D E

VIA HOLE

DIAMETER

VIA LANDING

PAD DIAMETER

TRACE

SPACING VIA PITCH

LANDING PAD

TO TRACE

SPACING

unit um mil um mil um mil um mil um mil

STANDARD 200 8 250 10 75 3 500 20 100 4

ADVANCED 100 4 150 6 50 2 250 10 70 3

* Next Stage: Trace Width 25um, Trace Spacing 25um & Via Hole Diameter 30um

F G G H H

TRACE WIDTH

TRACE TO

PACKAGE

EDGE

TRACE TO

CAVITY

EDGE

LANDING PAD

TO PACKAGE

EDGE

LANDING PAD

TO CAVITY

EDGE

unit um mil um mil um mil um mil um mil

STANDARD 80 3 250 8 75 3 500 20 100 4

ADVANCED 50 2.5 100 4 50 2 100 8 70 3

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Buried Conductor Layers

A B C D E

VIA HOLE

DIAMETER

VIA LANDING

PAD DIAMETER

TRACE

SPACING VIA PITCH

LANDING PAD

TO TRACE

SPACING

unit um mil um mil um mil um mil um mil

STANDARD 200 8 250 10 75 3 500 20 100 4

ADVANCED 100 4 150 6 50 2 250 10 70 3

F G G H H

TRACE WIDTH

TRACE TO

PACKAGE

EDGE

TRACE TO

CAVITY

EDGE

LANDING PAD

TO PACKAGE

EDGE

LANDING PAD

TO CAVITY

EDGE

unit um mil um mil um mil um mil um mil

STANDARD 80 3 300 8 75 3 500 20 100 4

ADVANCED 50 2.5 100 4 50 2 100 8 70 3

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Ceramic Flip Chip VIA Technology

All Dimensions Unit : um / mil

Power/Ground

Plane VIAs A B C C D

VIA Hole

Diameter

VIA Capture

PAD

Isolation Gap

with Via in

Upper Layer

Isolation Gap

Without Via in

Upper Layer

Package

Edge to

Plane Edge

STANDARD 200 / 8 300 / 12 200 / 8 150 / 6 400 / 16

ADVANCED 95 / 4 155 / 6 100 / 4 80 / 3 300 / 12

Power/Ground

Plane VIAs D E E F

Cavity Edge

To Plane Edge

Package

Edge to VIA

Cavity Edge

to VIA

Minimum

Solid Plane

STANDARD 300 / 12 300 / 12 300 / 12 100 / 4

ADVANCED 200 / 8 200 / 8 200 / 8 80 / 3

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SMD LAYOUT NON-SOLDERMASK DEFINED

COMPONENT SIZE

(All Dimensions

Unit : um / mil)

A B C D E COMPONENT

PAD LENGTH

MINIMUM

COMPONENT

PAD SPACE

MAXIMUM

COMPONENT

PAD WIDTH

MINIMUM

COMPONENT

SOLDERMASK

PULL-BACK

MINIMUM*

SOLDERMASK

TO TRACE

MINIMUM **

CHIP SIZE 2012 (0805) 930 / 37 840 / 33 1200 / 48 75 / 3 100 / 4

CHIP SIZE 1508 (0603) 700 / 28 700 / 28 800 / 32 75 / 3 100 / 4

CHIP SIZE 1008 (0403) 325 / 13 500 / 20 700 / 28 75 / 3 100 / 4

CHIP SIZE 1005 (0402) 325 / 13 500 / 20 450 / 18 75 / 3 100 / 4

CHIP SIZE 0603 (0201) 275 / 11 325 / 13 275 / 11 75 / 3 100 / 4

CHIP SIZE 0402 (01005) 75 / 3 100 / 4

COMPONENT SIZE

(Alll Dimensions

Unit : um / mil)

F G H J K SOLDERMASK

WEB

MINIMUM

COMPONENT

TO

COMPONENT

MINIMUM

***

COMPONENT

PAD TO

PACKAGE

EDGE

MINIMUM

COMPONENT

PAD

TO DIE FLAG

MINIMUM

****

SMETAL TO

METAL

MINIMUM

CHIP SIZE 2012 (0805) 150 / 6 600 / 24 200 / 8 500 / 20 75 / 3

CHIP SIZE 1508 (0603) 150 / 6 500 / 20 200 / 8 350 / 14 75 / 3

CHIP SIZE 1008 (0403) 150 / 6 300 / 12 200 / 8 300 / 12 75 / 3

CHIP SIZE 1005 (0402) 150 / 6 300 / 12 200 / 8 300 / 12 75 / 3

CHIP SIZE 0603 (0201) 150 / 6 250 / 10 200 / 8 300 / 12 75 / 3

CHIP SIZE 0402 (01005) 150 / 6 200 / 8 250 / 10 75 / 3 * VIOLATING THIS GUIDELINE MAY RESULT IN YIELD HIT.

** UNLESS TRACE CAN BE EXPOSED BY DESIGN.

*** IF TWO DIFFERENT SIZE COMPONENTS ARE NEXT TO EACH OTHER THEN AN AVERAGED "G"

DIMENSION WILL BE USED.

**** IF DIE HAS BONDING WIRES ON THE COMPONENT SIDE SEE PAGE xx (CASTELLATION).

*****008004 soldering pad (SMT)design and testing is under developing ,will be completed by Q2 end of 2014

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SMD LAYOUT SOLDERMASK DEFINED

COMPONENT SIZE

(All Dimensions

Unit : um / mil)

A B C D E COMPONENT

PAD LENGTH

MINIMUM

COMPONENT

PAD SPACE

MAXIMUM

COMPONENT

PAD WIDTH

MINIMUM

COMPONENT

SOLDERMASK

OVERLAY

MINIMUM*

COMPONENT

METAL TO

TRACE

MINIMUM

CHIP SIZE 2012 (0805) 930 / 37 840 / 33 1200 / 48 50 / 2 75 / 3

CHIP SIZE 1508 (0603) 700 / 28 700 / 28 800 / 32 50 / 2 75 / 3

CHIP SIZE 1008 (0403) 325 / 13 500 / 20 700 / 28 50 / 2 75 / 3

CHIP SIZE 1005 (0402) 325 / 13 500 / 20 450 / 18 50 / 2 75 / 3

CHIP SIZE 0603 (0201) 275 / 11 325 / 13 275 / 11 50 / 2 75 / 3

COMPONENT SIZE

(All Dimensions

Unit : um)

F G H J K SOLDERMASK

WEB

MINIMUM

COMPONENT

TO

COMPONENT

MINIMUM **

COMPONENT

PAD TO

PACKAGE

EDGE

MINIMUM

COMPONENT

PAD

TO DIE FLAG

MINIMUM ***

METAL TO

METAL

MINIMUM

CHIP SIZE 2012 (0805) 150 / 6 600 / 24 200 / 8 500 / 20 75 / 3

CHIP SIZE 1508 (0603) 150 / 6 500 / 20 200 / 8 350 / 14 75 / 3

CHIP SIZE 1008 (0403) 150 / 6 300 / 12 200 / 8 300 / 12 75 / 3

CHIP SIZE 1005 (0402) 150 / 6 300 / 12 200 / 8 300 / 12 75 / 3

CHIP SIZE 0603 (0201) 150 / 6 250 / 10 200 / 8 300 / 12 75 / 3 * VIOLATING THIS GUIDELINE MAY RESULT IN YIELD HIT.

*** IF TWO DIFFERENT SIZE COMPONENTS ARE NEXT TO EACH OTHER THEN AN AVERAGED "G"

DIMENSION WILL BE USED.

**** IF DIE HAS BONDING WIRES ON THE COMPONENT SIDE SEE PAGE xx (CASTELLATION).

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SMD WIRE BONDING Wire Bonding Type

COMPONENT

HEIGHT

(All Dimensions

Unit : um / mil)

MINIMUM DISTANCE (D1)

FROM BOND FINGER TO

COMPONENT (BONDING

AWAY FROM COMPONENT)

MINIMUM DISTANCE (D2 )

FROM BOND FINGER TO

COMPONENT (BONDING

TOWARD COMPONENT)

MINIMUM DISTANCE (D3 )

FROM BOND FINGER TO

COMPONENT

200 / 8 375 / 15 175 / 7 175 / 7

300 / 12 475 / 19 275 / 11 275 / 11

400 / 16 500 / 20 300 / 12 300 / 12

500 / 20 550 / 22 350 / 14 350 / 14

600 / 24 575 / 23 375 / 15 375 / 15

700 / 28 600 / 24 400 / 16 400 / 16

800 / 32 650 / 26 450 / 18 450 / 18

900 / 36 700 / 28 500 / 20 500 / 20

1000 / 40 750 / 30 550 / 22 550 / 22

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DIE BONDING

All

Dimensions

Unit :um/mil

A A B C D E F Die Edge to

Die Flag (Die

Thickness

< 100)

Die Edge to

Die Flag (Die

Thickness

> 100)

Die Flag to Bond Finger

Die Flag

Solder Mask

Pullback

Maximum

Wire

Length

Minimum

Wire

Separation On

Stitch Bond

Maximum

Wire

Angle

STANDARD 100 / 4 150 / 6 150 / 6 75 / 3 28 / 1 75 / 3 45 Degrees

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Wire Bonding Options

All Dimensions

Unit : um / mil

A B C E

Down Bond

Length

Down Bond

Length

Die Edge to

Die Flag Edge

Wirebond Pad

Edge to VIA

Pad Edge

"D" Die Thickness <10 330 / 13 250 / 10 Down Bond Length + 100 300 / 12

"D" Die Thickness >100 - 200 380 / 15 250 / 10 Down Bond Length + 100 300 / 12

"D" Die Thickness >200 - 300 430 / 17 250 / 10 Down Bond Length + 100 300 / 12

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EMBEDDED COMPONENTS

A、Inductor Designs：Minimum space acceptable up to 100um

B、Layout Drawing Dimensions for Embedded Capacitors Capacitor plates, as large areas of conductors, are acceptable up to 5mm square. Adjacent capacitor

plates at maximum size, must be separated by a space equal to the size of the capacitor plate.

Maximum conductor coverage is 50% of substrate area.

Capacitors are processed using standard screen printing techniques and fired directly onto any layer

of the substrate.

They may also be buried within or on top of multilayer structures. Electrodes must be of the same

material.

Typical dielectric thickness is 40 um(minimum). Capacitor tolerance is typically ± 30%. Design

options are available to reduce tolerances.

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C、Layout Drawing Dimensions for Embedded Resistors Embedded resistors are available with fired tolerances of 30%, with good tracing to adjacent

resistors. The following table is a list of available materials for buried resistors.

Ink for Printing Ohms per Square

Level R 1 50 Ω

Level R 2 100 Ω

Level R 3 1K Ω

Level R 4 10K Ω

Level R 5 100K Ω

All Dimension

Unit : um / mil

LENGTH

MAXIMUM

LENGTH

Minimum

WIDTH

MAXIMUM

WIDTH

Minimum

Overlap

Minimum

10,000 / 400 200 / 8 10,000 / 400 200 / 8 100 / 4

Standard resistor materials are made from glasses and metal oxides of ruthenium metal. Sheet

resistivities are available from milliohms to gigaohms and can be combined on a single substrate.

Standard trim tolerances are 10% through 1%, and in some cases to 0.5%. Large numbers of

minimum size resistors on a substrate may limit the tolerance to 5% to 10% due to yield considerations.

Typical Resistor Characteristics Sheet Resistivities (ohms/square)

Range 1 10 100 1K 10K 100K 1M 10M

TCR (PPM/C)

Maximum ±300 ±300 ±300 ±300 ±300 ±300 ±300 ±300

Typical 100±200 100±200 100±200 100±200 0±200 0±200 0±200 0±200

Maximum Rated Power Dissipation (mW)

Al2O3 Base 500 575 750 500 400 275 10 10

AlN Base

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Ceramic Flip Chip Via Technology ( All Dimensions Unit : um)

All Dimension Unit : um / mil Die Size

Flip Chip VIAs and

PADs ≧1,000 um

A A B B C D Top VIA

Diameter

Bottom VIA

Diameter

VIA Capture

PAD Top

VIA Capture

Pad Bottom

Bottom PAD

With no VIA

Minimum

PAD Pitch

STANDARD 125 / 5 75 / 3 175 / 7 125 / 5 100 / 4 225 / 9

ADVANCED 80 / 3 70 / 3 150 / 6 120 / 5 75 / 3 200 / 8

Die Size

Flip Chip VIAs and

PADs ≦ 1,000 um

A A B B C D Top VIA

Diameter

Bottom VIA

Diameter

VIA Capture

PAD Top

VIA Capture

Pad Bottom

Bottom PAD

With no VIA

Minimum

PAD Pitch

STANDARD 125 / 5 75 / 3 175 / 7 125 / 5 100 / 4 225 / 9

ADVANCED 80 / 3 70 / 3 150 / 6 120 / 5 75 / 3 200 / 8

* LTCC flip chip metal for attaching die with copper pillar is under developing,will be completed by Q3

of 2014

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FLIP CHIP DIE PLACEMENT

All Dimension

Unit : um / mil

A B C DIE EDGE TO

PACKAGE EDGE

DIE EDGE TO

COMPONENT PAD

DIE TO DIE

SPACING

STANDARD 2000 / 80 2500 / 100 3000 / 120

ADVANCED 1500 / 60 2000 / 80 2500 / 100

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LGA PADS NON-SOLDERMASK DEFINED

All Dimension Unit : um / mil

A B C D E F

LGA PAD Pitch

LGA PAD Size

LGA PAD to

Package Edge

Minimum

LGA Solder Mask

Pull-Back

Minimum

LGA Solder Mask

WEB Minimum

LGA PAD to

Ground Plane

Minimum

500 / 20 300 / 12 100 / 4 75 / 3 150 / 6 250 / 10

750 / 30 300 / 12 100 / 4 75 / 3 150 / 6 250 / 10

800 / 32 400 / 16 100 / 4 75 / 3 150 / 6 250 / 10

100 / 4 400 / 16 100 / 4 75 / 3 150 / 6 250 / 10

1270 / 51 630 / 25 100 / 4 75 / 3 150 / 6 250 / 10

1500 / 60 1170 / 47 100 / 4 75 / 3 150 / 6 250 / 10

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LGA PADS SOLDERMASK DEFINED

All Dimension Unit : um / mil

A B C D E F

LGA PAD Pitch

LGA PAD Size

LGA PAD to

Package Edge

Minimum

LGA Solder Mask

Over-Lay

Minimum

LGA Solder Mask

WEB Minimum

LGA PAD to

Ground Plane

Minimum

500 / 20 430 / 17 100 / 4 75 / 3 200 / 8 250 / 10

750 / 30 430 / 17 100 / 4 75 / 3 200 / 8 250 / 10

800 / 32 550 / 22 100 / 4 75 / 3 200 / 8 250 / 10

1000 / 40 550 / 22 100 / 4 75 / 3 200 / 8 250 / 10

1270 / 51 800 / 32 100 / 4 75 / 3 200 / 8 250 / 10

1500 / 60 1000 / 40 100 / 4 75 / 3 200 / 8 250 / 10

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BGA PADS NON-SOLDERMASK DEFINED

All Dimension Unit : um / mil

A B C D

BGA PAD Pitch BGA PAD Size BGA Solder Mask

Open Size

BGA PAD to

Package Edge

500 / 20 300 / 12 450 / 18 200 / 8

750 / 30 300 / 12 450 / 18 200 / 8

800 / 32 400 / 16 550 / 22 200 / 8

1000 / 40 400 / 16 550 / 22 200 / 8

1270 / 51 630 / 25 800 / 32 200 / 8

1500 / 60 630 / 25 800 / 32 200 / 8

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BGA PADS SOLDERMASK DEFINED

All Dimension Unit : um / mil

A B C D

BGA PAD Pitch BGA PAD Size BGA Solder Mask

Open Size

BGA PAD to

Package Edge

500 / 20 430 / 17 200 / 8 250 / 10

750 / 30 430 / 17 200 / 8 250 / 10

800 / 32 550 / 22 200 / 8 250 / 10

1000 / 40 550 / 22 200 / 8 250 / 10

1270 / 51 800 / 32 200 / 8 250 / 10

1500 / 60 1000 / 40 200 / 8 250 / 10

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Encapsulation The minimum clearance from the top of the highest component or wire loop to the top of the

encapsulation is 250 um minimum.

When metal shields for EMI/RF requirements are part of the design, consult the design guidelines

for shields. Future additions will include guidelines for layout design when using transfer molding as the

method of encapsulation.

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CAVITY PACKAGE DESIGN

All Dimension

Unit : um / mil

A B C D E Minimum

Base

Thickness

Minimum

Cavity

Depth

Shelf

Thickness

Bond Shelf

Height

Die Edge to

Cavity Edge

Minimum

STANDARD 400 / 16 160 / 6 80 / 3 125 / 5 200 / 8

ADVANCED 300 / 12 80 / 3 40 / 1.5 120 / 5 100 / 4

All Dimension

Unit : um

F G H J Bond Shelf

Width

Minimum

Die

Thickness

Bond Line

Thickness

BGA/LGA to

Cavity Edge

Minimum

STANDARD 500 / 20 TBD TBD 400 / 16

ADVANCED 300 / 12 TBD TBD 400 / 16

* Cavity to Cavity Edge Minimum: 300um / 12mil @ LTCC thickness 200um

** Cavity to Cavity Edge Minimum: 520um / 21mil @ LTCC thickness 600um