Low power project_presentation
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![Page 1: Low power project_presentation](https://reader036.fdocuments.us/reader036/viewer/2022082513/557d3df3d8b42ac2788b50cd/html5/thumbnails/1.jpg)
CLOCK GATING OF
LINEAR FEEDBACK SHIFT REGISTERS
RICHU JOSE CYRIACM120128EC
MICROELECTRONICS AND VLSI DESIGN
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Traditional LFSR•LFSR is used to pseudo random bit
generator.
•It is usually a shift register with some flip-flop outputs XOR ed and fed back into the first flip-flop.
Simplified circuit of a generic n-bit LFSR[1]
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Traditional LFSR…..(contd)
01 0 01 00111
1100, 1100, 1110, 1111, 0111, 1011, 0101, 1010, 1101, 0110, 0011,1001, 0100, 0010, 0001, 1000,1100…….
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Gated clock design of LFSR
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Gated clock design of LFSR…(contd)
XOR AND GATE[1]
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CLOCK GATED OUTPUT
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CONCLUSION
•Reduction in power is about 10% after applying clock gating in LFSR.
•There is an overhead of 12 transistors per clock gating circuit and it also dissipates power.
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References•Walter Aloisi and Rosario Mita, Member,
IEEE, “Gated clock design of Linear Feedback Shift Register,” Ieee transactions on circuits and systems—ii: express briefs, vol. 55, no. 6, JUNE 2008
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THANK YOU