Low Frequency Process for Silicon On Insulator DeepReactive Ion Etching

M. Wasilik, A.P. Pisano

ABSTRACT

Due to the inherently non-uniform etching effects in the standard DRIE (Deep Reactive Ion Etch) process, a newtechnique has been developed specifically for SOI (silicon on insulator) etching. The new system embodies a separateLF power supply that is pulsed when being applied to the platen during the etch cycle. This lends itself to assisting in thereduction of ionic charging at the insulator layer in deep trenches. Consequently, notching or “footing” of Si structures isdisallowed. From this a decrease in over etch sensitivity emerges, with the end result being the ability to produce high-quality, large aspect ratio structures.

Si etch rates in the same DRIE process may differ due to three basic effects: Aspect ratio dependent etch (ARDE),microloading (RIE-lag), and the general loading effect by which edges of the substrate etch faster than the center. Whenetching to a buried insulating layer these effects tend to indirectly encourage footing. The purpose of the researchinvolved was to find optimal process parameters that would minimize footing. Factorial design of experiment techniquewas used to accomplish this in a two step process. First, main and second order effects on etch-rate uniformity werestudied. Then, once supplied with process parameters that minimize uniformity effects, parameter settings that minimizefooting were found. The end result is a purse of optimized DRIE-SOI recipes that produce superb high-aspect ratioSilicon structures.

KEYWORDS

SOI, low frequency, DRIE, Footing, Notching

INTRODUCTION

The notching or “footing” effect can be a negative aspect of the standard deep reactive ion etch (DRIE) process1 whenetching anisotropic, high aspect ratio structures on SOI (Silicon on Insulator) substrates. Once the device layer of silicon

FIGURE 2absence of footing on SOI wafer using STS’ LF

upgrade option

FIGURE 1footing on SOI wafer as the result of a

conventional HF DRIE process

has been etched and the insulating layer (typically SiO2) reached, an accumulation of positively charged ions at theinsulator surface attack the surrounding silicon2. This effect is known as notching or footing. In FIGURE 1 this effect isclearly depicted as a side-effect of the conventional DRIE process. The silicon structures shown here measureapproximately 3.5µ wide and 50µ deep, with 5µ wide separating spaces. The overetch (calculated as the additionalpercentage time of the required etch time to reach the oxide) of the columns in FIGURE 1 was determined to be under5%, yet the width of the notches shown has already grown substantially large (> 1µ). Conversely, FIGURE 2 shows 2,4, 6, 8, and 10µ wide trenches 50µ deep processed with Surface Technology Systems’3 LF (low frequency) SOI option.There is no perceptible footing here even though a 14% overetch was performed.

For SOI substrates, the conventional DRIE process contains many aspects that lead to footing4-7. Surface TechnologySystems’ conventional multiplex ASE™ (Advanced Silicon Etch) system uses an ICP (Inductively Coupled Plasma) forthe required high density plasma. The power supply for the ICP coil operates at a relatively high frequency (HF) of13.56 MHz. Likewise, the electrode or platen that provides the bias for directional etching in the conventional ASE™system also operates at 13.56 MHz. The HF supply for the platen invariably promotes footing in SOI substrates.Unfortunately, the ions are too slow to respond directly to the applied HF voltage on the platen. Rather they aregoverned by an average d.c. (direct current) potential. For SOI substrates, positive ions will consequently be engaged ina continuous manner during the entire etch cycle by charging at the oxide layer. These ions accumulate and eventuallyrepel from one another resulting in the bombardment and attack of the surrounding silicon medium.

Methods have been previously reported that aid in the riddance or completely eliminate the footing phenomena. Someinclude incorporating an additional conductive layer to stop charging8-9. Other methods have shown that by replacingthe HF platen power supply with a relatively low frequency (LF) supply10, footing could be reduced. Furthermore,switching the platen supply on and off during the etch cycle has also been shown to reduce notching11. STS hasincorporated the latter two of these techniques in the SOI LF option system. The LF option kit comprises an LF powersupply which operates at 380 kHz, and a pulsing generator that switches the platen on and off during the etch cycle. Ionsnow are allowed to respond to the LF applied voltage bias on the platen, and may charge and release corresponding tothe pulse setting during the etch cycle. The wider ion distribution is advertised to reduce charging effects, and the benefitis a substantial reduction in footing for SOI substrates.

Overetch is one of the main concerns when processing SOI substrates. The ASE process invariably embodies uniformityeffects that necessitate an overetch, and consequently a degradation of silicon at the insulator surface. There are 3 (three)major uniformity effects that materialize from the DRIE ASE process. They are generally known as the bullseye effect,ARDE, and microloading or RIE lag.

The bullseye effect is a cross-surface substrate etch rate discordance. The edges of the wafer will tend to etch faster thanthe center. A circular succession of differential etch rate rings leading into the center of the substrate nets the termbullseye. The effect is caused by a relative abundance of desorbed product per unit area being released near the center ofthe wafer. Reactant is able to reach features at the edges of the substrate more readily, and thus produce the relativelyfaster etch rate. On an SOI substrate the oxide will be reached at the edges faster, and thus footing will be more likely totranspire here while the overetch for features near the center of the wafer is undertaken.

Aspect ratio dependent etch, also known as ARDE, is the differential etch rate effect observed when smaller spaces tendto etch slower than relatively larger spaces. This is due to a diminished transport capacity of reactant and ionicbombardment into the smaller trenches. Hence in a typical SOI ASE process larger trenches will hit the oxide soonerthan the smaller trenches. Conventional HF ASE processing will cause footing to occur in these large trenches while theoveretch is carried out for the smaller trenches.

Microloading12 is the circumstance by which isolated spaces on the substrate etch faster than spaces located in a densearray. Conversely, isolated lines will be completed (i.e. the oxide surface will be reached ) more slowly than lines in adense array. The effect is due simply to more reactant being consumed in the higher area silicon regions. Assuming auniform flux of reactant provided across the wafer per unit time, dense arrays of trenches will present a higher load tothe etch rate. Isolated trenches will retain a relatively larger flux supply of reactant, and thus a higher etch rate.

Naturally, footing is more likely to take place in the isolated spaces, as they will reach the insulator layer before thedense array features.

If all of the patterned spaces on an SOI substrate are to reach the oxide layer, these uniformity effects demand anoveretch in process time. Therefore it is required that certain areas of the substrate repudiate charging and thesuccession of footing while the etch depth of other features is catching up.

PROCESS DEVELOPMENT: PHASE I

An STS LF SOI upgrade kit was installed at the STS DRIE multiplex located at the UC Berkeley MicrofabricationLaboratory. STS developed the SOI kit to work in conjunction with the conventional HF ASE system. Regular HF ASEprocessing is still available with the upgrade. The new LF system parameters were characterized, and thereuponoptimized to produce minimal uniformity effects on customary silicon substrates. This portion of the research will bereferred to as phase I of the experiment. Following phase I the determination of the amelioration of footing on SOIsubstrates was completed. Furthermore, different LF parameter combinations were explored with the results beingreported in this paper. This portion of the research will be referred to as phase II of the experiment.

Phase I Experiment

Phase I of the research consisted of a fractional factorial experiment13 to assess main and second order effects of the newLF process. MINITAB™ statistical software14 was used to aid in the design of experiment. A two level (hi and lo), sixfactor, single replicate, resolution IV type factorial design was chosen. Uniformities, etch rates, and other occurrenceswere then observed as responses to the experiment. New LF parameters as well as conventional HF parameters werechosen as factors for the experiment. 16 (sixteen) runs were performed. In the resolution IV type fractional factorial,higher order effects are aliased, so it is assumed that 3rd order effects (and greater) are negligible. Also in resolution IVexperiments some 2nd order effects are aliased. So, the order of variables were set up accordingly to allow the study of2nd order effects of interest. In FIGURE 3 the alias structure for the fractional factorial design is represented along withthe factors (variables) used.

In TABLE 1, the designation of the high and low levels of the experiment variables are shown. The 2 (two) variablesDuty Cycle and Period are exclusive to the new LF SOI process. The remaining parameters however are common toboth the LF and HF processes. Pressure of the process chamber was held at 20 and 45 milli Torr. Duty Cycle denotes thepercent of the on time in the pulsing cycle. Low and high levels Duty Cycle were held at 25 and 50% respectively.Period is the total time of the pulsing cycle, and was held at 10 and 20 milli seconds. APC refers to the automatic

TABLE 1 TABLE 2

LO HIPressure 20 mTorr 45 mTorr

Duty Cycle 25% 50%Period 10 ms 20 msAPC automatic manual

Flow Rates 150/125 120/100Cycle Times 6.7etch/5pass 16etch/12pass

FIGURE 3variables and alias structure

A = Pressure D = APCB = Duty Cycle E = Flow Rates

C = Period F = Cycle Times

I + ABCE + ADEF +BCDF SOIDOE Pass EtchRFp (Watt) 0 10RFc (Watt) 600 600C4F8 (sccm) 120/150 0O2 (sccm) 0 10/12.5SF6 (sccm) 0 100/120Cyctime (sec) 5/12 6.7/16Overrun (sec) 0.5 0.5APC (%) variableProcess Time 15 minuteschiller temp 20 Cfrequency LF - 380 kHzpulse variable

pressure control option of the STS system. The Automatic set level adjusts a valve via feedback control to obtain a targetprocess pressure in the chamber. When held to the Manual level, the valve is set at a fixed angle. Moreover, The fixedangle was predetermined to allow for the target pressure level listed in TABLE 1. Flow Rates were held at ratios, thelow level being 150 sccm for C4F8, and 125 sccm for SF6. The high level for Flow Rates was held at 120 sccm for C4F8,and 100 sccm for SF6. Cycle Times were also held at high and low levels of ratios. The low level was held at 6.7 secondsfor the etch time (SF6 step), and 5 seconds for the passivation time (C4F8 step). The high level was held at 16 seconds forthe etch time (SF6 step), and 12 seconds for the passivation time (C4F8 step). It should be noted that the interactionamong the ASE HF process parameters mentioned has been previously explored15. How these parameters react with thenew LF constituents however was unclear, and thus concentrated upon within the scope of this research.

In TABLE 2 the recipe for the phase I experiment is shown. The power for the platen (electrode) was set at 10 watts forthe etch cycle (off during the passivation cycle). The coil power for the ICP was set to 600 watts for both etch andpassivation cycle. A 10% of the SF6 flow of oxygen was introduced into each etch cycle. This component is normallyplaced in all recipes on the STS etcher at the UC Berkeley Microlab to reduce sulfur buildup in the pump apparatus ofthe system. The overrun times of 0.5 seconds for each cycle is defined as the time whereby the etch cycle overlaps thepassivation cycle and vise versa.

Each process was run for 15 minutes. The order of the 16 runs was randomized. The chiller for the electrode was set to20 C. As previously mentioned, the new LF system uses a 380 kHz power supply for the platen. Naturally, each run wasset to LF mode. The pulse generator unit then switches the supply on and off during each etch cycle, and was setaccordingly for each run. The same mask pattern was used for each wafer, so as to provide consistency in the amount ofexposed silicon load. The experiments were carried out upon test grade n-type silicon wafers. The patterned mask was2µ thick g-line OCG-825 photoresist. The resist was UVbaked, which is a process that uses both high intensityultraviolet light and a heat to respectively cross-link and harden patterned photoresist. UVbake resist exhibits a highresistance to sputtering and therefore better selectivity than conventionally hard baked resist.

Additionally, before the experiments were performed a 30 (thirty) minute condition process was run. The conditionprocess consisted of a standard 10 minute oxygen plasma clean recipe followed by a standard 20 minute ASE recipe torecoat the chamber walls. The preprocess condition run held a twofold purpose. One purpose was to remove anycontaminating organics that might effect the performance of the system. The other aim was to sufficiently heat up theprocess chamber, such that a steady state etch rate could be achieved.

EXPERIMENTAL DATA: PHASE 1

After processing, the wafers were cleaved and the cross sections examined using a Scanning Electron Microscope(SEM). For each wafer, the following responses were gauged: ARDE uniformity, cross surface uniformity, etch rate,selectivity of the photo resist to silicon, quantity of grass present, the preservation of 2µ line widths, and the degree ofscalloping in the silicon trenches. Four dies at different locations on each wafer were examined; top, center, lower left,and lower right (respective to the major flat of the wafer at the “bottom” of the orientation). The metrology of each dieinspected consisted of a 2, 4 ,6, 8 and 10µ trench configuration separated by 2µ lines. What follows are details of theresponses observed.

ARDE Uniformity

The average ARDE uniformity was determined by measuring the etch depths of the 2, 4, 6, 8 and 10µ trenches.Uniformity was calculated from the equation: (max-min)/(min+max). The results from each of the four points (top,center, lower left, lower right) that spanned the surface of the wafer were then averaged to achieve the net average of thewafer’s ARDE uniformity. The main effects of ARDE uniformity are shown in FIGURE 4. Pressure, Duty Cycle,Period, and Cycle Times all were significant factors in governing ARDE. As seen in FIGURE 4 a lower (and thuspreferred) ARDE could be obtained by setting the duty cycle and period to the low level. No 2nd order interaction of thefactors was observed for ARDE.

Cross Surface Uniformity

Cross surface etch rate uniformity was calculated as such: each trench width’s (2, 4, 6, 8 and 10µ) depth was measuredfor each of the four points across the wafer (top, center, lower left, lower right). The averages across the surface of thewafer for each trench width depth was calculated, and the total average of each five of these averages served as the totalcross surface uniformity for the response. Only Pressure was seen as to have a main effect on cross surface uniformity.A lower process pressure resulted in better cross surface uniformity. Note that this is just the opposite of what is shownin FIGURE 4, where better ARDE uniformity is achieved at a high level process pressure.

Etch Rate

Etch rate was observed by first measuring the etch depth of each trench (2, 4, 6, 8 and 10µ) for all four points across thewafer (top, center, lower left, and lower right), and then dividing by the 15 (fifteen) minute process time to obtain a rate.These five averages were then subsequently averaged to obtain the net etch rate of each run. The main effects plot foretch rate is shown in FIGURE 5. It could be interpreted that each variable had an effect on etch rate, but clearly themajor factors are Duty Cycle and Period. The high levels of Duty Cycle and Period yielded the higher etch rate, and thisis intuitively what one would expect. Etch rate was determined to be slower for LF processing than with HF ASEprocessing. Shown in FIGURE 6 is the 2nd order effects plot. Parallel lines indicate no 2nd order interaction, while criss-crossing lines suggest that interaction between the variables is present. Also, a positive 2nd order interaction of factorsgenerally renders the 1st order effects plot meaningless.

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FIGURE 4main effects plot for ARDE uniformity

FIGURE 5main effects plot for etch rate (µ/min)

Selectivity

As mentioned, UVbaked photoresist was used as the mask for each experiment run. It is worth stating again that thiscrosslinked resist has a higher selectivity than conventionally hard baked resist. Resist thickness was measured beforeeach run using a Tencor™ Alphastep 200 automatic step profiler, and after each run by means of the SEM. Theselectivity was calculated as the ratio of silicon etch depth to the thickness of photo resist consumed. A high levelPressure and Cycle Times coupled with a low level Duty Cycle gave the best selectivity. The main effects plot forselectivity is shown in FIGURE 7. There were no discernable 2nd order effects for selectivity.

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FIGURE 6interaction plot for etch rate (µ/min)

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FIGURE 7main effects plot for selectivity, (Si:PR)

Grass

Grass can be defined as the thin fiber-like strands of silicon that sometimes occurs at the bottom of a trench. The level ofgrass was qualified in terms of the cross sectional area present in the trenches on the SEM image. A grass rating from 1-10, 10 being the highest amount, was given to each trench across the wafer. In FIGURE 8 and FIGURE 9 are displayedthe main and second order effects plots of grass.

FIGURE 9Interaction Plot for Grass, (1-10)

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FIGURE 8main effects plot for grass, (1-10)

FIGURE 9interaction plot for grass, (1-10)

2µµµµ Line width preservation

Each 2 µ line width was measured and recorded across the range of four points on each wafer. It became apparent thateach factor in the experiment had a 1st order effect on line width. The main and second order effects plots are shown inFIGURES 10 and FIGURE 11 respectively.

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FIGURE 11interaction plot, post process 2µ line width, (µ)

FIGURE 10main effects plot, Post process 2µ line width, (µ)

Scallop

Scalloping or “mouse bites” are defined as the semi-circular lateral voids in silicon that sometimes occur in the ASEprocess. No LF parameters were found to have any effect on scalloping. The Cycle Times however when held to the highlevel ratio were observed to cause significant scalloping.

At the conclusion of the phase I experiment it became evident that some optimization would be necessary. Some of the1st and 2nd order effects of responses contradicted one another in the obtainment of the best possible recipe. For instance,the best settings for ARDE would be at the expense of cross surface uniformity. Hence, an optimization was performedusing MINITAB™ statistical software and an optimized recipe was procured. The optimized recipe parameters areshown in TABLE 3 . The results of this very recipe upon a silicon wafer are presented in FIGURE 12. From left to rightare the 10, 8, 6, 4, and 2µ trenches separated by 2µ lines. The average etch depth seen here is approximately 45µ , withthe average ARDE uniformity coming in well under 3%. The cross surface uniformity was ascertained to be under 7%.

PROCESS DEVELOPMENT: PHASE II

Once the responses of the phase I experiment were found and the variables optimized, the second phase of theexperiment could be carried out. SOI wafers with a nominal silicon device layer of 50µ and a thermal oxide layer of 1µwere used for this portion of the LF characterization. The SOI wafers were patterned with the same UVbaked OCG-825g-line resist and pattern used in phase I. Naturally, the parameters of principle interest in the phase II experiment werethe LF pulsing components. Armed with an optimized uniformity LF recipe, an exploration of different pulsingcombinations and their effects on footing could then be undergone.

8 (eight) runs were executed with the SOI wafers. The runs were randomized and performed after the same pre-processconditioning run used in the phase I experiment. As stated previously, the side effect of grass was a nuisance responseprevalent with a range of different combinations of parameters. In order to test discrete LF parameters in phase II, platenpower was adjusted to eliminate the grass effect. It was discovered that by boosting the LF platen power the presence ofgrass could be eliminated. A pre-process experiment upon silicon wafers consisted of raising the platen powerincrementally until grass was no longer visible. This was done for each corresponding LF parameter combination (DutyCycle, Period). The purpose of this was to allow various combinations of LF parameters to be explored without havingto worry about grass on the SOI substrates. It is worth mentioning that the differences in platen power did not affect thetrench profile of the 50µ deep device layer being etched.

Pass Etch

RFp (Watt) 0 var

RFc (Watt) 600 600

C4F8 (sccm) 150 0

O2 (sccm) 0 12.5

SF6 (sccm) 0 125

Cyctime (sec) 5 6.7

Overrun (sec) 0.5 0.5

APC (%) APC 31 mT

Process Time variable overetch

chiller temp 20 Cfrequency LFpulse variable variable

FIGURE 12results of optimized recipe

TABLE 3parameters in optimized recipe

EXPERIMENTAL DATA: PHASE II

The Phase II data is presented in TABLE 4. The LF pulsing was investigated for the four possible factorial groupingsbetween the low and high levels of Duty Cycle and Period from phase I. Additionally, a center point experimentcomposed of a 15 millisecond period with a 33% duty cycle was performed. Note that the percent overetch from run torun differs slightly due to the slight variance in silicon device depths. In some of the runs grass was still present at theoxide layer despite the increase of platen power. How this might have effected footing is unknown.

The only prevalent footing (>>150nm) occurred in run 5, with a 10 msec period and 50% duty cycle. Run 3 revealedsome notching at the insulator layer only slightly larger than 150 nm. The same segment of the die examined in phase Iwas studied in phase II. The 2µ lines between the 2 and 4µ spaces were missing in runs 3, 5, and 6. It could be reasonedthat footing may have destroyed the lines entirely thus freeing them from the substrate. However, there was nodiscernable footing in other line widths for run 6. The results of run are shown in FIGURE 2. Presented in FIGURE 13and FIGURE 14 are 2µ lines from run 8 with no visible footing.

FIGURE 14zoom-in of 2µ lines in Run 8

FIGURE 132µ lines from Run 8

run # platen period dc %overetch notching grass missing lines1 25W 20ms 25% 14% none some all entact2 15W 15ms 33% 11% none some all entact3 18W 20ms 50% 17% slight none 2 mic4 21W 15ms 33% 16% none some all entact5 18W 10ms 50% 11% yes none 2 mic6 30W 20ms 25% 38% none some 2 mic7 30W 10ms 25% 22% none yes all entact8 30W 20ms 25% 12% none none all entact

TABLE 4results of phase II LF etching on SOI wafers

CONCLUSION

The characterization, optimization, and ensuing trial runs of STS’ SOI LF upgrade system reported in this paper has led to acategorical conclusion: the system does indeed alleviate the footing effect. High aspect ratio (25:1) silicon structures on oxide wereable to be achieved by using the LF SOI system. By running a factorial design of experiment, it was possible to minimize uniformityeffects associated with LF DRIE processing. This apparently lent itself well to the final results. Overetch times up to 38% withoutdiscrete notching were revealed with the LF system. Light was shed upon the new LF parameters as well. Although an optimizedrecipe was presented, any special type of desired recipe could be procured from the characterization data disclosed. For instance, oneof the drawbacks of the LF system reported is the tendency to promote grass. In the phase II experiment it was shown that grass couldbe bypassed by increasing platen power. Nonetheless, an absolute minimization of grass could be obtained by closely studying the 1st

and 2nd order effects plots and adjusting the variables accordingly.

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