Logic Design Fundamentals - 3 Discussion D3.2. Logic Design Fundamentals - 3 Basic Gates Basic...

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Transcript of Logic Design Fundamentals - 3 Discussion D3.2. Logic Design Fundamentals - 3 Basic Gates Basic...

  • Slide 1
  • Logic Design Fundamentals - 3 Discussion D3.2
  • Slide 2
  • Logic Design Fundamentals - 3 Basic Gates Basic Combinational Circuits Basic Sequential Circuits
  • Slide 3
  • Logic Design Fundamentals - 3 Latches Flip-Flops Registers Counters Shift Registers
  • Slide 4
  • R-S Latch R S Q Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW
  • Slide 5
  • library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatch is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatch; architecture rslatch of rslatch is begin process(R,S) begin if S = '1' and R = '0' then Q