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Unit 8.Unit 8.

Combinational Circuit Design andCombinational Circuit Design andSimulation Using GatesSimulation Using Gates

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OutlineOutline

Review of Combinational Circuit Design

Design of Circuits w ith Limited Gate Fan-In

Gate Delay and Timing Diagrams

Hazards in Combinational Logic

Simulation and Testing of Logic Circuits

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88--11 Review of Combinational Circuit DesignReview of Combinat ional Circuit Design

Design of a combinational sw itching circuit Setup a truth table which specifies the output(s)

as a function of the input variables Derive simplified algebraic expressions for the output functions

using K-maps, the Q-M method, or other similar procedures.

Multi-level & Multi-output circuit

Minimum SOPs starting point Minimum two-level AND-ORNAND-NANDOR-NANDNOR-OR

Minimum POSs starting point Minimum two-level OR-ANDNOR-NORAND-NORNAND-AND

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88--22 Circuit w ith Limited Gate FanCircuit w ith Limited Gate Fan--InIn

Example I

Realize

using 3-input NOR gates

),,,,,,,,(),,,( 151410985430mdcbaf =

00

1

0

1

0

1

1

1

1

1

1

0

0

0

0

0

1

ab

cd 01 11 10

00

01

11

10

'abc)'db(c'a)ac'c'a(d'b

'cd'abc'a'abccd'abd'c'b'a'f

++++=

++++=

f

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Example II

only using 2-input NAND gates and inverters

b'a'ab'c'bf1 ++= b'abc'c'bf2 ++= 'bcbac'b'af2 ++=

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)c'b(ac'b'af

b'a)'cb)(c'b(for'c'b)c'a(bf

b'a)'ca('bf

3

22

1

++=

+++=++=

++=

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88--33 Gate Delay and Timing DiagramsGate Delay and Timing Diagrams

G1

A

B=1C=0

G2

20n

s

20n

s

20n

s

20n

s

A

G 2

G1

1us delay

due to w ire lenth

X Y Z

2us

1us

3us

1us

X

Y

Z

propagation delay in A N D

X

X '

1

2

1,

2m ay be very

sm all but still exist.

x x'

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88--44 Hazard in Combinational LogicHazard in Combinational Logic

What is hazard? Unwanted switching transients appearing in the output

while the input to a combinational circuit changes

Types of hazards

In K -Map, If any two adjacent 1s are not covered by the same loop,

a 1-hazard exists for the transition between the two 1s.

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Static 1Static 1 --hazardhazard

Let A=1 and C=1

Circuit w ith Hazard Removed

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Static 0Static 0 --hazardhazard

Let A=0, B=1, and D=0

Circuit w ith Hazard Removed

)'C'B'A)(D'BA)('DC)(D'C'B)('D'A)(CA(F +++++++++=

)D'C'B)('D'A)(CA(F ++++=

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88--55 Simulation and Testing of Logic CircuitsSimulation and Testing of Logic Circuits

For simulation logic circuits Specify the circuit components and connections

Determine the circuit inputs Observe the circuit outputs

4-valued logic simulator

0 (low)1 (high)X (unknow)Z (high impedance)

AND & OR function for 4-valued simulation

0

1

X

Z

0

1

X

X

1 X X

1

1

1 X

X

1 1

X

X

0 1 X Z

0

1

X

Z

0

0

0

0

0 0 0

1

X

X X

X

X X

X

X

0 1 X Z

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Testing of logic circuitsTesting of logic circuits

In the logic circuit, a wrong output may be due to Incorrect design

Gates connected wrong Wrong input signals to the circuit

Defective gates

Defective connecting wires

Logic circuit w ith incorrect output

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HomeworkHomework

135710

Design Problems