LOCx2, a Low-latency, Low-overhead, 2 × 5.12-Gbps Transmitter ASIC for the ATLAS Liquid Argon...
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LOCX2 LO Cic16B LC -PLL I2C Slave CML D river 1 6 : 1 S e r i a l i z e r A D ata X 4 A C lock 40 M H z R efC lk A Fram e 16-bitdata 5.12 G bps B D ata x 4 B C lock B Fram e LO Cic16B CML D river 1 6 : 1 S e r i a l i z e r C D ata x 4 C C lock C Fram e 5.12 G bps D D ata x 4 D C lock D Fram e 2.56 G Hz 320M H z 16-bitdata 320M H z SDA SCL Address BC ID _R eset ADC A ADC B G B T B ased C ontrollink ADC C ADC D G B T based C ontrollink M Tx LOCx2, a Low-latency, Low-overhead, 2 × 5.12-Gbps T ransmitter ASIC for the ATLAS Liquid Argon Calorimeter Trigger Upgrade Le Xiao, a,b Xiaoting Li, a Datao Gong, b,* Jinghong Chen, c Di Guo, b,d Huiqin He, a,b,e Guangming Huang, a Suen Hou, f Chonghan Liu, b Tiankuan Liu, b Xiangming Sun, a Ping-Kun Teng, f Bozorgmehr Vosooghi, c Annie C. Xiang, b Jingbo Ye, b Yang You, g a Department of Physics, Central China Normal University,Wuhan, Hubei 430079, P.R. China b Department of Physics, Southern Methodist University, Dallas, TX 75275, USA c Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77004, USA d State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei Anhui 230026, China e Shenzhen Polytechnic, Shenzhen 518055, P.R. China f Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan g Department of Electrical Engineering, Southern Methodist University, Dallas, TX 75275, USA * dgong @mail.smu.edu [1] ATLAS Collaboration, ATLAS liquid argon calorimeter Phase-I upgrade technical design report, CERN-LHCC-2013-017 and ATLAS-TDR-022, September 20, 2013. [2] J. Kuppambatti, et al, A radiation-hard dual channel 4-bit pipeline for a 12-bit 40 MS/s ADC prototype with extended dynamic range for the ATLAS Liquid Argon Calorimeter readout electronics upgrade at the CERN LHC, 2013 JINST 8 P09008 [3] B. Deng, et al, A line code with quick-resynchronization capability and low latency for the optical data links of LHC experiments , 2014 JINST 9 P07020 Introduction Conclusion and outlook Acknowledgments References • An transmitter ASIC, LOCx2, is designed and tested for the ATLAS LAr Calorimeter trigger upgrade. • LOCx2 consists of two channels and each channel encodes ADC data with an overhead of 14.3% and transmits serial data at 5.12 Gbps with a latency of less than 27.2 ns. The power consumption of the transmitter is 842.5 mW. • The next version will interface with both ASIC and COST ADCs This work is supported by US-ATLAS R&D program for the upgrade of the LHC, the US Department of Energy Grant DE-FG02- 04ER1299. We are grateful to Drs. Hucheng Chen and Hao Xu of Brookhaven National Laboratory for help on test and firmware development, Dr. Nicolas Dumont Dayot of LAPP for discussion on decoder implement. TWEPP 2015 - Topical Workshop on Electronics for Particle Physics, September 28 - October 2, 2015, Instituto Superior Técnico, Lisbon, Portugal Serializer Laser driver Optical transm itter Optical fiber TIA Optical receiver deserializer D ecoder Receiver On-detector, rad-tol Off-detector, COTS Encoder Transm ittter FPGA • The ATLAS Liquid Argon calorimeter (LAr) Phase-I trigger upgrade calls for a data transmission rate of 204.8 Gbps for each front-end board (LTDB) [1]. • The optical link on the transmitter side consists of a t ransmitter ASIC LOCx2 and a custom optical transmitter module MTx. • LOCx2 is a two-channal transmitter ASIC. Each channel receives data from the upstream ADCs [2], encodes the data, and outputs them in serial at a speed of 5.12Gbps. • The transmitter ASIC is fabricated in a commercial 0.25- µm Silicon-on-Sapphire CMOS technology for radiation- tolerance. • The latency budget of the optical link is 150 ns. • The power consumption budget of the transmitter ASIC is 1 W. P LL P FD C harge pum p LVDS R ec LP F LC VCO UP D ow n 40 M Hz Clock 2.56 G Hz clock Div64 The design of AISC Function block Latency (ns) TX FIFO 8.4-11.6 Scrambler & CRC gen 6.25 Frame Builder 3.125 Serializer 6.25 Total LOCx2 24.0-27.2 RX Deserializer 28.5-31.4 Data Extractor 9.4 Descrambler 3.1 CRC Check 3.1 Total FPGA 44.1-47.0 Total optical link 68.1-74.2 The test system and measurement results Functional blocks Power consumption (mW) LC-PLL 52.5 LOCic 192.5 Serializer 350.0 CML Driver 150.0 Clock Buffers 22.5 SLVS Receivers 75.0 Total 842.5 The block diagram of the optical link in ATLAS LAr trigger phase-I update The block diagram of LOCx2 ASIC Layout of the LOCx2 ASIC QFN packaged LOCx2 ASIC The block diagram of PLL The block diagram of serializer The block diagram of LOCic encoder The block diagram of test setup A picture of test setup The eye diagram of LOCx2 output at 5.12Gbps Latency of the optical link Power consumption of LOCx2 chip • The PLL has four tuning frequency bands selected through the I2C interface. The tuning range of LC-VCO is from 1.86 GHz to 2.98 GHz at the nominal process corner and 55 C. • Both the bandwidth of the LPF and the charge pump current are programmable, thus the loop the PLL is programmable from 0.5 to 2.5 MHz. • The ASIC uses a custom line code called LOCic [3]. • Each frame consists of 128 bits, including 8- bit frame header, 112-bit payload and 8-bit frame trailer. • The payload is scrambled before transmitted, whereas the frame header and trailer are not scrambled. • 12-bit BCID information is embedded in the frame header automatically. • The overhead is 14.3% (= 16/112). • Each Serializer unit consists of 4 stages of 2:1 multiplexers in a binary tree structure. All 2:1 multiplexer are based on static CMOS D flip flops for single-event effect (SEE) immunity. Measuremen t Simulati on PLL turning range 2.0-3.1 GHz PLL random jitter 1 ps (RMS) Serial date output rise tim e 70 ps Serial date output fall tim e 64 ps Serial date output determin istic jitter 28 ps Serial date output random j itter 1.5 ps (RMS) Serial date output total ji tter 42 ps (peak-peak) Serial date output amplitud e 445mV (peak-peak) Serial date output BER < 10 -12 PLL and LOCx2 output measurment 8x4 S ynch FIFO 16 Scram bler 16 8 CRC G enerator 8 PRBS G enerator 16 4 A D ata A Fram e A C lock 320M H z LO C Clock SC R C lk C RC Clk PR BS C lk F r a m e B u i l d e r 320M H z C lock From P LL BC ID _R eset Fram e C lock Data D ata to S erializer BC ID_R eset From GBTx LV D S R ec LV D S R ec LV D S R ec 4 A D ata A Fram e A C lock A D C A 4 B D ata B Fram e B C lock LV D S R ec LV D S R ec LV D S R ec 4 B D ata B Fram e B C lock A D C B Encoder S erializer Div2 D ata 8 2.56G H z C lock from PLL C M L D river SerialD ata @ 5.12G bps Div2 Div2 2:1 M ux D ata 8 4 2:1 M ux 4 2 2:1 M ux 2 2:1 M ux KC705 FPG A E valuation B oard 4 0 M H z R e f C l o c k 320 M Hz C lock B oard R eceiverx 2 SC K x 4 FC K x 4 BC ID R eset B C ID R esetG en C o n n e c t o r MGT Deserializer LOCic D ecoder 16 E rror Logger 16 LO C x2 Test B oard P LL 640 MHz Oscilloscope 4 0 M H z T r i g C l o c k TestC lock I2C M aster SDA SCL C hannel0 C hannel1 PC USB D A TA[3:0]x 4 N EVIS ADC Em ulatorx 4 5.12G bps 5.12G bps
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Transcript of LOCx2, a Low-latency, Low-overhead, 2 × 5.12-Gbps Transmitter ASIC for the ATLAS Liquid Argon...
LOCX2
LOCic16B
LC-PLL I2C Slave
CML Driver
1 6 : 1
S e r i a l i z e r
A Data X 4
A Clock
40 MHz Ref Clk
A Frame
16-bit data5.12 Gbps
B Data x 4
B Clock
B Frame
LOCic16BCML
Driver
1 6 : 1
S e r i a l i z e r
C Data x 4
C Clock
C Frame
5.12 Gbps
D Data x 4
D Clock
D Frame
2.56 GHz
320MHz
16-bit data
320MHz
SDA
SCL
AddressBCID_Reset
ADC A
ADC B
GBT Based Control link
ADC C
ADC D
GBT based Control link
MTx
LOCx2, a Low-latency, Low-overhead, 2 × 5.12-Gbps Transmitter ASIC for the ATLAS Liquid Argon Calorimeter Trigger Upgrade
Le Xiao,a,b Xiaoting Li,a Datao Gong,b,* Jinghong Chen,c Di Guo,b,d Huiqin He,a,b,e Guangming Huang,a Suen Hou,f
Chonghan Liu,b Tiankuan Liu,b Xiangming Sun,a Ping-Kun Teng,f Bozorgmehr Vosooghi,c Annie C. Xiang,b Jingbo Ye,b Yang You,g a Department of Physics, Central China Normal University,Wuhan, Hubei 430079, P.R. China
b Department of Physics, Southern Methodist University, Dallas, TX 75275, USAc Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77004, USA
d State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei Anhui 230026, Chinae Shenzhen Polytechnic, Shenzhen 518055, P.R. China
f Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwang Department of Electrical Engineering, Southern Methodist University, Dallas, TX 75275, USA
[1] ATLAS Collaboration, ATLAS liquid argon calorimeter Phase-I upgrade technical design report, CERN-LHCC-2013-017 and ATLAS-TDR-022, September 20, 2013.[2] J. Kuppambatti, et al, A radiation-hard dual channel 4-bit pipeline for a 12-bit 40 MS/s ADC prototype with extended dynamic range for the ATLAS Liquid Argon Calorimeter readout electronics upgrade at the CERN LHC, 2013 JINST 8 P09008[3] B. Deng, et al, A line code with quick-resynchronization capability and low latency for the optical data links of LHC experiments, 2014 JINST 9 P07020
Introduction
Conclusion and outlook Acknowledgments References• An transmitter ASIC, LOCx2, is designed and tested for the
ATLAS LAr Calorimeter trigger upgrade.• LOCx2 consists of two channels and each channel encodes
ADC data with an overhead of 14.3% and transmits serial data at 5.12 Gbps with a latency of less than 27.2 ns. The power consumption of the transmitter is 842.5 mW.
• The next version will interface with both ASIC and COST ADCs
This work is supported by US-ATLAS R&D program for the upgrade of the LHC, the US Department of Energy Grant DE-FG02-04ER1299. We are grateful to Drs. Hucheng Chen and Hao Xu of Brookhaven National Laboratory for help on test and firmware development, Dr. Nicolas Dumont Dayot of LAPP for discussion on decoder implement.
TWEPP 2015 - Topical Workshop on Electronics for Particle Physics, September 28 - October 2, 2015, Instituto Superior Técnico, Lisbon, Portugal
SerializerLaserdriver
Optical transmitter
Optical fiber TIA
Optical receiver
deserializer Decoder
Receiver
On-detector, rad-tol Off-detector, COTS
Encoder
Transmittter
FPGA
• The ATLAS Liquid Argon calorimeter (LAr) Phase-I trigger upgrade calls for a data transmission rate of 204.8 Gbps for each front-end board (LTDB) [1].
• The optical link on the transmitter side consists of a transmitter ASIC LOCx2 and a custom optical transmitter module MTx.
• LOCx2 is a two-channal transmitter ASIC. Each channel receives data from the upstream ADCs [2], encodes the data, and outputs them in serial at a speed of 5.12Gbps.
• The transmitter ASIC is fabricated in a commercial 0.25-µm Silicon-on-Sapphire CMOS technology for radiation-tolerance.
• The latency budget of the optical link is 150 ns.• The power consumption budget of the transmitter ASIC is 1 W.
PLL
PFDChargepump
LVDS Rec
LPFLC
VCO
UP
Down
40 MHzClock
2.56 GHz clock
Div64
The design of AISC
Function block Latency (ns)
TX
FIFO 8.4-11.6
Scrambler & CRC gen 6.25
Frame Builder 3.125Serializer 6.25
Total LOCx2 24.0-27.2
RX
Deserializer 28.5-31.4Data Extractor 9.4Descrambler 3.1CRC Check 3.1Total FPGA 44.1-47.0
Total optical link 68.1-74.2
The test system and measurement results
Functional blocks Power consumption (mW)
LC-PLL 52.5
LOCic 192.5
Serializer 350.0
CML Driver 150.0
Clock Buffers 22.5
SLVS Receivers 75.0
Total 842.5
The block diagram of the optical link in ATLAS LAr trigger phase-I update
The block diagram of LOCx2 ASIC
Layout of the LOCx2 ASIC QFN packaged LOCx2 ASIC
The block diagram of PLL
The block diagram of serializer
The block diagram of LOCic encoder
The block diagram of test setup
A picture of test setup
The eye diagram of LOCx2 output at 5.12Gbps
Latency of the optical link
Power consumption of LOCx2 chip
• The PLL has four tuning frequency bands selected through the I2C interface. The tuning range of LC-VCO is from 1.86 GHz to 2.98 GHz at the nominal process corner and 55 C.
• Both the bandwidth of the LPF and the charge pump current are programmable, thus the loop bandwidth of the PLL is programmable from 0.5 to 2.5 MHz.
• The ASIC uses a custom line code called LOCic [3]. • Each frame consists of 128 bits, including 8-bit frame header,
112-bit payload and 8-bit frame trailer. • The payload is scrambled before transmitted, whereas the
frame header and trailer are not scrambled. • 12-bit BCID information is embedded in the frame header
automatically.• The overhead is 14.3% (= 16/112).
• Each Serializer unit consists of 4 stages of 2:1 multiplexers in a binary tree structure. All 2:1 multiplexer are based on static CMOS D flip flops for single-event effect (SEE) immunity.
Measurement
Simulation
PLL turning range 2.0-3.1 GHz
PLL random jitter 1 ps (RMS)
Serial date output rise time 70 ps
Serial date output fall time 64 ps
Serial date output deterministic jitter 28 ps
Serial date output random jitter 1.5 ps (RMS)
Serial date output total jitter 42 ps (peak-peak)
Serial date output amplitude 445mV (peak-peak)
Serial date output BER < 10-12
PLL and LOCx2 output measurment
8x4SynchFIFO
16
Scrambler
168
CRCGenerator
8PRBS
Generator164
A Data
A Frame
A Clock
320MHz LOC Clock
SCR Clk
CRC Clk
PRBS Clk
Fra
me
Bu
ilde
r
320MHz ClockFrom PLL
BCID_Reset
Frame Clock
Data
Data to Serializer
BCID_ResetFrom GBTx
LVDSRec
LVDSRec
LVDSRec
4
A Data
A Frame
A Clock
AD
C A
4
B Data
B Frame
B Clock
LVDSRec
LVDSRec
LVDSRec
4
B Data
B Frame
B Clock
AD
C B
Encoder
Serializer
Div2
Data 8
2.56GHz Clock from PLL
CML Driver
Serial Data@ 5.12Gbps
Div2Div2
2:1Mux
Data 8
42:1Mux4
22:1Mux2
2:1Mux
KC705 FPGA Evaluation Board
40M
Hz R
ef
Clo
ck
320 MHzClock Board
Receiver x 2
SCK x 4
FCK x 4
BCIDReset
BCID Reset Gen
Con
ne
ctor
MGT Deserializer
LOCicDecoder 16
ErrorLogger
16
LOCx2Test
BoardPLL
640MHz
Oscilloscope
40
MH
z T
rig C
lock
Test Clock
I2C Master
SDA
SCL
Channel0
Channel1PC
USB
DATA[3:0] x 4
NEVIS ADC Emulator x 4
5.12Gbps
5.12Gbps
