Lock-free Linearizable 1-Dimensional Range Queriessalaa/wttm2016/html/... · Bapi Chatterjee...

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Lock-free Linearizable 1-Dimensional Range Queries Bapi Chatterjee Distributed Computing and Systems Group Department of Computer Science and Engineering Chalmers University of Technology, Sweden 8th WTTM 2016 July 25, 2016 1/20 Lock-free Linearizable Range Queries Bapi Chatterjee

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Lock-free Linearizable 1-Dimensional RangeQueries

Bapi Chatterjee

Distributed Computing and Systems GroupDepartment of Computer Science and Engineering

Chalmers University of Technology, Sweden

8th WTTM 2016July 25, 2016

1/20 Lock-free Linearizable Range Queries Bapi Chatterjee

Introduction

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Introduction

The problem statement

• Given: Set of data-points on the real line and an intervalthereon.

• Setup: Dynamic and Concurrent addition and removal ofdata-points.

• Output: The data-points in the interval.

• Requirement:• Lock-freedom.

• Linearizability.

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Introduction

Problem relevance

• Ubiquitous multi-core systems.

• The ordered Set ADT provides size(T a, T b) that isimplemented in sequential setup.

• Increasing availability of efficient lock-free ordered sets.

• Linearizability provides an aligned view with respect to areal-time line.

• Growing popularity of In-memory Databases. Some withlock-free index structures e.g. MemSQL uses lock-freeskip-lists.

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Introduction

Existing linearizable concurrent range search implementations

1 Brown and Avni [OPODIS ’12]: Lock-free k-ary search treebased; Lock-free; Double-scan and validation.

2 Avni et al. [PODC ’13]: STM based approach on a variant ofSkip-list with “fat” nodes; Blocking.

3 Sagonas and Winblad [LCPC Workshop ’15]: Locking treestructure based; Blocking.

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Presented Method

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Algorithm

Motivation for an alternate approach

• Progress guarantee.

• Independence from the performance of a particular STM.

• Avoiding multi-scan and restart.

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Algorithm

Overview

Afek et al. ’93: Snapshot

Attiya et al. ’08, Imbs etal. ’09: Partial Snapshot

Brown and Avni ’12: kstbased Range Search

Jayanti ’05: Snapshot

Petrank et al. ’13:Lock-free Iterators

Our method

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Algorithm

Snap-collectorAn Ordered Set Data Structure

∗sc

isActive: bool

A Snap-Collector Object

L: node-list

R1: report-list of p1 Rn: report-list of pn

Remove-report

Add-report

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Algorithm

Range-collectorAn Ordered Set Data Structure

∗rc

isActive: bool

A Range-Collector Object

L: node-list

R1: report-list of p1 Rn: report-list of pn

Remove-report

Add-report

x : lower limit

x ′: upper limit

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Algorithm

Lock-free data structure with Range-collector-listAn Ordered Set Data Structure

head

tail

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Algorithm

Lock-free data structure with Range-collector-listAn Ordered Set Data Structure

head

tail

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Algorithm

Lock-free data structure with Range-collector-list

An Active set

An Ordered Set Data Structure

head

tail

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Performance

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Performance

Performance

2 4 8 16 28 32

2,000

3,000

4,000

5,000

6,000

7,000

#threads

Ops

/ms

LLBSTSL

KST 64

Figure: 5% Add, 5% Rem, 89%Con, 1% RSearch, 0≤x<102

Machine: Intel(R) Xeon(R) E5-2695 v3 processor, dual chip with 14 hardware processes per chip (28 threads with HT) @ 2.30 GHz. Average of 10 repetitions of 5 seconds runs. Integer type keys.

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Performance

Performance

2 4 8 16 28 320

2,000

4,000

6,000

#threads

Ops

/ms

LLBSTSL

KST 64

Figure: 25% Add, 25% Rem, 49%Con, 1% RSearch, 0≤x<102

Machine: Intel(R) Xeon(R) E5-2695 v3 processor, dual chip with 14 hardware processes per chip (28 threads with HT) @ 2.30 GHz. Average of 10 repetitions of 5 seconds runs. Integer type keys.

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Performance

Performance

2 4 8 16 28 32

1,000

2,000

3,000

#threads

Ops

/ms

LLBSTSL

KST 64

Figure: 5% Add, 5% Rem, 89%Con, 1% RSearch, 0≤x<103

Machine: Intel(R) Xeon(R) E5-2695 v3 processor, dual chip with 14 hardware processes per chip (28 threads with HT) @ 2.30 GHz. Average of 10 repetitions of 5 seconds runs. Integer type keys.

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Performance

Performance

2 4 8 16 28 32

400

600

800

1,000

#threads

Ops

/ms

LLBSTSL

KST 64

Figure: 25% Add, 25% Rem, 49%Con, 1% RSearch, 0≤x<103

Machine: Intel(R) Xeon(R) E5-2695 v3 processor, dual chip with 14 hardware processes per chip (28 threads with HT) @ 2.30 GHz. Average of 10 repetitions of 5 seconds runs. Integer type keys.

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Summary

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Summary

Summary

Summary

• A generic linearizable lock-free 1-dimensional range search.

• No multiple-scan, no invalidation.

• Scalability does not deteriorate with high number of updates.

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