NEM RELAY BASED LOW POWER DESIGN1. LITERATURE REVIEW1.1. MOTIVATIONDuring the last 50 years, CMOS technology scaling has provided substantial improvements in terms of density, performance, and energy efficiency. Scaling the minimum feature size of a design by a factor of 1/2 has improved the overall density by a factor of 2 (1/2 in the x-dimension and 1/2 in the y-dimension). Since the total energy consumption in early designs was largely dominated by the dynamic power dissipation and not by leakage, scaling the supply voltage (VDD) drastically improved energy efficiency. In order to maintain or improve performance at these lower supply voltages, the threshold voltage (Vth) was also scaled, allowing for an increase in on-state current (Ion) and reducing the delay. However, this scaling has now reached a point at which an integrated circuit design is limited by its total power consumption i.e., any further scaling comes at the expense of increased total power.This has occurred as VDD scaling, although reducing dynamic power consumption, comes at the expense of Vth scaling (to maintain performance) that increases the leakage power consumption. The Vth of todays transistors is already set to optimally balance a designs dynamic and leakage power consumption, thereby imposing a limit on further supply scaling through conventional means. For further energy efficiency improvements, designers have shifted towards the use of multi-core processors. Each core operates at a lower supply voltage with lower power and at a lower throughput, but as long as parallelism is available, the overall performance is unchanged. However, even at arbitrarily low per-core performance, the energy efficiency achievable by CMOS devices is ultimately limited by their offstate leakage (Ioff) which will cause even this technique to eventually become ineffective. If a device with a steeper sub-threshold slope (one that achieves a more ideal switching behaviori.e., lower (Ioff for the same Ion) can be identified, this challenge can potentially be overcome, allowing for further scaling improvements in energy efficiency beyond the limits of CMOS technology.1.2 CMOS ENERGY EFFICIENCY LIMITA MOSFET is essentially an electronic switch whose on/off state is controlled by the voltage difference between the gate and the source (VGS). With the channel doped of opposite type as the source/drain regions, a built-in potential barrier is formed at the source-channel junction in the off state. The height of this barrier governs the rate at which mobile charge carriers diffuse from the source into the channel region via thermionic emission and then drift across the channel region to be collected by the drain (i.e. the amount of current flowing through the device). By changing VGS, the channel potential and hence the source potential barrier height is modulated, to control the current flowing through the channel. Consider the typical drain current (ID) vs. gate voltage (VG) characteristic of a MOSFET. When the magnitude of VGS exceeds the threshold voltage (VTH), the potential barrier at the source side is insignificant so that carriers can easily diffuse into the channel region. In the on state, a conductive path of mobile charge carriers forms in the channel region and current flow is limited by the rate of carrier drift to the drain. The on-current (ION) of a long-channel MOSFET is given by the following equation: (1.1)where is the effective carrier mobility, is the gate oxide capacitance per unit area, and and are the transistor gate width and length, respectively. When IDis plotted on a logarithmic scale vs. VG (Figure 1.1), it can be clearly seen that the off-state to on-state transition is not abrupt. The energy distribution of carriers within the source region follows Boltzmann statistics. Thus, in the sub-threshold (VG > so that the channel potential closely follows the gate potential and SS reduces to ln(10), which is 60 mV/dec at room temperature. Since is a non-scaling physical constant, an ideal MOSFET switching characteristic is limited to be no steeper than 60mV/dec at room temperature. In practice, is typically closer to 100mV/dec. The fundamental limit on how abruptly a MOSFET can switch on/off due to the non-scalability of the thermal voltage results in a minimum energy limit for CMOS digital circuits.

Figure 1.2.CMOS minimum energy limit due to sub-threshold leakage. The total energy dissipated in a CMOS circuit consists of two components: dynamic energy () from charging and discharging capacitors and leakage energy () caused by transistor off-state leakage current: =+ (1.4) =2 (1.5) = (1.6)where is the activity factor, is the logic depth, is the fan-out, and is the capacitance per stage. The time delay per operation, , is given by: t=/2.Dynamic energy can be reduced by lowering VDD following the blue line in Figure 1.2(b). However, by doing so, transistor drive current () is also reduced (Figure 1.2(a)), which in turn increases delay (). In order to maintain the same drive current (i.e. circuit performance), the threshold voltage () must be reduced to maintain the same gate overdrive (VDD ). However, a linear reduction in increases the off-state leakage () exponentially according to , following the red line in Figure 1.2(b). Alternatively, can be held fixed while scaling VDD at the expense of performance (a longer ), which in turn increases as well. Hence, there is a minimum total energy point that balances these two energy components. This is the energy efficiency limit of CMOS that will always exist if the mechanism for on/off switching is thermionic emission over a potential barrier. To avoid unreasonably high levels of chip power density, parallelism (multi-core processing) has been adopted in recent years. The idea is to operate the circuits more slowly at a lower energy point (Figure 1.3(a)), and to run multiple processor cores in parallel to recoup system level performance (Figure 1.3(b)). Today, multi-core microprocessor chips (with up to 8 cores in a single chip) have become the norm. Parallelism is only a temporary fix. Due to the fundamental energy efficiency limit for CMOS, energy consumption per operation cannot be lowered indefinitely by reducing core performance. When the CMOS circuitry is operating at the minimum energy point, the energy per operation cannot be lowered anymore even if throughput is further reduced (Figure 1.3(c)). To continue to improve system performance in the long run, sub-threshold leakage needs to be eliminated..

Figure 1.3.Plots of normalized energy per operation vs. 1/throughput1.3. VARIOUS MOSFET REPLACEMENT DEVICESThe leakage power is strongly influenced by the subthreshold swing of a device defined as SS= (d log IDS/dVGS )-1. The SS indicates the minimum amount of gate-voltage reduction necessary to lower the subthreshold current by a factor of ten. Transistor designs with lower SS value reduce the leakage energy; this allows for more aggressive Vdd scaling and improvement in the energy efficiency.To reach this goal, alternative transistor designs such as the tunneling based field effect transistors, impact ionization MOS, ferroelectric FETs and electromechanical devices have been proposed and demonstrated to achieve subthreshold swing (SS) < 60mV/dec.Tunneling Field Effect Transistor (TFET) Among all the alternative transistor designs, the tunnel field effect transistor (TFET) shows the most promise due to its relative simplicity and resemblance to the conventional MOSFET. The TFET utilizes band-to-band tunneling (BTBT) current to achieve a more abrupt on-to-off transition than what is achievable through thermionic emission. Fig.1.4 shows the energy and diagram of the TFET in on and off states.

Figure 1.4.T-FET ON and OFF band diagramsIn the off state, the wide energy barrier prohibits quantum tunneling between the source and channel regions. When a large Vgs is applied, the energy barrier narrows, and allowed energy states in the channel conduction band align with allowed energy states in the source valence band, so that electrons can tunnel from the source to the channel. Since the TFET utilizes a different source injection mechanism from the MOSFET, it can potentially achieve lower SS values, which has already been experimentally demonstrated. Note, however, that a TFET achieves SS