liserre_lecture_7-1

8/12/2019 liserre_lecture_7-1

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Grid synchronization for power converters

Marco Liserre [email protected]

Grid synchronization for power

converters

Marco Liserre

[email protected]


2/36



Grid requirements for DG inverters

PLL Basics, PLL in power systems

Design of PLL

PLL for single-phase systems

Methods to create the orthogonal component

Methods using adaptive filters

PLL for three-phase systems

Conclusions

Reference papers

Outline


3/36



Grid

Distrurbances

Thomsen,1999; CIGRE WG14-31, 1999

Grid disturbances are not

at all a new issue, andthe utilities are aware of

them. However, they

have to take a new look

because of the rapidly

changing customers

needs and the nature ofloads (CIGRE WG14-31,

1999)


4/36



Grid requirements for DG inverters

The following conditions should be met, with voltages in RMS andmeasured at the point of utility connection.

When the utility frequency is outside the range of +/- 1 Hz the invertershould cease to energize the utility line within 0.2 seconds.

The PV system shall have an average lagging power factor greaterthan 0,9 when the output is greater than 50% rated.

Thus the grid voltage and frequency should beestimated and monitored fast and accurate enough inorder to cope with the standard


5/36



Grid synchronization requirements

A good synchronization of the current with the grid voltage isnecessary as:

the standards require a high power factor (> 0.9)

a clean reference for the current is necesarry in order to cope with theharmonic requirements of grid standards and codes

grid connection transients needs to be minimized in order not to trip theinverter

Distributed Generation systems of higher power have also requirements interms of voltage support or reactive power injection capability and offrequency support or active power droop

Micro-grid distributed generation systems have wider range of voltage andfrequency and the estimated grid voltage parameters are often involved incontrol loops


6/36



Grid synchronization options and challenges

There are two basical synchronization methods: Filtered Zero Cross Detection (ZCD)

PLL

Single-phase systems:

The classical solution for single-phase systems was Filtered ZCD as for the PLLtwo orthogonal voltages are required.

The trend now is to use the PLL technique also by creating virtualorthogonal components using different techniques!

Three-phase systems:

Three-phase PLL should deal with unbalnace hence with negative sequence

Moreover in three-phase systems dynamics would be better if synchronizingto all three phase voltages, i.e. based on space vectors rather then on a scalarvoltage


7/36



Zero Cross Detection (ZCD) circuits

Resistive feedback hysteresiscircuit

Dual point interpolation circuit

Dynamic hysteresis comparatorcircuit

Source: R.W. Wall, Simple methods for detectingzero crossing, IEEE IECON03, pp. 2477-2481


8/36



Filtered Zero Cross Detection (ZCD) based

monitoring and synchronization

v

21 x d tT

1

2

T

f

V

sin

I

I

OV/UV

OF/UF

TRIP

Filter

maxV

minV

minf

maxf

RMS CALC

2

x

RST

ku

filvZCD

maxV

minV

minfmaxf

V

f

v filv

Filtering introduces delay. There are digital predictive FIR filters withoutdelay bu with high complexity (very high order!)

The RMS voltage and frequency are calculated once in a period poordetection of changes (sags, dips, etc.)


9/36



-200

-100

0

100

200

v[V]

Basic idea of synchronization based on a phase-locked loop:

Phase-locked technology is broadly used in military, aerospace, consumer electronics systemswhere some kind of feedback is used to synchronize some local periodic event with somerecognizable external event

Many biological processes are synchronized to environmental events. Actually, most of usschedule our daily activities phase-locking timing information supplied by a clock.

A grid connected power converter should phase-lock its internal oscillator to the grid voltage

(or current), i.e., an amplitude and phase coherent internal signalshould be generated.

Event based synchronization

(simple, discontinuous, )

in

v

Phase-locked synchronization

(continuous, predictive,)

PLL basis


10/36



Basic blocks:

Phase Detector (PD). This block generates an output signal proportional to the phasedifference between its two input signals. Depending on the type of PD, high frequency accomponents appear together the dc phase difference signal.

Loop Filter (LF). This block exhibits low pass characteristic and filters out the high frequency accomponents from the PD output. Typically this is a 1-st order LPF or PI controller.

Voltage Controlled Oscillator (VCO). This block generates at its output an ac signal whosefrequency varies respect a central frequency as a function of the input voltage.

Phase

Detector

Loop

Filter

Voltage

Controlled

Oscillator

fvvvd

v

PLL basis


11/36



PLL in power systems

va

vb

T1 T3

Evdc

T5

vc

ia

T4 T6 T2

LS

+

-

LLRL

In 1968 Ainsworth proposed to use a voltage

controlled oscillator (VCO) inside the control loopof a High Voltage Direct Current (HVDC)

transmission system to deal with the novel, at that

time, harmonic instability problem.

Subsequently, analog phase locked

loops (PLL) were proposed to be used as

measurement blocks, which provide frequency

adaptation in motor drives.


12/36



Phase Locked Loop tuning

cos( )x

p ik k

ok

dk

c

esdv sin in inA t

PD LF

VCO

sin in in inv A t

cos VCO c out v t

Reference:

VCO output:

PD/Mixer output: sin cos sin sin2

dd d in in c out in c in out in c in out

Akv Ak t t t t

VCO angle: c o e out o et k s dt k s dt

if , then ,

Smallsignal

analysis:

inc sin 2 sin2d

d in in out in out

Akv t

in out sin 22

dd in in in out

Akv t

The average value is

2

dd in out

Akv

sin in out in out if , then ,


13/36



Phase Locked Loop tuning

2

( )( )

( )

p

p

out i

pinp

i

kk s

s TH s

kss k s

T

;2

p ip

n

i

k Tk

T

1.8r

n

t

29.2;

2.3s

p i

s

tk T

t

11p

i

kT s

esdv

PD LF - HPI VCO

in outokmk

1

s

1 1o mk k assuming

that can be written as

2

2 2

( ) 2( )

( ) 2

out n n

in n n

s sH s

s s s

with

4.6s

n

t

The PLL can be tuned as function of the

damping and of the settling time

then


14/36


15/36



Phase Locked Loop: the need of the orthogonal

component

11pi

KsT

X

X

cos

sin

s1

in

Vsin -in out

Vsin in int

Vcos in int

in out t

+++-

To eliminate the 2 harmonic oscillation from sin 2 sin2

din in out in out

Akt

and obtain it should be considered that sin2

din out

Ak

sin - sin cos cos sinin out in out in out


16/36



Park transformation in the PD

cos( ) sin( )

sin( ) cos( )

d out out

q out out

v v

v v

Park transformation:

sin( )

cos( )

in

in

vV

v

sin cos cos sin sin

sin sin cos cos cos

d in out in out in out

q in out in out in out

vV V

v

Assuming in=out:

sin

cos

d in out

q in out

vV

v

11

p

i

kT s

fvdv

LF VCO

1

sc

qv

dq

v

v

out

out

PD

inv QuadratureSignal

Generator

v

v

qv

dv

d

q

in

out

sin( )inv V

v


17/36



Park transformation in the PD

0

0in

t

d

q

v

02

out

t

sin( ) ; 0in qv V v

0

0int

d

q

v

0

0outt

sin( ) ; 0in dv V v 11p

i

kT s

fvdvLF VCO

1

sc

dq

v

v

out in

out

PD

inv QuadratureSignal

Generator

qv v

11p

i

kT s

fv

LF VCO

1

sc

qv

dq

v

v 2out in

out

PD

inv Quadrature

Signal

Generator

dv v

PI on vd

PI on vq

From here on, it will be considered:

and PI on vq,, i.e.,

Therefore:

sinin inv v V 0qv

andout in d v v V


18/36




Transport Delay T/4

The transport delay block is easily implemented through the use of a first-in-first-out

(FIFO) buffer, with size set to one fourth the number of samples contained in one

cycle of the fundamental frequency.

This method works fine for fixed grid frequency. If the grid frequency is changing

with for ex +/-1 Hz, then the PLL will produce an error

If input voltage consists of several frequency components, orthogonal signals

generation will produce errors because each of the components should be delayed

one fourth of its fundamental period.

11p

i

kT s

esdv

LF VCO

1

sc

qv

dqDelay

T/4

v

v

PD

inv

inv


19/36




Inverse Park Transformation

A single phase voltage (v

) and an internally generated signal (v

) are used as inputs to a Park

transformation block (-dq). The d axis output of the Park transformation is used in a control loop to

obtain phase and frequency information of the input signal.

v is obtained through the use of an inverse Park transformation, where the inputs are the d and q-

axis outputs of the Park transformation (dq-). fed through first-order low pass filters.

Although the algorithm of the PLL based on the inverse Park transformation is easily implemented,

requiring only an inverse Park and two first-order low-pass filters

11p

i

kT s

esdv

LF VCO

1

sc

qv

dq

v

v

PD

inv

inv

dq

LPF

LPF

dv

qvv

v


20/36



k

SOGI

v v

q v


Second Order Generalized Integrator

2 2( ) ( )

d sS s s

f s

SOGI

d

q

f

2

2 2( ) ( )

qT s s

f s

2 2( ) ( )

v k sD s s

v s k s

2

2 2( ) ( )

qv kQ s s

v s k s

-60

-40

-20

0

20

Magnitude(dB)

10-1

100

101

102

103

104

-90-45

0

45

90

P

hase(deg)

k=0.1

k=1

k=4

-60

-40

-20

0

20

Magnitude(dB)

10-1

100

101

102

103

104

-180

-135

-90

-45

0

Phase(deg)

Frequency (Hz)

k=0.1

k=1

k=4

( )D

( )Q


21/36



k

k

outvvinv

cos

sin

OSCILLATOR


Adaptive Notch Filter (ANF)2 2

2 2( ) ( )out

in

v sANF s s

v s ks

vout=0 when:

voutcan not be directly used as

PD in the PLL

t

vout=0 when:

voutcan be used as PD in the

PLL

int

koutvvinv

cos

OSCILLATOR

cosin inv A t

G id h i i f


22/36




ANF-based PLLPD

k

v

cos

inv

es

LF

VCO

1

scAdaptive Notch Filter

dvck

1

s

Very sensible to frequency variationANF+PLL EPLL

More robust

Faster dynamic response

PDk

v

cos

inv 1

1p ik T s

es

LF VCO

1

sc

sin

Adaptive Notch Filter

dv

Conventional PLL structure

1

s

Combination of an ANF with a

conventional PLL gives rise to the

Enhanced PLL (EPLL)

G id h i ti f t


23/36



dv

kv v

PI

cos

ju u

v ( )V

ABPF

ff

v v

sin

VCO

LF

PD

Enhanced PLL (EPLL)

Original structure of the EPLL


K

90

Kp

Ki sin

+ +

+

+

+-

y

A

0

BPAF LP VCO

v e

1

s

1

s

1

s

G id h i ti f t


24/36



2 2( ) ( )

v k sD s s

v s k s

SOGI-PLL


2 2( ) 1 ( ) ( )

v ksABPF s ANF s s

v s ks

Adaptive band-pass filter:

Damping factor is a function of

the detected frequency value

Second order generalized integrator follower:

If can change, SOGI follower can be seen

as an adaptive band-pass filter with damping

factor set by kand unitary gain

As in the EPLL, a standard PLL can be

used to detect grid frequency and angle

juis 90-leading vwhen the PLL issynchronized in steady state

ju=-quand qu qv

It seems intuitive to use -qu(insteadju) as

the feedback signal for the PD of the PLL

v

VCO

kv v

qv

PI

juffsin

LF

SOGI

v

PD

Conventional PLL structure

G id h i ti f t


25/36



SOGI-based Frequency Locked Loop (SOGI-FLL)


v

kv v

qv

SOGI

1

ffv

qv

FLL

Does not need any trigonometric function since

neither synchronous reference frame nor voltage

controlled oscillator are used in its algorithm.

Is frequency-adaptive by using a FLL and not a

PLL.

Is highly robust in front of transient events

since grid frequency is more stable than voltage

phase-angle.

Attenuates high-order harmonics of the grid

voltage.

Entails light computational burden, using onlyfive integrators for detection of both sequence

components.



26/36



Distorted and unbalanced voltage vector

Three-phase grid synchronization

t

t

1

SV

1SV

SV

a

b

c

1SV

1SV

11 SS VV11 SS VV

1 2 1 2 1 1 1( ) ( ) 2 cos( 2 )S S S S S V V V V t

v

1 11

1 1 1

sin( 2 )tan

cos( 2 )

S

S S

V tt

V V t

a

b

c

SV

1SV

5SV

5SV

1SV

v S S Sn S SnV V V V n t 1 2 2 12 1cos

t

V n t

V V n t

S

n

S S

ntan

sin

cos

1

1

1

1

Neither constant amplitude nor

rotation speed



27/36



Characterization of voltage dips

0 0.02 0.04 0.06 0.08 0.1-1.5

-1

-0.5

0

0.5

1

1.5

V=0.5


28/36



Three-phase Synchronous Reference Frame PLL


PIs

1

SavSbv

Scv dqT

Sdv

Sqv

Sd Sv v

-150

-100

-50

0

50

100

150

0

1

2

3

4

5

6

7

0 25 50 75 100-50

0

50

100

150

t [ms]

-150

-100

-50

0

50

100

150

0

1

2

3

4

5

6

7

0 25 50 75 100-50

0

50

100

150

t [ms]

Balanced

voltage

Unbalanced

voltage

Sv

Sv

t

t

Sd Sv v

0Sqv

Sd Sv v

0Sq

v

1

1 1

1( )

cos( ) cos( )

sin( ) sin( )

Sd

S S Sdq Sq

v t tV V

v t t

v



29/36



-100

-50

0

50

100

150

0

1

2

3

4

5

6

7

-50

0

50

100

150



The SRF is not able to track instantaneous evolution

of the voltage vector when the PLL bandwidth is low

Sv

t

Sdv

Sqv

0 25 50 75 100-150

-100

-50

0

50

100

150

t [ms]

t 1S

v

1 1

( )

1 cos( 2 )v

' sin( 2 )S S Sdq

tV V

t t

' t Near of synchronization:

sin( ') 't t cos( ') 1t ' 2t t PI

s

1

SavSbv

Scv dqT

Sdv

Sqv

Sd Sv

v

1

1 1

1sin(2 ) ' 'SSq S S

S

Vv V t t V V

1

1sin(2 )S

S

Vt t

V

i

p

kk

s

1

s

1

S

V

*1Sq

v

2

2 2

2( ) ( )

2

c c

c c

sP s s

s s

1

c S iV k

1

2

p S

i

k V

k



30/36



-150

-100

-50

0

50

100

150



Setting a low PLL bandwidth and using a low-pass filter it is possible to obtain a

reasonable approximation of the positive sequence voltage but the dynamic is too slow.

Sv

0

1

2

3

4

5

6

7

-50

0

50

100

150

Sqv

Sdv

0 25 50 75 100-150

-100

-50

0

50

100

150

t [ms]

1

S

v

PIs

1

Sav

Sbv

Scv dqT

Sdv

Sqv

Sd Sv v

Repetitive

controller

Advanced filtering strategies can be used to cancel out the double frequency oscillation

keeping high locking dynamics, e.g., a repetitive controller based on a DFT algorithm.

Additional improvements are added to these filters to make them frequency adaptive.



31/36



Decoupled Doubled SRF-PLL. Decoupling


t

1Sv

1d

1q

1d

1q

1Sv

Sv

1

t

1

1

1 1

1

1 1

1( )( )

cos( ) cos( )

sin( ) sin( )

Sd

S S S S dqdq Sq

v t tT V V

v t t

v v

1

1

1 1

1

1 1

1( )( )

cos( ) cos( )

sin( ) sin( )

Sd

S S S S dqdq Sq

v t tT V V

v t t

v v

' t Near of synchronization:

1

11 1

1( )

1 cos( 2 )

sin( 2 )S S S

dq

tV V

tt

v

1

1

1 1

1( )

cos(2 ) cos( )

sin(2 ) sin( )S S S

dq

tV V

t

v

cos(( ) ) sin(( ) )cos( )cos( ) sin( )

sin(( ) ) cos(( ) )sin( )

n

n

n n

Sd m m m mS

S Sn n

Sq S

v n m t n m t VV V

v n m t n m t V

cos(( ) ) sin(( ) )cos( )cos( ) sin( ) .

sin(( ) ) cos(( ) )sin( )

m

m

m mSd n n n nS

S Sm m

Sq S

v n m t n m t VV V

v n m t n m t V

Generic decoupling cell:

cos

nSd

v

sin

mSd

v mSq

v

n

Sq

v

*n

Sdv

*n

Sq

v

m

nDC

nd

nq

md mq *nd

*nq

n-m

This terms act asinterferences on

the SRF dqn

rotating at n

frequency and

viceversa



32/36




y

.

Decoupled Doubled SRF-PLL

1Sdv

1Sqv

1d 1q

1

1DC

1

d1q

*1d

*1q

1

Sd

v

1Sqv

*1Sd

v

*1Sq

v

*

1Sdv*

1Sqv

1Sdv

1Sqv

1

1

SSdv

v

1Sqv

T Sv

1dqT

1dqT

abcSv

1d 1q

1

1DC

1d1q

*1d

*1q

ip kk

LPF

LPF

LPF

LPF

1

*

Sqv

*1Sq

v

2 2

q d qv v v

f

f

PLL input normalization



33/36



Conclusions

PLL is a very useful method that enable the grid inverters to:

Create a "clean" current reference synchronized with the grid Comply with the grid monitoring standards

The PLL generate is able to track the frequency and phase of the input

signal in a designed settling time

By setting a higher settling time a "filtering" effect can be achieved in order

to obtain a "clean" reference even with a polluted grid. Some PLLs need two signals in quadrature at the input.

For single-phase systems as there is only one signal available, the

orthogonal signal needs to be created artificially.

Transport Delay, Inverse Park Transformation, or Second Order

Generalized Integrators are some the methods used for quadrature signalgeneration.

Adaptive notch filters canceling fundamental utility frequency are used as

phase detectors in PLLs

FLL based on a SOGI is a very effective method for single phase

synchronization



34/36



References

1. J. D. Ainsworth, The phase-locked oscillator-a new control system for controlled static

convertors, IEEE Transactions on Power Apparatus and Systems, vol. 87, no. 3, pp. 859-865,

Mar. 1968.

2. G. C. Hsieh, J. C. Hung, Phase-locked loop techniquesA survey, IEEE Trans. On Ind.

Electronics, vol.43, pp.609-615, Dec.1996.

3. F. M. Gardner, Phase Lock Techniques. New York: Wiley, 1979.

4. L. D. Zhang, M. H. J. Bollen Characteristic of voltage dips (sags) in power systems, IEEE Trans.

Power Delivery, vol.15, pp.827-832, April 2000.

5. F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, Overview of Control and Grid

Synchronization for Distributed Power Generation Systems, IEEE Trans. on Ind. Electronics, Vol.

53, Oct. 2006 Page(s):13981409

6. M. K. Ghartemani, M.R. Iravani, A method for synchronization of power electronic converters in

polluted and variable-frequency environments, IEEE Trans. Power Systems, vol. 19, pp. 1263-

1270, Aug. 2004.

7. M.K. Ghartemani, M.R. Iravani, A Method for Synchronization of Power Electronic Converters in

Polluted and Variable-Frequency Environments, IEEE Trans. Power Systems, vol. 19, Aug. 2004,

pp. 1263-1270.

8. H.-S. Song and K. Nam, Dual current control scheme for PWM converter under unbalanced input

voltage conditions, IEEE Trans. On Industrial Electronics, vol. 46, no. 5, pp. 953959, 1999.



35/36



References

1. P. Rodrguez, A. Luna, I. Candela, R. Teodorescu, and F. Blaabjerg, Grid Synchronization of

Power Converters using Multiple Second Order Generalized Integrators, IECON08, Nov.

2008.

2. P. Rodrguez, J. Pou, J. Bergas, J.I. Candela, R. Burgos and D. Boroyevich, Decoupled

Double Synchronous Reference Frame PLL for Power Converters Control, IEEE Trans. on

Power Electronics, March 2007.

3. P. Rodriguez, R. Teodorescu, R.; I. Candela, I.; A.V. Timbus, M. Liserre, F. Blaabjerg, New

Positive-sequence Voltage Detector for Grid Synchronization of Power Converters under

Faulty Grid Conditions, PESC '06, June 2006.

4. M Ciubotaru, Teodorescu, R., Blaabjerg, F., A New Single-Phase PLL Structure Based on

Second Order Generalized Integrator, PESC06, June 2006.

5. P. Rodrguez, A. Luna, M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, Advanced Grid

Synchronization System for Power Converters under Unbalanced and Distorted Operating

Conditions, IECON06, Nov. 2006.

6. S.-K. Chung, Phase-Locked Loop for grid-connected three-phase power conversion

systems, IEE Proceedings on Electronic Power Applications, vol. 147, no. 3, pp. 213219,

2000.

7. Francisco Daniel Freijedo Fernndez, Contributions to Grid-Synchronization Techniques for

Power Electronic Converters, PhD Thesis, Vigo University, Spain, 2009



36/36


Acknowledgment

Part of the material is or was included in the present and/or past editions

of the

Industrial/Ph.D. Course in Power Electronics for Renewable Energy

Systemsin theory and practice

Speakers: R. Teodorescu, P. Rodriguez, M. Liserre, J. M. Guerrero,

Place: Aalborg University, Denmark

The course is held twice (May and November) every year

liserre_lecture_7-1

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