Linear Technology LTC3728EG28400

8/14/2019 Linear Technology LTC3728EG28400

1/37

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Jameco Part Number 1758331


2/37

LTC3728

1

3728fd

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Dual, 550kHz, 2-PhaseSynchronous Step-Down

Switching Regulator

The LTC3728 is a dual high performance step-downswitching regulator controller that drives all N-channelsynchronous power MOSFET stages. A constant frequencycurrent mode architecture allows phase-lockable frequencyof up to 550kHz. Power loss and noise due to the ESR ofthe input capacitors are minimized by operating the twocontroller output stages out of phase.

OPTI-LOOP compensation allows the transient response tobe optimized over a wide range of output capacitance andESR values. The precision 0.8V reference and power good

output indicator are compatible with future microprocessorgenerations, and a wide 3.5V to 30V (36V maximum) inputsupply range encompasses all battery chemistries.

A RUN/SS pin for each controller provides both soft-start and optional timed, short-circuit shutdown. Currentfoldback limits MOSFET dissipation during short-circuitconditions when overcurrent latchoff is disabled. Outputovervoltage protection circuitry latches on the bottomMOSFET until VOUT returns to normal. The FCB modepin can select among Burst Mode, constant frequencymode and continuous inductor current mode or regulatea secondary winding. The LTC3728 includes a power goodoutput pin that indicates when both outputs are within7.5% of their designed set point.

Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter

n Dual, 180 Phased Controllers Reduce RequiredInput Capacitance and Power Supply Induced Noise

n OPTI-LOOPCompensation Minimizes COUTn 1% Output Voltage Accuracyn Power Good Output Voltage Indicatorn Phase-Lockable Fixed Frequency 250kHz to 550kHzn Dual N-Channel MOSFET Synchronous Driven Wide VINRange: 3.5V to 36V Operationn Very Low Dropout Operation: 99% Duty Cyclen Adjustable Soft-Start Current Rampingn

Foldback Output Current Limitingn Latched Short-Circuit Shutdown with Defeat Optionn Output Overvoltage Protectionn Remote Output Voltage Sensen Low Shutdown IQ: 20An 5V and 3.3V Regulatorsn 3 Selectable Operating Modes: Constant Frequency,

Burst ModeOperation and PWMn Available in 32-Pin 5mm 5mm QFN and

28-Pin SSOP Packages

n Notebook and Palmtop Computersn Telecom Systemsn Portable Instrumentsn Battery-Operated Digital Devicesn DC Power Distribution Systems

L, LT, LTC, LTM, OPTI-LOOP and Burst Mode are registered trademarks of Linear TechnologyCorporation. All other trademarks are the property of their respective owners. Protected byU.S. Patents including 5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258,5705919.

+4.7F

D3D4

M1

CB1, 0.1F

R2105k1%

1000pF

L13.2H

CC1220pF

1FCIN22F50V

+COUT147F6VSP

RSENSE10.01

R120k1%

RC115k

VOUT15V5A

M2

CB2, 0.1F

R463.4k1%

L23.2H

CC2220pF

1000pF

+

COUT56F

6VSP

RSENSE20.01

R320k1%

RC215k

VOUT23.3V5A

TG1 TG2

BOOST1 BOOST2

SW1 SW2

BG1 BG2

SGND

PGND

SENSE1+ SENSE2+

SENSE1 SENSE2

VOSENSE1 VOSENSE2ITH1 ITH2

VIN PGOOD INTVCC

RUN/SS1 RUN/SS2

VIN5.2V TO 28V

M1, M2: FDS6982S 3728 F01

CSS10.1F

CSS20.1F

LTC3728

PLLINfIN

500kHz


3/37

LTC3728

2

3728fd

ABSOLUTE MAXIMUM RATINGS

Input Supply Voltage (VIN) .........................36V to 0.3VTop Side Driver Voltages(BOOST1, BOOST2) ................................... 42V to 0.3V

Switch Voltage (SW1, SW2) ......................... 36V to 5VINTVCC, EXTVCC, RUN/SS1, RUN/SS2, (BOOST1-SW1),(BOOST2-SW2), PGOOD .............................. 7V to 0.3VSENSE1+, SENSE2+, SENSE1,SENSE2Voltages .........................(1.1)INTVCCto 0.3VPLLIN, PLLFLTR, FCB, Voltage ............. INTVCCto 0.3V

(Note 1)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

TOP VIEW

G PACKAGE28-LEAD PLASTIC SSOP

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS1

SENSE1+

SENSE1

VOSENSE1

PLLFLTR

PLLIN

FCB

ITH1

SGND

3.3VOUT

ITH2

VOSENSE2

SENSE2

SENSE2+

PGOOD

TG1

SW1

BOOST1

VIN

BG1

EXTVCC

INTVCC

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

TJMAX= 125C, JA= 95C/W

32

33

31 30 29 28 27 26 25

9 10 11 12 13

TOP VIEW

14 15 16

17

18

19

20

21

22

23

24

8

7

6

5

4

3

2

1VOSENSE1

PLLFLTR

PLLIN

FCB

ITH1

SGND

3.3VOUT

ITH2

BOOST1

VIN

BG1

EXTVCC

INTVCC

PGND

BG2

BOOST2

NC

SENSE1

SENSE1+

NC

RUN/SS1

PGOOD

TG1

SW1

VOSENS

E2

N

C

SENSE2

SENSE2+

RUN/SS2

TG2

SW

2

N

C

UH PACKAGE32-LEAD 5mm 5mm PLASTIC QFN

TJMAX= 125C, JA= 34C/WEXPOSED PAD IS SGND (MUST BE SOLDERED TO PCB)

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3728EG#PBF LTC3728EG#TRPBF 3728 28-Lead Plastic SSOP 40C to 85C

LTC3728EUH#PBF LTC3728EUH#TRPBF 3728 32-Lead (5mm 5mm) Plastic QFN 40C to 85C

LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3728EG LTC3728EG#TR 3728 28-Lead Plastic SSOP 40C to 85C

LTC3728EUH LTC3728EUH#TR 3728 32-Lead (5mm 5 mm) Plastic QFN 40C to 85C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to:http://www.linear.com/leadfree/For more information on tape and reel specifications, go to:http://www.linear.com/tapeandreel/

ITH1, ITH2, VOSENSE1, VOSENSE2Voltages ... 2.7V to 0.3VPeak Output Current


4/37

LTC3728

3

3728fd

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loops

VOSENSE1, 2 Regulated Feedback Voltage (Note 3); ITH1, 2Voltage = 1.2V l 0.792 0.800 0.808 VIOSENSE1, 2 Feedback Current (Note 3) 5 50 nA

VREFLNREG Reference Voltage Line Regulation VIN= 3.6V to 30V (Note 3) 0.002 0.02 %/V

VLOADREG Output Voltage Load Regulation (Note 3)Measured in Servo Loop; ITHVoltage = 1.2V to 0.7VMeasured in Servo Loop; ITHVoltage = 1.2V to 2.0V

l

l

0.10.1

0.50.5

%%

gm1, 2 Transconductance Amplifier gm ITH1, 2= 1.2V; Sink/Source 5A; (Note 3) 1.3 mmho

gmGBW1, 2 Transconductance Amplifier GBW ITH1, 2= 1.2V; (Note 3) 3 MHzIQ

Input DC Supply Current Normal Mode Shutdown

(Note 4)VIN= 15V; EXTVCCTied to VOUT1; VOUT1= 5VVRUN/SS1, 2= 0V

45020 35

AA

VFCB Forced Continuous Threshold l 0.76 0.800 0.84 V

IFCB Forced Continuous Pin Current VFCB= 0.85V 0.50 0.18 0.1 A

VBINHIBIT Burst Inhibit (Constant Frequency)Threshold

Measured at FCB Pin 4.3 4.8 V

UVLO Undervoltage Lockout VINRamping Down l 3.5 4 V

VOVL Feedback Overvoltage Lockout Measured at VOSENSE1, 2 l 0.84 0.86 0.88 V

ISENSE Sense Pins Total Source Current (Each Channel); VSENSE1, 2 = VSENSE1+, 2+ = 0V 85 60 A

DFMAX Maximum Duty Factor In Dropout 98 99.4 %

IRUN/SS1, 2 Soft-Start Charge Current VRUN/SS1, 2= 1.9V 0.5 1.2 A

VRUN/SS1, 2ON RUN/SS Pin ON Threshold VRUN/SS1,VRUN/SS2Rising 1.0 1.5 1.9 V

VRUN/SS1, 2LT RUN/SS Pin Latchoff ArmingThreshold

VRUN/SS1,VRUN/SS2Rising from 3V 3.8 4.5 V

ISCL1, 2 RUN/SS Discharge Current Soft Short Condition VOSENSE1, 2= 0.5V;VRUN/SS1, 2= 4.5V

0.5 2 4 A

ISDLHO Shutdown Latch Disable Current VOSENSE1, 2= 0.5V 1.6 5 A

VSENSE(MAX) Maximum Current Sense Threshold VOSENSE1, 2= 0.7V, VOSENSE1, 2 = 5VVOSENSE1, 2= 0.7V, VOSENSE1, 2 = 5V l

6562

7575

8588

mVmV

TG1, 2 trTG1, 2 tf

TG Transition Time:Rise TimeFall Time

(Note 5)CLOAD= 3300pFCLOAD= 3300pF

5050

9090

nsns

BG1, 2 trBG1, 2 tf

BG Transition Time:Rise TimeFall Time

(Note 5)CLOAD= 3300pFCLOAD= 3300pF

4040

9080

nsns

TG/BG t1D Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time CLOAD= 3300pF Each Driver 90 nsBG/TG t2D Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time CLOAD= 3300pF Each Driver 90 ns

tON(MIN) Minimum On-Time Tested with a Square Wave (Note 6) 100 ns

INTVCCLinear Regulator

VINTVCC Internal VCCVoltage 6V < VIN< 30V, VEXTVCC= 4V 48 5.0 5.2 V

VLDOINT INTVCCLoad Regulation ICC= 0 to 20mA, VEXTVCC= 4V 0.2 1.0 %

VLDOEXT EXTVCCVoltage Drop ICC= 20mA, VEXTVCC= 5V 80 160 mV

The ldenotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA= 25C. VIN= 15V, VRUN/SS1, 2= 5V unless otherwise noted.


5/37

LTC3728

4

3728fd

ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA= 25C. VIN= 15V, VRUN/SS1, 2= 5V unless otherwise noted.

Note 1:Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition for extended periods may affect devicereliabilty and lifetime.

Note 2:TJis calculated from the ambient temperature TAand powerdissipation PDaccording to the following formulas:

LTC3728: TJ= TA+ (PD 95 C/W)

Note 3:The LTC3728 is tested in a feedback loop that servos VITH1, 2to aspecified voltage and measures the resultant VOSENSE1, 2.Note 4:Dynamic supply current is higher due to the gate charge beingdelivered at the switching frequency. See Applications Information.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VEXTVCC EXTVCCSwitchover Voltage ICC= 20mA, EXTVCCRamping Positive l 4.5 4.7 V

VLDOHYS EXTVCCHysteresis 0.2 VOscillator and Phase-Locked Loop

fNOM Nominal Frequency VPLLFLTR= 1.2V 360 400 440 kHz

fLOW Lowest Frequency VPLLFLTR= 0V 230 260 290 kHz

fHIGH Highest Frequency VPLLFLTR 2.4V 480 550 590 kHz

RPLLIN PLLIN Input Resistance 50 k

IPLLFLTR Phase Detector Output Current Sinking Capability Sourcing Capability

fPLLIN< fOSCfPLLIN> fOSC

1515

AA

3.3V Linear Regulator

V3.3OUT 3.3V Regulator Output Voltage No Load l 3.25 3.35 3.45 V

V3.3IL 3.3V Regulator Load Regulation I3.3= 0 to 10mA 0.5 2 %

V3.3VL 3.3V Regulator Line Regulation 6V < VIN< 30V 0.05 0.2 %

I3.3LEAK Leakage Current of 3.3V Regulator inShutdown

VRUN/SS1, 2= 0V, VIN= 30V l 10 50 A

PGOOD Output

VPGL PGOOD Voltage Low IPGOOD= 2mA 0.1 0.3 V

IPGOOD PGOOD Leakage Current VPGOOD= 5V 1 A

VPG PGOOD Trip Level, Either Controller VOSENSEwith Respect to Set Output Voltage VOSENSERamping Negative VOSENSERamping Positive

6 6

7.5 7.5

9.5 9.5

%%

Note 5:Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.Note 6:The IC minimum on-time is tested under an ideal conditionwithout external power FETs. It can be different when the IC is working inan actual circuit. See Minimum On-Time Considerations in the ApplicationInformation section.

Note 7:The LTC3728E is guaranteed to meet performance specificationsfrom 0C to 70C. Specifications over the 40C to 85C operatingtemperature range are assured by design, characterization and correlationwith statistical process controls.


6/37

LTC3728

5

3728fd

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Output Current andMode (Figure 13)

Efficiency vs Output Current(Figure 13)

Efficiency vs Input Voltage(Figure 13)

Supply Current vs Input Voltageand Mode (Figure 13) EXTVCCVoltage Drop

INTVCCand EXTVCCSwitchVoltage vs Temperature

Internal 5V LDO Line Regulation Maximum Current SenseThreshold vs Duty Factor

Maximum Current SenseThreshold vs Percent of NominalOutput Voltage (Foldback)

OUTPUT CURRENT (A)

0.0010

EFFICIENCY(%)

10

30

40

50

100

70

0.01 0.1 1

3728 G01

20

80

90

60

10

FORCEDCONTINUOUSMODE (PWM)

CONSTANTFREQUENCY(BURST DISABLE)

Burst ModeOPERATION

VIN= 15VVOUT= 5Vf = 250kHz

OUTPUT CURRENT (A)

0.001

EFFICIENCY(%)

70

80

10

3728 G02

60

500.01 0.1 1

100

90

VIN= 10V

VIN= 15V

VIN= 7V

VIN= 20V

VOUT= 5Vf = 250kHz

INPUT VOLTAGE (V)

5

EFFICIENCY(%)

70

80

3728 G03

60

5015 25 35

100

VOUT= 5VIOUT= 3Af = 250kHz

90

INPUT VOLTAGE (V)

0 50

SUPPLYCURRENT(A)

400

1000

10 20 25

3728 G04

200

800

600

15 30 35

BOTHCONTROLLERS ON

SHUTDOWN

CURRENT (mA)

0

E

XTVCCVOLTAGEDROP(mV)

150

200

250

40

3728 G05

100

50

010 20 30 50

TEMPERATURE (C)

50

INTVCC

ANDEXTVCCSWITCHVOLTAGE(V)

4.95

5.00

5.05

25 75

3728 G06

4.90

4.85

25 0 50 100 125

4.80

4.70

4.75

INTVCCVOLTAGE

EXTVCCSWITCHOVER THRESHOLD

INPUT VOLTAGE (V)

0

4.8

4.9

5.1

15 25

3728 G07

4.7

4.6

5 10 20 30 35

4.5

4.4

5.0

INTVCCVOLTAG

E(V)

ILOAD= 1mA

DUTY FACTOR (%)

00

VSENSE(mV

)

25

50

75

20 40 60 80

3728 G08

100

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

0

VSENSE(mV)

40

50

60

100

3728 G09

30

20

025 50 75

10

80

70


7/37

LTC3728

6

3728fd


Maximum Current Sense Thresholdvs VRUN/SS(Soft-Start)

Maximum Current Sense Thresholdvs Sense Common Mode Voltage

Current Sense Threshold vsITHVoltage

Load Regulation VITHvs VRUN/SS SENSE Pins Total Source Current

Mazimum Current SenseThreshold vs Temperature

Dropout Voltage vs Output Current(Figure 14) RUN/SS Current vs Temperature

VRUN/SS(V)

00

VSENSE(mV)

20

40

60

80

1 2 3 4

3728 G10

5 6

VSENSE(CM)= 1.6V

COMMON MODE VOLTAGE (V)

0

VSENSE(mV)

72

76

80

4

3728 G11

68

64

601 2 3 5

VITH(V)

0

VSENSE(mV)

30

50

70

90

2

3728 G12

10

10

20

40

60

80

0

20

300.5 1 1.5 2.5

LOAD CURRENT (A)

0

NORMALIZEDVOUT(%)

0.2

0.1

4

3728 G13

0.3

0.41 2 3 5

0.0FCB = 0VVIN= 15V

VRUN/SS(V)

00

VITH(V)

0.5

1.0

1.5

2.0

2.5

1 2 3 4

3728 G14

5 6

VOSENSE= 0.7V

VSENSECOMMON MODE VOLTAGE (V)

0

ISENSE(A)

0

3728 G15

50

1002 4

50

100

6

TEMPERATURE (C)

50 2570

VSENSE(mV

)

74

80

0 50 75

3728 G17

72

78

76

25 100 125

OUTPUT CURRENT (A)

00

DROPOUTVOLTA

GE(V)

1

2

3

4

0.5 1.0 1.5 2.0

3728 G18

2.5 3.0 3.5 4.0

RSENSE= 0.015

RSENSE= 0.010

VOUT= 5V

TEMPERATURE (C)

50 250

RUN/SSCURREN

T(A)

0.2

0.6

0.8

1.0

75 10050

1.8

3728 G25

0.4

0 25 125

1.2

1.4

1.6


8/37

LTC3728

7

3728fd


Soft-Start Up (Figure 13) Load Step (Figure 13) Load Step (Figure 13)

Input Source/CapacitorInstantaneous Current (Figure 13) Burst Mode Operation (Figure 13)

Constant Frequency (BurstInhibit) Operation (Figure 13)

Current Sense Pin Input Currentvs Temperature

EXTVCCSwitch Resistance vsTemperature

Oscillator Frequency vsTemperature

TEMPERATURE (C)

50 2525

CURRENTSENSEINPUT

CURRENT(A)

29

35

0 50 75

3728 G26

27

33

31

25 100 125

VOUT= 5V

TEMPERATURE (C)

50 250

EXTVCCSWITCHRESISTANCE()

4

10

0 50 75

3728 G27

2

8

6

25 100 125

TEMPERATURE (C)

50

400

500

700

25 75

3728 G28

300

200

25 0 50 100 125

100

0

600

FREQUENCY(

kHz)

VPLLFLTR= 5V

VPLLFLTR= 1.2V

VPLLFLTR= 0V

VIN= 15VVOUT= 5V

5ms/DIV 3728 G19

VRUN/SS5V/DIV

VOUT5V/DIV

IL2A/DIV

VIN= 15VVOUT= 5VVPLLFLTR= 0VLOAD STEP = 0A to 3ABurst Mode OPERATION

20s/DIV 3728 G20

VOUT200mV/DIV

IL2A/DIV

VIN= 15VVOUT= 5VVPLLFLTR= 0VLOAD STEP = 0A to 3ACONTINUOUS OPERATION

20s/DIV 3728 G21

VOUT200mV/DIV

IL2A/DIV

VIN= 15VVOUT= 5VVPLLFLTR= 0VIOUT= IOUT3.3A = 2A

1s/DIV 3728 G22

VSW110V/DIV

VSW210V/DIV

IIN2A/DIV

VIN200mV/DIV

VIN= 15VVOUT= 5VVPLLFLTR= 0VVFCB= OPENIOUT= 20mA

10s/DIV 3728 G23

VOUT20mV/DIV

IL0.5A/DIV

VIN= 15VVOUT= 5VVPLLFLTR= 0VVFCB= 5VIOUT= 20mA

2s/DIV 3728 G24

VOUT20mV/DIV

IL0.5A/DIV


9/37

LTC3728

8

3728fd

RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13):Combinationof soft-start, run control inputs and short-circuit detectiontimers. A capacitor to ground at each of these pins sets theramp time to full output current. Forcing either of these pinsback below 1.0V causes the IC to shut down the circuitryrequired for that particular controller. Latchoff overcurrentprotection is also invoked via this pin as described in the

Applications Information section.SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12): The (+)Input to the Differential Current Comparators. The Ithpinvoltage and controlled offsets between the SENSEandSENSE+pins in conjunction with RSENSEset the currenttrip threshold.

SENSE1, SENSE2 (Pins 3, 13/Pins 31, 11): The ()Input to the Differential Current Comparators.

VOSENSE1, VOSENSE2(Pins 4, 12/Pins 1, 9):Receives theremotely-sensed feedback voltage for each controller from

an external resistive divider across the output.

PLLFLTR (Pin 5/Pin 2):The Phase-Locked Loops LowpassFilter is Tied to This Pin. Alternatively, this pin can be drivenwith an AC or DC voltage source to vary the frequency ofthe internal oscillator.

PLLIN (Pin 6/Pin 3):External Synchronization Input toPhase Detector. This pin is internally terminated to SGND

with 50k. The phase-locked loop will force the risingtop gate signal of controller 1 to be synchronized withthe rising edge of the PLLIN signal.

FCB (Pin 7/Pin 4): Forced Continuous Control Input.This input acts on both controllers and is normally usedto regulate a secondary winding. Pulling this pin below0.8V will force continuous synchronous operation.

ITH1, ITH2(Pins 8, 11/Pins 5, 8):Error Amplifier Outputand Switching Regulator Compensation Point. Each as-sociated channels current comparator trip point increaseswith this control voltage.

SGND (Pin 9/Pin 6):Small Signal Ground common toboth controllers, must be routed separately from highcurrent grounds to the common () terminals of theCOUT capacitors.

3.3VOUT(Pin 10/Pin 7):Output of a linear regulator ca-pable of supplying 10mA DC with peak currents as highas 50mA.

NC (Pins 10, 16, 29, 32 UH Package Only):No Connect.

PGND (Pin 20/Pin 19):Driver Power Ground. Connects tothe sources of bottom (synchronous) N-channel MOSFETs,anodes of the Schottky rectifiers and the () terminal(s)of CIN.

G Package/UH Package


Undervoltage Lockout vsTemperature

Shutdown Latch Thresholds vsTemperature

TEMPERATURE (C)

50

UNDERVOLTAGELOCKOUT(V)

3.40

3.45

3.50

25 75

3728 G29

3.35

3.30

25 0 50 100 125

3.25

3.20

TEMPERATURE (C)

50 250

SHUTDOWNLATCHTHRESHOLDS(V)

0.5

1.5

2.0

2.5

75 10050

4.5

3728 G30

1.0

0 25 125

3.0

3.5

4.0 LATCH ARMING

LATCHOFFTHRESHOLD

PIN FUNCTIONS


10/37

LTC3728

9

3728fd

PIN FUNCTIONS

INTVCC(Pin 21/Pin 20):Output of the Internal 5V LinearLow Dropout Regulator and the EXTVCCSwitch. The driverand control circuits are powered from this voltage source.

Must be decoupled to power ground with a minimum of4.7F tantalum or other low ESR capacitor.

EXTVCC (Pin 22/Pin 21): External Power Input to anInternal Switch Connected to INTVCC. This switch closesand supplies VCCpower, bypassing the internallow drop-out regulator, whenever EXTVCCis higher than 4.7V. SeeEXTVCCconnection in Applications section. Do not exceed7V on this pin.

BG1, BG2 (Pins 23, 19/Pins 22, 18):High Current GateDrives for Bottom (Synchronous) N-Channel MOSFETs.

Voltage swing at these pins is from ground to INTVCC.VIN(Pin 24/Pin 23):Main Supply Pin. A bypass capaci-tor should be tied between this pin and the signal groundpin.

BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17):BootstrappedSupplies to the Top Side Floating Drivers. Capacitors

are connected between the boost and switch pins andSchottky diodes are tied between the boost and INTVCCpins. Voltage swing at the boost pins is from INTVCC to

(VIN+ INTVCC).

SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch NodeConnections to Inductors. Voltage swing at these pinsis from a Schottky diode (external) voltage drop belowground to VIN.

TG1, TG2 (Pins 27, 16/Pins 26, 14):High Current GateDrives for Top N-Channel MOSFETs. These are the out-puts of floating drivers with a voltage swing equal toINTVCC 0.5V superimposed on the switch node voltageSW.

PGOOD (Pin 28/Pin 27):Open-Drain Logic Output. PGOODis pulled to ground when the voltage on either VOSENSEpin is not within 7.5% of its set point.

Exposed Pad (Pin 33) SGND:The exposed pad must besoldered to PCB ground for elecrical contact and ratedthermal performance.


11/37

LTC3728

10

3728fd

FUNCTIONAL DIAGRAM

SWITCHLOGIC

+

0.8V

4.7V

5V

VIN

VIN

4.5VBINH

CLK2

CLK1

0.18A

R6

R5

+

FCB

+

+

+

+ VREF

INTERNALSUPPLY

3.3VOUT

VSEC

RLP

CLP

1.5V

FCB

EXTVCC

INTVCC

SGND

+

5VLDOREG

SW

SHDN

0.55V

TOP

BOOST

TG CB

CIND1

DB

PGND

BOTBG

INTVCC

INTVCC

VIN

+

CSEC

COUT

VOUT

3728 FD/F02

DSEC

RSENSE

R2

+

+

VOSENSE

DROPOUTDET

RUNSOFT

START

BOT

TOP ONS

R

Q

Q

OSCILLATOR

PHASE DET

PLLFLTR

PLLIN

FCB

EA

0.86V

0.80V

OV

VFB

1.2A

6V

R1

+

RC

4(VFB)

RST

SHDN

RUN/SS

ITHCC

CC2

CSS

4(VFB)

0.86V

SLOPECOMP

3mV

+

+

SENSE

SENSE+

INTVCC

30k

45k

2.4V

45k

30k

I1 I2

B

DUPLICATE FOR SECONDCONTROLLER CHANNEL

+ +

50k

FIN

+

+

+

+

PGOODVOSENSE1

VOSENSE2

0.86V

0.74V

0.86V

0.74V

Figure 2


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LTC3728

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OPERATION

Main Control Loop

The LTC3728 uses a constant frequency, current mode

step-down architecture with the two controller channelsoperating 180 degrees out of phase. During normal opera-tion, each top MOSFET is turned on when the clock forthat channel sets the RS latch, and turned off when themain current comparator, I1, resets the RS latch. The peakinductor current at which I1 resets the RS latch is controlledby the voltage on the ITH pin, which is the output of eacherror amplifier EA. The VOSENSEpin receives the voltagefeedback signal, which is compared to the internal refer-ence voltage by the EA. When the load current increases,it causes a slight decrease in VOSENSE relative to the 0.8V

reference, which in turn causes the ITHvoltage to increaseuntil the average inductor current matches the new loadcurrent. After the top MOSFET has turned off, the bottomMOSFET is turned on until either the inductor currentstarts to reverse, as indicated by current comparator I2,or the beginning of the next cycle.

The top MOSFET drivers are biased from floating bootstrapcapacitor CB, which normally is recharged during each offcycle through an external diode when the top MOSFETturns off. As VINdecreases to a voltage close to VOUT, theloop may enter dropout and attempt to turn on the top

MOSFET continuously. The dropout detector detects thisand forces the top MOSFET off for about 400ns every tenthcycle to allow CBto recharge.

The main control loop is shut down by pulling the RUN/SS pin low. Releasing RUN/SS allows an internal 1.2Acurrent source to charge soft-start capacitor CSS. WhenCSSreaches 1.5V, the main control loop is enabled withthe ITH voltage clamped at approximately 30% of itsmaximum value. As CSS continues to charge, the ITHpin voltage is gradually released allowing normal, full-

current operation. When both RUN/SS1 and RUN/SS2are low, all LTC3728 controller functions are shut down,including the 5V and 3.3V regulators.

Low Current Operation

The FCB pin is a multifunction pin providing two func-tions: 1) to provide regulation for a secondary windingby temporarily forcing continuous PWM operation onboth controllers; and 2) select between twomodes of

low current operation. When the FCB pin voltage is below0.8V, the controller forces continuous PWM current modeoperation. In this mode, the top and bottom MOSFETs

are alternately turned on to maintain the output voltageindependent of direction of inductor current. When theFCB pin is below VINTVCC 1V but greater than 0.8V,the controller enters Burst Mode operation. Burst Modeoperation sets a minimum output current level beforeinhibiting the top switch and turns off the synchronousMOSFET(s) when the inductor current goes negative. Thiscombination of requirements will, at low currents, forcethe ITHpin below a voltage threshold that will temporarilyinhibit turn-on of both output MOSFETs until the outputvoltage drops. There is 60mV of hysteresis in the burst

comparator B tied to the ITHpin. This hysteresis producesoutput signals to the MOSFETs that turn them on for severalcycles, followed by a variable sleep interval dependingupon the load current. The resultant output voltage rippleis held to a very small value by having the hystereticcomparator after the error amplifier gain block.

Frequency Synchronization

The phase-locked loop allows the internal oscillator tobe synchronized to an external source via the PLLIN pin.

The output of the phase detector at the PLLFLTR pin isalso the DC frequency control input of the oscillator thatoperates over a 250kHz to 550kHz range correspondingto a DC voltage input from 0V to 2.4V. When locked, thePLL aligns the turn on of the top MOSFET to the risingedge of the synchronizing signal. When PLLIN is leftopen, the PLLFLTR pin goes low, forcing the oscillator tominimum frequency.

Constant Frequency Operation

When the FCB pin is tied to INTVCC, Burst Mode opera-

tion is disabled and the forced minimum output currentrequirement is removed. This provides constant frequency,discontinuous (preventing reverse inductor current)current operation over the widest possible output currentrange. This constant frequency operation is not as efficientas Burst Mode operation, but does provide a lower noise,constant frequency operating mode down to approximately1% of designed maximum output current.

(Refer to Functional Diagram)


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OPERATION

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous current

operation. This is the least efficient operating mode, butmay be desirable in certain applications. The output cansource or sink current in this mode. When sinking currentwhile in forced continuous operation, current will be forcedback into the main power supply.

INTVCC/EXTVCCPower

Power for the top and bottom MOSFET drivers and mostother internal circuitry is derived from the INTVCCpin. Whenthe EXTVCCpin is left open, an internal 5V low dropoutlinear regulator supplies INTVCCpower. If EXTVCCis taken

above 4.7V, the 5V regulator is turned off and an internalswitch is turned on connecting EXTVCCto INTVCC. This al-lows the INTVCCpower to be derived from a high efficiencyexternal source such as the output of the regulator itselfor a secondary winding, as described in the ApplicationsInformation section.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transientovershoots (>7.5%) as well as other more serious condi-tions that may overvoltage the output. In this case, the topMOSFET is turned off and the bottom MOSFET is turnedon until the overvoltage condition is cleared.

Power Good (PGOOD) Pin

The PGOOD pin is connected to an open drain of an internalMOSFET. The MOSFET turns on and pulls the pin low wheneither output is not within 7.5% of the nominal outputlevel as determined by the resistive feedback divider. Whenboth outputs meet the 7.5% requirement, the MOSFET isturned off within 10s and the pin is allowed to be pulled

up by an external resistor to a source of up to 7V.

Foldback Current, Short-Circuit Detectionand Short-Circuit Latchoff

The RUN/SS capacitors are used initially to limit the inrushcurrent of each switching regulator. After the controllerhas been started and been given adequate time to chargeup the output capacitors and provide full load current, theRUN/SS capacitor is used in a short-circuit time-out circuit.If the output voltage falls to less than 70% of its nominaloutput voltage, the RUN/SS capacitor begins dischargingon the assumption that the output is in an overcurrentand/or short-circuit condition. If the condition lasts fora long enough period as determined by the size of theRUN/SS capacitor, the controller will be shut down until

the RUN/SS pin(s) voltage(s) are recycled. This built-inlatchoff can be overridden by providing a >5A pull-upat a compliance of 5V to the RUN/SS pin(s). This currentshortens the soft start period but also prevents net dis-charge of the RUN/SS capacitor(s) during an overcurrentand/or short-circuit condition. Foldback current limitingis also activated when the output voltage falls below70% of its nominal level whether or not the short-circuitlatchoff circuit is enabled. Even if a short is present andthe short-circuit latchoff is not enabled, a safe, low outputcurrent is provided due to internal current foldback and

actual power wasted is low due to the efficient nature ofthe current mode switching regulator.

THEORY AND BENEFITS OF 2-PHASE OPERATION

The LTC1628 and the LTC3728 dual high efficiency DC/DCcontrollers bring the considerable benefits of 2-phase op-eration to portable applications for the first time. Notebookcomputers, PDAs, handheld terminals and automotiveelectronics will all benefit from the lower input filter-ing requirement, reduced electromagnetic interference

(EMI) and increased efficiency associated with 2-phaseoperation.



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OPERATION

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching RegulatorsConverting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator AllowsLess Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency

IIN(MEAS)= 1.55ARMSIIN(MEAS)= 2.53ARMS3728 F03b3728 F03a

3.3V SWITCH20V/DIV

5V SWITCH20V/DIV

INPUT CURRENT5A/DIV

INPUT VOLTAGE500mV/DIV

(a) (b)

Why the need for 2-phase operation? Up until the 2-phase family, constant-frequency dual switching regula-tors operated both channels in phase (i.e., single-phaseoperation). This means that both switches turned on atthe same time, causing current pulses of up to twice theamplitude of those for one regulator to be drawn from theinput capacitor and battery. These large amplitude currentpulses increased the total RMS current flowing from theinput capacitor, requiring the use of more expensive input

capacitors and increasing both EMI and losses in the inputcapacitor and battery.

With 2-phase operation, the two channels of the dual-switching regulator are operated 180 degrees out of phase.This effectively interleaves the current pulses drawn by theswitches, greatly reducing the overlap time where they addtogether. The result is a significant reduction in total RMSinput current, which in turn allows less expensive inputcapacitors to be used, reduces shielding requirements forEMI and improves real world operating efficiency.

Figure 3 compares the input waveforms for a representa-tive single-phase dual switching regulator to the LTC16282-phase dual switching regulator. An actual measurementof the RMS input current under these conditions shows

that 2-phase operation dropped the input current from2.53ARMS to 1.55ARMS. While this is an impressivereduction in itself, remember that the power losses areproportional to IRMS

2, meaning that the actual power wastedis reduced by a factor of 2.66. The reduced input ripplevoltage also means less power is lost in the input powerpath, which could include batteries, switches, trace/con-nector resistances and protection circuitry. Improvementsin both conducted and radiated EMI also directly accrue asa result of the reduced RMS input current and voltage.

Of course, the improvement afforded by 2-phase opera-tion is a function of the dual switching regulators relativeduty cycles which, in turn, are dependent upon the inputvoltage VIN(Duty Cycle = VOUT/VIN). Figure 4 shows howthe RMS input current varies for single-phase and 2-phaseoperation for 3.3V and 5V regulators over a wide inputvoltage range.

It can readily be seen that the advantages of 2-phase opera-tion are not just limited to a narrow operating range, but

in fact extend over a wide region. A good rule of thumbfor most applications is that 2-phase operation will reducethe input capacitor requirement to that for just one channeloperating at maximum current and 50% duty cycle.



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OPERATION

A final question: If 2-phase operation offers such an ad-vantage over single-phase operation for dual switchingregulators, why hasnt it been done before? The answer

is that, while simple in concept, it is hard to implement.Constant-frequency current mode switching regula-tors require an oscillator derived slope compensationsignal to allow stable operation of each regulator at over50% duty cycle. This signal is relatively easy to derive insingle-phase dual switching regulators, but required thedevelopment of a new and proprietary technique to allow2-phase operation. In addition, isolation between the twochannels becomes more critical with 2-phase operationbecause switch transitions in one channel could potentiallydisrupt the operation of the other channel.

These 2-phase parts are proof that these hurdles havebeen surmounted. They offer unique advantages for theever-expanding number of high efficiency power suppliesrequired in portable electronics.

INPUT VOLTAGE (V)

0

INPUTRMSCURRENT(A)

3.0

2.5

2.0

1.5

1.0

0.5

010 20 30 40

3728 F04

SINGLE PHASEDUAL CONTROLLER

2-PHASEDUAL CONTROLLER

VO1= 5V/3AVO2= 3.3V/3A

Figure 4. RMS Input Current Comparison



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Figure 1 on the first page is a basic LTC3728 applicationcircuit. External component selection is driven by theload requirement, and begins with the selection of RSENSE

and the inductor value. Next, the power MOSFETs andD1 are selected. Finally, CINand COUTare selected. Thecircuit shown in Figure 1 can be configured for operationup to an input voltage of 28V (limited by the externalMOSFETs).

RSENSESelection For Output Current

RSENSEis chosen based on the required output current. TheLTC3728 current comparator has a maximum thresholdof 75mV/RSENSE and an input common mode range of

SGND to 1.1(INTVCC). The current comparator thresholdsets the peak of the inductor current, yielding a maximumaverage output current IMAXequal to the peak value lesshalf the peak-to-peak ripple current, IL.

Allowing a margin for variations in the LTC3728 and externalcomponent values yields:

RSENSE =50mV

IMAX

Because of possible PCB noise in the current sensing loop,

the AC current sensing ripple of VSENSE= I RSENSEalso needs to be checked in the design to get good sig-nal-to-noise ratio. In general, for a reasonable good PCBlayout, a 15mV VSENSE voltage is recommended as aconservative number to start with.

When using the controller in very low dropout conditions,the maximum output current level will be reduced due tothe internal compensation required to meet stability cri-terion for buck regulators operating at greater than 50%duty factor. A curve is provided to estimate this reductonin peak output current level depending upon the operatingduty factor.

Operating Frequency

The LTC3728 uses a constant frequency phase-lockablearchitecture with the frequency determined by an internalcapacitor. This capacitor is charged by a fixed current plusan additional current which is proportional to the voltageapplied to the PLLFLTR pin. Refer to Phase-Locked Loop

APPLICATIONS INFORMATION

and Frequency Synchronization in the Applications Infor-mation section for additional information.

A graph for the voltage applied to the PLLFLTR pin vsfrequency is given in Figure 5. As the operating frequencyis increased the gate charge losses will be higher, reducingefficiency (see Efficiency Considerations). The maximumswitching frequency is approximately 550kHz.

Inductor Value Calculation

The operating frequency and inductor selection are inter-related in that higher operating frequencies allow the useof smaller inductor and capacitor values. So why wouldanyone ever choose to operate at lower frequencies withlarger components? The answer is efficiency. A higherfrequency generally results in lower efficiency becauseof MOSFET gate charge losses. In addition to this basictrade-off, the effect of inductor value on ripple current andlow current operation must also be considered.

The inductor value has a direct effect on ripple current.The inductor ripple current IL decreases with higher

inductance or frequency and increases with higher VIN:

IL =1

(f)(L)VOUT 1

VOUTVIN

Accepting larger values of IL allows the use of lowinductances, but results in higher output voltage rippleand greater core losses. A reasonable starting point forsetting ripple current is IL=0.3(IMAX) or higher for good

Figure 5. PPLFLTR Pin Voltage vs Frequency

OPERATING FREQUENCY (kHz)

200 250 300 350 550400 450 500

PLLFLTRPINVOLTAGE

(V)

3728 F05

2.5

2.0

1.5

1.0

0.5

0


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LTC3728

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load transient response and sufficient ripple current sig-nal in the current loop. The maximum ILoccurs at themaximum input voltage.

The inductor value also has secondary effects. The tran-sition to Burst Mode operation begins when the averageinductor current required results in a peak current below25% of the current limit determined by RSENSE. Lowerinductor values (higher IL) will cause this to occur atlower load currents, which can cause a dip in efficiency inthe upper range of low current operation. In Burst Modeoperation, lower inductance values will cause the burstfrequency to decrease.

Inductor Core SelectionOnce the value for L is known, the type of inductor mustbe selected. High efficiency converters generally cannotafford the core loss found in low cost powdered iron cores,forcing the use of more expensive ferrite, molypermalloy,or Kool Mcores. Actual core loss is independent of coresize for a fixed inductor value, but it is very dependenton inductance selected. As inductance increases, corelosses go down. Unfortunately, increased inductancerequires more turns of wire and therefore copper losseswill increase.

Ferrite designs have very low core loss and are preferredat high switching frequencies, so design goals can con-centrate on copper loss and preventing saturation. Ferritecore material saturates hard, which means that induc-tance collapses abruptly when the peak design current isexceeded. This results in an abrupt increase in inductorripple current and consequent output voltage ripple. Donot allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, lowloss core material for toroids, but it is more expensive

than ferrite. A reasonable compromise from the samemanufacturer is Kool M. Toroids are very space efficient,especially when you can use several layers of wire. Becausethey generally lack a bobbin, mounting is more difficult.However, designs for surface mount are available that donot increase the height significantly.


Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for each

controller in the LTC3728: One N-channel MOSFET forthe top (main) switch, and one N-channel MOSFET forthe bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTVCCvoltage. This voltage is typically 5V during start-up(see EXTVCCPin Connection). Consequently, logic-levelthreshold MOSFETs must be used in most applications.The only exception is if low input voltage is expected(VIN < 5V); then, sub-logic level threshold MOSFETs(VGS(TH)< 3V) should be used. Pay close attention to theBVDSSspecification for the MOSFETs as well; most of the

logic level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the ONresistance RDS(ON), reverse transfer capacitance CRSS, inputvoltage and maximum output current. When the LTC3728is operating in continuous mode the duty cycles for thetop and bottom MOSFETs are given by:

Main Switch Duty Cycle =VOUTVIN

Synchronous Switch Duty Cycle

=

VIN VOUTVIN

The MOSFET power dissipations at maximum outputcurrent are given by:

PMAIN =VOUTVIN

IMAX( )2

1+( )RDS(ON) +

k VIN( )2

IMAX( ) CRSS( ) f( )

PSYNC=

VIN VOUT

VIN IMAX( )

2

1+

( )RDS(ON)

where is the temperature dependency of RDS(ON)and kis a constant inversely related to the gate drive current.

Both MOSFETs have I2R losses while the topside N-channelequation includes an additional term for transition losses,


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which are highest at high input voltages. For VIN< 20Vthe high current efficiency generally improves with largerMOSFETs, while for VIN> 20V the transition losses rapidly

increase to the point that the use of a higher RDS(ON)devicewith lower CRSSactually provides higher efficiency. Thesynchronous MOSFET losses are greatest at high inputvoltage when the top switch duty factor is low or duringa short-circuit when the synchronous switch is on closeto 100% of the period.

The term (1+) is generally given for a MOSFET in theform of a normalized RDS(ON)vs Temperature curve, but= 0.005/C can be used as an approximation for lowvoltage MOSFETs. CRSSis usually specified in the MOSFET

characteristics. The constant k = 1.7 can be used to esti-mate the contributions of the two terms in the main switchdissipation equation.

The Schottky diode D1 shown in Figure 1 conducts dur-ing the dead-time between the conduction of the twopower MOSFETs. This prevents the body diode of thebottom MOSFET from turning on, storing charge duringthe dead-time and requiring a reverse recovery periodthat could cost as much as 3% in efficiency at high V IN.A 1A to 3A Schottky is generally a good compromise forboth regions of operation due to the relatively small aver-

age current. Larger diodes result in additional transitionlosses due to their larger junction capacitance. Schottkydiodes should be placed in parallel with the synchronousMOSFETs when operating in pulse-skip mode or in BurstMode operation.

CINand COUTSelection

The selection of CIN is simplified by the multiphase ar-chitecture and its impact on the worst-case RMS currentdrawn through the input network (battery/fuse/capacitor).

It can be shown that the worst case RMS current occurswhen only one controller is operating. The controller withthe highest (VOUT)(IOUT) product needs to be used in theformula below to determine the maximum RMS current

requirement. Increasing the output current, drawn fromthe other out-of-phase controller, will actually decrease theinput RMS ripple current from this maximum value (see

Figure 4). The out-of-phase technique typically reducesthe input capacitors RMS ripple current by a factor of30% to 70% when compared to a single phase powersupply solution.

The type of input capacitor, value and ESR rating haveefficiency effects that need to be considered in the selec-tion process. The capacitance value chosen should besufficient to store adequate charge to keep high peakbattery currents down. 20F to 40F is usually sufficientfor a 25W output supply operating at 200kHz. The ESR of

the capacitor is important for capacitor power dissipationas well as overall battery efficiency. All of the power (RMSripple current ESR) not only heats up the capacitor butwastes power from the battery.

Medium voltage (20V to 35V) ceramic, tantalum, OS-CONand switcher-rated electrolytic capacitors can be usedas input capacitors, but each has drawbacks: ceramicvoltage coefficients are very high and may have audiblepiezoelectric effects; tantalums need to be surge-rated;OS-CONs suffer from higher inductance, larger case sizeand limited surface-mount applicability; electrolytics

higher ESR and dryout possibility require several to beused. Multiphase systems allow the lowest amount ofcapacitance overall. As little as one 22F or two to three10F ceramic capacitors are an ideal choice in a 20W to35W power supply due to their extremely low ESR. Eventhough the capacitance at 20V is substantially below theirrating at zero-bias, very low ESR loss makes ceramicsan ideal candidate for highest efficiency battery operatedsystems. Also consider parallel ceramic and high qualityelectrolytic capacitors as an effective means of achievingESR and bulk capacitance goals.

In continuous mode, the source current of the top N-channelMOSFET is a square wave of duty cycle VOUT/VIN. To preventlarge voltage transients, a low ESR input capacitor sized for


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the maximum RMS current of one channel must be used.The maximum RMS capacitor current is given by:

CINRequiredIRMS IMAXVOUT VINVOUT( )

1/2

VIN

This formula has a maximum at VIN = 2VOUT, whereIRMS= IOUT/2. This simple worst case condition is com-monly used for design because even significant deviationsdo not offer much relief. Note that capacitor manufacturersripple current ratings are often based on only 2000 hoursof life. This makes it advisable to further derate the capaci-tor, or to choose a capacitor rated at a higher temperaturethan required. Several capacitors may also be paralleledto meet size or height requirements in the design. Alwaysconsult the manufacturer if there is any question.

The benefit of the LTC3728 multiphase can be calculated byusing the equation above for the higher power controllerand then calculating the loss that would have resulted ifboth controller channels switch on at the same time. Thetotal RMS power lost is lower when both controllers areoperating due to the interleaving of current pulses throughthe input capacitors ESR. This is why the input capacitorsrequirement calculated above for the worst-case controller

is adequate for the dual controller design. Remember thatinput protection fuse resistance, battery resistance and PCboard trace resistance losses are also reduced due to thereduced peak currents in a multiphase system. The overallbenefit of a multiphase design will only be fully realizedwhen the source impedance of the power supply/batteryis included in the efficiency testing. The drains of thetwo top MOSFETS should be placed within 1cm of eachother and share a common CIN(s). Separating the drainsand CIN may produce undesirable voltage and currentresonances at VIN.

The selection of COUTis driven by the required effectiveseries resistance (ESR). Typically once the ESR require-ment is satisfied the capacitance is adequate for filtering.

The output ripple (VOUT) is determined by:

VOUT IL ESR+1

8fCOUT

Where f = operating frequency, COUT= output capacitance,andIL= ripple current in the inductor. The output ripple ishighest at maximum input voltage sinceILincreases withinput voltage. WithIL= 0.3IOUT(MAX)the output ripple willtypically be less than 50mV at max VINassuming:

COUTRecommended ESR < 2 RSENSE

and COUT> 1/(8fRSENSE)

The first condition relates to the ripple current into the ESR

of the output capacitance while the second term guaranteesthat the output capacitance does not significantly dischargeduring the operating frequency period due to ripple current.The choice of using smaller output capacitance increasesthe ripple voltage due to the discharging term but can becompensated for by using capacitors of very low ESR tomaintain the ripple voltage at or below 50mV. The ITHpinOPTI-LOOP compensation components can be optimizedto provide stable, high performance transient responseregardless of the output capacitors selected.

Manufacturers such as Nichicon, United Chemicon andSanyo can be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectriccapacitor available from Sanyo has the lowest (ESR)(size)product of any aluminum electrolytic at a somewhathigher price. An additional ceramic capacitor in parallelwith OS-CON capacitors is recommended to reduce theinductance effects.

In surface mount applications multiple capacitors mayneed to be used in parallel to meet the ESR, RMS currenthandling and load step requirements of the application.

Aluminum electrolytic, dry tantalum and special polymercapacitors are available in surface mount packages. Specialpolymer surface mount capacitors offer very low ESR but


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have lower storage capacity per unit volume than othercapacitor types. These capacitors offer a very cost-effec-tive output capacitor solution and are an ideal choice when

combined with a controller having high loop bandwidth.Tantalum capacitors offer the highest capacitance densityand are often used as output capacitors for switchingregulators having controlled soft-start. Several excellentsurge-tested choices are the AVX TPS, AVX TPSV or theKEMET T510 series of surface mount tantalums, availablein case heights ranging from 2mm to 4mm. Aluminumelectrolytic capacitors can be used in cost-driven ap-plications providing that consideration is given to ripplecurrent ratings, temperature and long term reliability. Atypical application will require several to many aluminum

electrolytic capacitors in parallel. A combination of theabove mentioned capacitors will often result in maximizingperformance and minimizing overall cost. Other capacitortypes include Nichicon PL series, NEC Neocap, CornellDubilier ESRE and Sprague 595D series. Consult manu-facturers for other specific recommendations.

INTVCCRegulator

An internal P-channel low dropout regulator produces 5Vat the INTVCCpin from the VINsupply pin. INTVCCpow-

ers the drivers and internal circuitry within the LTC3728.The INTVCCpin regulator can supply a peak current of50mA and must be bypassed to ground with a minimumof 4.7F tantalum, 10F special polymer, or low ESR typeelectrolytic capacitor. A 1F ceramic capacitor placed di-rectly adjacent to the INTVCCand PGND IC pins is highlyrecommended. Good bypassing is necessary to supplythe high transient currents required by the MOSFET gatedrivers and to prevent interaction between channels.

Higher input voltage applications in which large MOSFETsare being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3728 to beexceeded. The system supply current is normally dominatedby the gate charge current. Additional external loading ofthe INTVCCand 3.3V linear regulators also needs to betaken into account for the power dissipation calculations.The total INTVCCcurrent can be supplied by either the 5Vinternal linear regulator or by the EXTVCCinput pin. When

the voltage applied to the EXTVCCpin is less than 4.7V, allof the INTVCCcurrent is supplied by the internal 5V linearregulator. Power dissipation for the IC in this case is high-

est: (VIN)(IINTVCC), and overall efficiency is lowered. Thegate charge current is dependent on operating frequencyas discussed in the Efficiency Considerations section.The junction temperature can be estimated by using theequations given in Note 2 of the Electrical Characteristics.For example, the LTC3728 VINcurrent is limited to lessthan 24mA from a 24V supply when not using the EXTVCCpin as follows:

TJ= 70C + (24mA)(24V)(95C/W) = 125C

Use of the EXTVCC input pin reduces the junction tem-

perature to:

TJ= 70C + (24mA)(5V)(95C/W) = 81C

Dissipation should be calculated to also include any addedcurrent drawn from the internal 3.3V linear regulator.To prevent maximum junction temperature from beingexceeded, the input supply current must be checked op-erating in continuous mode at maximum VIN.

EXTVCCConnection

The LTC3728 contains an internal P-channel MOSFETswitch connected between the EXTVCCand INTVCCpins.When the voltage applied to EXTVCC rises above 4.7V,the internal regulator is turned off and the switch closes,connecting the EXTVCC pin to the INTVCC pin therebysupplying internal power. The switch remains closed aslong as the voltage applied to EXTVCCremains above 4.5V.This allows the MOSFET driver and control power to bederived from the output during normal operation (4.7V< VOUT< 7V) and from the internal regulator when theoutput is out of regulation (start-up, short-circuit). If more

current is required through the EXTVCC switch than isspecified, an external Schottky diode can be added betweenthe EXTVCCand INTVCCpins. Do not apply greater than 7Vto the EXTVCCpin and ensure that EXTVCC < VIN.

Significant efficiency gains can be realized by poweringINTVCCfrom the output, since the VINcurrent resultingfrom the driver and control currents will be scaled by a


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factor of (Duty Cycle)/(Efficiency). For 5V regulators thissupply means connecting the EXTVCCpin directly to VOUT.However, for 3.3V and other lower voltage regulators,

additional circuitry is required to derive INTVCC powerfrom the output.

The following list summarizes the four possible connec-tions for EXTVCC:

1. EXTVCCLeft Open (or Grounded). This will cause INTVCCto be powered from the internal 5V regulator resulting in anefficiency penalty of up to 10% at high input voltages.

2. EXTVCCConnected directly to VOUT. This is the normalconnection for a 5V regulator and provides the highest

efficiency.3. EXTVCCConnected to an External supply. If an externalsupply is available in the 5V to 7V range, it may be used topower EXTVCCproviding it is compatible with the MOSFETgate drive requirements.

4. EXTVCCConnected to an Output-Derived Boost Network.For 3.3V and other low voltage regulators, efficiency gainscan still be realized by connecting EXTVCCto an output-derived voltage that has been boosted to greater than 4.7V.This can be done with either the inductive boost windingas shown in Figure 6a or the capacitive charge pumpshown in Figure 6b. The charge pump has the advantageof simple magnetics.

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitors CBconnected to the BOOST

pins supply the gate drive voltages for the topside MOSFETs.Capacitor CBin the functional diagram is charged thoughexternal diode DBfrom INTVCCwhen the SW pin is low.When one of the topside MOSFETs is to be turned on,the driver places the CBvoltage across the gate-sourceof the desired MOSFET. This enhances the MOSFET andturns on the topside switch. The switch node voltage, SW,rises to VINand the BOOST pin follows. With the topsideMOSFET on, the boost voltage is above the input supply:VBOOST = VIN+ VINTVCC. The value of the boost capacitorCBneeds to be 100 times that of the total input capacitance

of the topside MOSFET(s). The reverse breakdown of theexternal Schottky diode must be greater than VIN(MAX).When adjusting the gate drive level, the final arbiter is thetotal input current for the regulator. If a change is madeand the input current decreases, then the efficiency hasimproved. If there is no change in input current, then thereis no change in efficiency.

Output Voltage

The LTC3728 output voltages are each set by an exter-nal feedback resistive divider carefully placed across

the output capacitor. The resultant feedback signal iscompared with the internal precision 0.800V voltage

EXTVCC

FCB

SGND

VIN

TG1

SW

BG1

PGND

LTC3728

RSENSEVOUT

VSEC

+COUT

+1F

3728 F06a

N-CH

N-CH

R6

+CIN

VIN

T1

1:N

OPTIONAL EXTVCCCONNECTION5V < VSEC< 7V

R5

EXTVCC

VIN

TG1

SW

BG1

PGND

LTC3728

RSENSEVOUT

VN2222LL

+COUT

3728 F06b

N-CH

N-CH

+CIN

+1F

VIN

L1

BAT85 BAT85

BAT85

0.22F

Figure 6a. Secondary Output Loop & EXTVCCConnection Figure 6b. Capacitive Charge Pump for EXTVCC


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reference by the error amplifier. The output voltage is givenby the equation:

VOUT =0.8V 1+ R2R1

where R1 and R2 are defined in Figure 2.

SENSE+/SENSEPINS

The common mode input range of the current comparatorsense pins is from 0V to (1.1)INTVCC. Continuous linearoperation is guaranteed throughout this range allowingoutput voltage setting from 0.8V to 7.7V, depending upon

the voltage applied to EXTVCC. A differential NPN inputstage is biased with internal resistors from an internal 2.4Vsource as shown in the Functional Diagram. This requiresthat current either be sourced or sunk from the SENSEpins depending on the output voltage. If the output voltageis below 2.4V current will flow out of both SENSE pins tothe main output. The output can be easily preloaded bythe VOUTresistive divider to compensate for the currentcomparators negative input bias current. The maximumcurrent flowing out of each pair of SENSE pins is:

ISENSE++ ISENSE

= (2.4V VOUT)/24k

Since VOSENSEis servoed to the 0.8V reference voltage,we can choose R1 in Figure 2 to have a maximum valueto absorb this current.

R1(MAX) =24k 0.8V

2.4V VOUT

for VOUT < 2.4V

Regulating an output voltage of 1.8V, the maximum valueof R1 should be 32K. Note that for an output voltage above

2.4V, R1 has no maximum value necessary to absorb thesense currents; however, R1 is still bounded by the VOSENSEfeedback current.

Soft-Start/Run Function

The RUN/SS1 and RUN/SS2 pins are multipurpose pins

that provide a soft-start function and a means to shut downthe LTC3728. Soft-start reduces the input power sourcessurge currents by gradually increasing the controllerscurrent limit (proportional to VITH). This pin can also beused for power supply sequencing.

An internal 1.2A current source charges up the CSScapaci-tor.When the voltage on RUN/SS1 (RUN/SS2) reaches 1.5V,the particular controller is permitted to start operating. Asthe voltage on RUN/SS increases from 1.5V to 3.0V, theinternal current limit is increased from 25mV/RSENSEto75mV/RSENSE. The output current limit ramps up slowly,

taking an additional 1.25s/F to reach full current. Theoutput current thus ramps up slowly, reducing the start-ing surge current required from the input power supply.If RUN/SS has been pulled all the way to ground there isa delay before starting of approximately:

tDELAY =1.5V

1.2ACSS = 1.25s /F( )CSS

tIRAMP =3V 1.5V

1.2A CSS = 1.25s /F( )CSS

By pulling both RUN/SS pins below 1V, the LTC3728 isput into low current shutdown (IQ = 20A). The RUN/SSpins can be driven directly from logic as shown in Figure7. Diode D1 in Figure 7 reduces the start delay but allowsCSSto ramp up slowly providing the soft-start function.Each RUN/SS pin has an internal 6V zener clamp (SeeFunctional Diagram).

Fault Conditions: Overcurrent Latchoff

The RUN/SS pins also provide the ability to latch off the

controller(s) when an overcurrent condition is detected.The RUN/SS capacitor, CSS, is used initially to turn onand limit the inrush current. After the controller has been


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started and been given adequate time to charge up theoutput capacitor and provide full load current, the RUN/SScapacitor is used for a short-circuit timer. If the regulators

output voltage falls to less than 70% of its nominal valueafter CSSreaches 4.1V, CSSbegins discharging on the as-sumption that the output is in an overcurrent condition. Ifthe condition lasts for a long enough period as determinedby the size of the CSSand the specified discharge current,the controller will be shut down until the RUN/SS pin volt-age is recycled. If the overload occurs during start-up, thetime can be approximated by:

tLO1 [CSS (4.1 1.5 + 4.1 3.5)]/(1.2A)= 2.7 106(CSS)

If the overload occurs after start-up the voltage on CSSwillbegin discharging from the zener clamp voltage:

tLO2 [CSS(6 3.5)]/(1.2A) = 2.1 106(CSS)

This built-in overcurrent latchoff can be overridden byproviding a pull-up resistor to the RUN/SS pin as shownin Figure 7. This resistance shortens the soft-start periodand prevents the discharge of the RUN/SS capacitor duringan over current condition. Tying this pull-up resistor toVINas in Figure 7a, defeats overcurrent latchoff. Diode-connecting this pull-up resistor to INTVCC, as in Figure

7b, eliminates any extra supply current during controllershutdown while eliminating the INTVCC loading frompreventing controller start-up.

Why should you defeat overcurrent latchoff? During theprototyping stage of a design, there may be a problemwith noise pickup or poor layout causing the protectioncircuit to latch off. Defeating this feature will easily allowtroubleshooting of the circuit and PC layout. The internalshort-circuit and foldback current limiting still remainsactive, thereby protecting the power supply system from

failure. After the design is complete, a decision can bemade whether to enable the latchoff feature.

The value of the soft-start capacitor CSSmay need to bescaled with output voltage, output capacitance and loadcurrent characteristics. The minimum soft-start capaci-

tance is given by:

CSS> (COUT)(VOUT) (104) (RSENSE)

The minimum recommended soft-start capacitor ofCSS = 0.1F will be sufficient for most applications.

Fault Conditions: Current Limit and Current Foldback

The LTC3728 current comparator has a maximum sensevoltage of 75mV resulting in a maximum MOSFET cur-rent of 75mV/RSENSE. The maximum value of currentlimit generally occurs with the largest V

INat the highest

ambient temperature, conditions that cause the highestpower dissipation in the top MOSFET.

The LTC3728 includes current foldback to help furtherlimit load current when the output is shorted to ground.The foldback circuit is active even when the overloadshutdown latch described above is overridden. If theoutput falls below 70% of its nominal output level, thenthe maximum sense voltage is progressively lowered from75mV to 25mV. Under short-circuit conditions with verylow duty cycles, the LTC3728 will begin cycle skipping in

order to limit the short-circuit current. In this situationthe bottom MOSFET will be dissipating most of the powerbut less than in normal operation. The short-circuit ripplecurrent is determined by the minimum on-time tON(MIN)of the LTC3728 (less than 200ns), the input voltage andinductor value:

IL(SC)= tON(MIN)(VIN/L)

The resulting short-circuit current is:

ISC =25mV

RSENSE

+1

2

IL(SC)


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Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator risesmuch higher than nominal levels. The crowbar causes hugecurrents to flow, that blow the fuse to protect against ashorted top MOSFET if the short occurs while the control-ler is operating.

A comparator monitors the output for overvoltage con-ditions. The comparator (OV) detects overvoltage faultsgreater than 7.5% above the nominal output voltage. Whenthis condition is sensed, the top MOSFET is turned off andthe bottom MOSFET is turned on until the overvoltagecondition is cleared. The output of this comparator is

only latched by the overvoltage condition itself and willtherefore allow a switching regulator system having a poorPC layout to function while the design is being debugged.The bottom MOSFET remains on continuously for as longas the OV condition persists; if VOUTreturns to a safe level,normal operation automatically resumes. A shorted topMOSFET will result in a high current condition which willopen the system fuse. The switching regulator will regulateproperly with a leaky top MOSFET by altering the dutycycle to accommodate the leakage.

Phase-Locked Loop and Frequency Synchronization

The LTC3728 has a phase-locked loop comprised of aninternal voltage controlled oscillator and phase detector.This allows the top MOSFET turn-on to be locked to therising edge of an external source. The frequency rangeof the voltage controlled oscillator is 50% around thecenter frequency fO. A voltage applied to the PLLFLTRpin of 1.2V corresponds to a frequency of approximately400kHz. The nominal operating frequency range of theLTC3728 is 250kHz to 550kHz.

The phase detector used is an edge sensitive digital typewhich provides zero degrees phase shift between the ex-

ternal and internal oscillators. This type of phase detectorwill not lock up on input frequencies close to the harmonicsof the VCO center frequency. The PLL hold-in range, fH,

is equal to the capture range, fC:

fH= fC= 0.5 fO(250kHz-550kHz)

The output of the phase detector is a complementary pairof current sources charging or discharging the externalfilter network on the PLLFLTR pin.

If the external frequency (fPLLIN) is greater than the oscillatorfrequency fOSC, current is sourced continuously, pullingup the PLLFLTR pin. When the external frequency is lessthan fOSC, current is sunk continuously, pulling down the

PLLFLTR pin. If the external and internal frequencies arethe same but exhibit a phase difference, the current sourcesturn on for an amount of time corresponding to the phasedifference. Thus the voltage on the PLLFLTR pin is adjusteduntil the phase and frequency of the external and internaloscillators are identical. At this stable operating point thephase comparator output is open and the filter capacitorCLPholds the voltage. The LTC3728 PLLIN pin must bedriven from a low impedance source such as a logic gatelocated close to the pin. When using multiple LTC3728s(or LTC3729s, as shown in Figure 14) for a phase-locked

system, the PLLFLTR pin of the master oscillator should bebiased at a voltage that will guarantee the slave oscillator(s)ability to lock onto the masters frequency. A DC voltageof 0.7V to 1.7V applied to the master oscillators PLLFLTRpin is recommended in order to meet this requirement.The resultant operating frequency can range from 300kHzto 470kHz.

The loop filter components (CLP , RLP) smooth out thecurrent pulses from the phase detector and provide astable input to the voltage controlled oscillator. The filtercomponents CLP and RLP determine how fast the loop

acquires lock. Typically RLP =10k and CLP is 0.01Fto 0.1F.


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Minimum On-Time Considerations

Minimum on-time tON(MIN)is the smallest time duration

that the LTC3728 is capable of turning on the top MOSFET.It is determined by internal timing delays and the gatecharge required to turn on the top MOSFET. Low dutycycle applications may approach this minimum on-timelimit and care should be taken to ensure that

tON(MIN) 4.8V Burst Mode Operation DisabledConstant Frequency Mode EnabledNo Current Reversal AllowedNo Minimum Peak Current


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Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak

output voltage excursions under worst-case transientloading conditions. The open-loop DC gain of the controlloop is reduced depending upon the maximum load stepspecifications. Voltage positioning can easily be added tothe LTC3728 by loading the ITHpin with a resistive dividerhaving a Thevenin equivalent voltage source equal to themidpoint operating voltage range of the error amplifier, or1.2V (see Figure 8).

The resistive load reduces the DC loop gain while main-taining the linear control range of the error amplifier.The maximum output voltage deviation can theoretically

be reduced to half or alternatively the amount of outputcapacitance can be reduced for a particular application.A complete explanation is included in Design Solutions10. (See www.linear.com)

Efficiency Considerations

The percent efficiency of a switching regulator is equal tothe output power divided by the input power times 100%.It is often useful to analyze individual losses to determinewhat is limiting the efficiency and which change would

produce the most improvement. Percent efficiency canbe expressed as:

%Efficiency = 100% (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-age of input power.

ITH

RCRT1

INTVCC

CC

3728 F08

LTC3728

RT2

Figure 8. Active Voltage PositioningApplied to the LTC3728

Although all dissipative elements in the circuit producelosses, four main sources usually account for mostof the losses in LTC3728 circuits: 1) LTC3728 VIN cur-

rent (including loading on the 3.3V internal regulator),2) INTVCC regulator current, 3) I

2R losses, 4) TopsideMOSFET transition losses.

1. The VINcurrent has two components: the first is the DCsupply current given in the Electrical Characteristics table,which excludes MOSFET driver and control currents; thesecond is the current drawn from the 3.3V linear regulatoroutput. VINcurrent typically results in a small (


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each RDS(ON)= 30m, RL= 50m, RSENSE= 10mandRESR= 40m(sum of both input and output capacitancelosses), then the total resistance is 130m. This results

in losses ranging from 3% to 13% as the output currentincreases from 1A to 5A for a 5V output, or a 4% to 20%loss for a 3.3V output. Efficiency varies as the inversesquare of VOUT for the same external components andoutput power level. The combined effects of increasinglylower output voltages and higher currents required byhigh performance digital systems is not doubling butquadrupling the importance of loss terms in the switchingregulator system!

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high inputvoltages (typically 15V or greater). Transition losses canbe estimated from:

Transition Loss = (1.7) VIN2IO(MAX)CRSSf

Other hidden losses such as copper trace and internalbattery resistances can account for an additional 5% to10% efficiency degradation in portable systems. It is veryimportant to include these system level losses duringthe design phase. The internal battery and fuse resistancelosses can be minimized by making sure that CINhas ad-

equate charge storage and very low ESR at the switchingfrequency. A 25W supply will typically require a minimum of20F to 40F of capacitance having a maximum of 20mto50mof ESR. The LTC3728 2-phase architecture typicallyhalves this input capacitance requirement over competingsolutions. Other losses including Schottky conductionlosses during dead-time and inductor core losses generallyaccount for less than 2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulatorstake several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts byan amount equal to ILOAD(ESR), where ESR is the ef-fective series resistance of COUT. ILOADalso begins to

charge or discharge COUTgenerating the feedback errorsignal that forces the regulator to adapt to the currentchange and return VOUTto its steady-state value. Duringthis recovery time VOUTcan be monitored for excessiveovershoot or ringing, which would indicate a stabilityproblem. OPTI-LOOP compensation allows the transientresponse to be optimized over a wide range of outputcapacitance and ESR values. The availability of the ITHpinnot only allows optimization of control loop behavior butalso provides a DC coupled and AC filtered closed loopresponse test point. The DC step, rise time and settling

at this test point truly reflects the closed loop response.Assuming a predominantly second order system, phasemargin and/or damping factor can be estimated using thepercentage of overshoot seen at this pin. The bandwidthcan also be estimated by examining the rise time at thepin. The ITHexternal components shown in the Figure 1circuit will provide an adequate starting point for mostapplications.

The ITH series RC-CC filter sets the dominant pole-zeroloop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimizetransient response once the final PC layout is done andthe particular output capacitor type and value have beendetermined. The output capacitors need to be selectedbecause the various types and values determine the loopgain and phase. An output current pulse of 20% to 80%of full-load current having a rise time of 1s to 10s willproduce output voltage and ITHpin waveforms that willgive a sense of the overall loop stability without break-ing the feedback loop. Placing a power MOSFET directlyacross the output capacitor and driving the gate with an

appropriate signal generator is a practical way to producea realistic load step condition. The initial output voltage


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step resulting from the step change in output current maynot be within the bandwidth of the feedback loop, so thissignal cannot be used to determine phase margin. This

is why it is better to look at the ITHpin signal which is inthe feedback loop and is the filtered and compensatedcontrol loop response. The gain of the loop will be in-creased by increasing RCand the bandwidth of the loopwill be increased by decreasing CC. If RCis increased bythe same factor that CCis decreased, the zero frequencywill be kept the same, thereby keeping the phase shift thesame in the most critical frequency range of the feedbackloop. The output voltage settling behavior is related to thestability of the closed-loop system and will demonstratethe actual overall supply performance.

A second, more severe transient is caused by switchingin loads with large (>1F) supply bypass capacitors. Thedischarged bypass capacitors are effectively put in parallelwith COUT, causing a rapid drop in VOUT. No regulator canalter its delivery of current quickly enough to prevent thissudden step change in output voltage if the load switchresistance is low and it is driven quickly. If the ratio ofCLOADto COUT is greater than1:50, the switch rise timeshould be controlled so that the load rise time is limitedto approximately 25 CLOAD. Thus a 10F capacitor would

require a 250s rise time, limiting the charging currentto about 200mA.

Automotive Considerations: Plugging into theCigarette Lighter

As battery-powered devices go mobile, there is a naturalinterest in plugging into the cigarette lighter in order toconserve or even recharge battery packs during opera-tion. But before you connect, be advised: you are plug-

ging into the supply from hell. The main power line in anautomobile is the source of a number of nasty potentialtransients, including load-dump, reverse-battery, and

double-battery.

Load-dump is the result of a loose battery cable. When thecable breaks connection, the field collapse in the alterna-tor can cause a positive spike as high as 60V which takesseveral hundred milliseconds to decay. Reverse-battery isjust what it says, while double-battery is a consequence oftow-truck operators finding that a 24V jump start crankscold engines faster than 12V.

The network shown in Figure 9 is the most straight for-ward approach to protect a DC/DC converter from the

ravages of an automotive power line. The series diodeprevents current from flowing during reverse-battery,while the transient suppressor clamps the input voltageduring load-dump. Note that the transient suppressorshould not conduct during double-battery operation, butmust still clamp the input voltage below breakdown of theconverter. Although the LTC3728 has a maximum inputvoltage of 36V, most applications will be limited to 30Vby the MOSFET BVDSS.

Figure 9. Automotive Application Protection

VIN

3728 F09

LTC3728

TRANSIENT VOLTAGESUPPRESSORGENERAL INSTRUMENT1.5KA24A

50A IPKRATING

12V


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Design Example

As a design example for one channel, assume V IN =

12V(nominal), VIN= 22V(max), VOUT = 1.8V, IMAX= 5A,and f = 300kHz.

The inductance value is chosen first based on a 30% ripplecurrent assumption. The highest value of ripple currentoccurs at the maximum input voltage. Tie the PLLFLTRpin to a resistive divider using the INTVCCpin generating1V for 300kHz operation. The minimum inductance for30% ripple current is:

IL =VOUT(f)(L)

1VOUT

VIN

A 4.7H inductor will produce 23% ripple current and a3.3H will result in 33%. The peak inductor current willbe the maximum DC value plus one half the ripple cur-rent, or 5.84A, for the 3.3H value. Increasing the ripplecurrent will also help ensure that the minimum on-timeof 100ns is not violated. The minimum on-time occurs atmaximum VIN:

tON(MIN) =VOUT

VIN(MAX)f=

1.8V

22V(300kHz)= 273ns

The RSENSEresistor value can be calculated by using themaximum current sense voltage specification with someaccommodation for tolerances:

RSENSE

60mV

5.84A0.01

Since the output voltage is below 2.4V the output resis-tive divider will need to be sized to not only set the outputvoltage but also to absorb the SENSE pins specified inputcurrent.

R1(MAX) = 24k 0.8V

2.4V VOUT

= 24K 0.8V

2.4V 1.8V

= 32k

Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yieldsan output voltage of 1.816V.

The power dissipation on the top side MOSFET can beeasily estimated. Choosing a Siliconix Si4412DY resultsin; RDS(ON)= 0.042, CRSS= 100pF. At maximum inputvoltage with T(estimated) = 50C:

PMAIN =1.8V

22V 5( )

21+ (0.005)(50C 2 5C)[ ]

0.042( )+1.7 22V( )2

5A( ) 100pF( ) 300kHz(= 220mW

A short-circuit to ground will result in a folded back cur-

rent of:

ISC =25mV

0.01+

1

2

200ns(22V)

3.3H

= 3.2A

with a typical value of RDS(ON) and = (0.005/C)(20) =0.1. The resulting power dissipated in the bottom MOSFETis:

PSYNC =22V 1.8V

22V 3.2A( )

21.1( ) 0.042( )

= 434mW

which is less than under full-load conditions.

CINis chosen for an RMS current rating of at least 3A attemperature assuming only this channel is on. COUT ischosen with an ESR of 0.02for low output ripple. Theoutput ripple in continuous mode will be highest at themaximum input voltage. The output voltage ripple due toESR is approximately:

VORIPPLE= RESR (IL) = 0.02(1.67A) = 33mVPP


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PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of theLTC3728. These items are also illustrated graphically inthe layout diagram of Figure 10. The Figure 11 illustratesthe current waveforms present in the various branchesof the 2-phase synchronous regulators operating in thecontinuous mode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 locatedwithin 1cm of each other with a common drain connectionat CIN? Do not attempt to split the input decoupling forthe two channels as it can cause a large resonant loop.

2. Are the signal and power grounds kept separate? Thecombined LTC3728 signal ground pin and the ground returnof CINTVCCmust return to the combined COUT() terminals.

The path formed by the top N-channel MOSFET, Schottkydiode and the CINcapacitor should have short leads andPC trace lengths. The output capacitor () terminals shouldbe connected as close as possible to the () terminalsof the input capacitor by placing the capacitors next toeach other and away from the Schottky loop describedabove.

3. Do the LTC3728 VOSENSEpins resistive dividers connectto the (+) terminals of COUT? The resistive divider mustbe connected between the (+) terminal of COUTand signal

Figure 10. LTC3728 Recommended Printed Circuit Layout Diagram

CB2

CB1

RPU

PGOOD

VPULL-UP(


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ground. The R2 and R4 connections should not be alongthe high current input feeds from the input capacitor(s).

4. Are the SENSE and SENSE +leads routed together withminimum PC trace spacing? The filter capacitor betweenSENSE+and SENSEshould be as close as possible to

the IC. Ensure accurate current sensing with Kelvin con-nections at the SENSE resistor.

5. Is the INTVCCdecoupling capacitor connected close tothe IC, betweenthe INTVCCand the power ground pins?This capacitor carries the MOSFET drivers current peaks.An additional 1F ceramic capacitor placed immediatelynext to the INTVCCand PGND pins can help improve noiseperformance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes(TG1, TG2), and boost nodes (BOOST1, BOOST2) awayfrom sensitive small-signal nodes, especially from theopposites channels voltage and current sensing feedbackpins. All of these nodes have very large and fast moving

signals and therefore should be kept on the output sideof the LTC3728 and occupy minimum PC trace area.

7. Use a modified star ground technique: a low imped-ance, large copper area central grounding point on the sameside of the PC board as the input and output capacitors withtie-ins for the bottom of the INTVCCdecoupling capacitor,the bottom of the voltage feedback resistive divider andthe SGND pin of the IC.

Figure 11. Branch Current Waveforms

RL1D1

L1SW1 RSENSE1 VOUT1

COUT1+

VIN

CIN

RIN +

RL2D2BOLD LINES INDICATEHIGH, SWITCHINGCURRENT LINES.KEEP LINES TO AMINIMUM LENGTH.

L2SW2

3728 F11

RSENSE2 VOUT2

COUT2+


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PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in theinductor while testing the circuit. Monitor the outputswitching node (SW pin) to synchronize the oscilloscopeto the internal oscillator and probe the actual output voltageas well. Check for proper performance over the operatingvoltage and current range expected in the application. Thefrequency of operation should be maintained over the inputvoltage range down to dropout and until the output loaddrops below the low current operation thresholdtypically10% to 20% of the maximum designed current level inBurst Mode operation.

The duty cycle percentage should be maintained from cycleto cycle in a well-designed, low noise PCB implementation.Variation in the duty cycle at a subharmonic rate can sug-gest noise pickup at the current or voltage sensing inputsor inadequate loop compensation. Overcompensation ofthe loop can

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