linear integrated circuits lab manual for flip flops and logic gates

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Transcript of linear integrated circuits lab manual for flip flops and logic gates

DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERINGPONDICHERRY ENGINEERING COLLEGE, PUDUCHERRY

Title of the Experiment

Name of the Student

Register Number

Date of Experiment

Date of Submission

S.NO.Marks Split upMaximum MarksMarks Obtained

1Attendance5

2.Preparation of observation/Record10

3.Viva Questions10

4.Execution Of Experiment15

5.Result10

Total50

Lab in-charge

Experiment 2A : Study of FLIP-FLOPSAim: To study and verify the truth tables of RS, JK, D and T Flip-flopsApparatus required: Digital IC trainer kit, ICs 7400,7408,7402, 7411Theory: Inelectronics, aflip-floporlatchis acircuitthat has two stable states and can be used to store state information. A flip-flop is abistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element insequential logic. Flip-flops and latches are a fundamental building block ofdigital electronicssystems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. Such data storage can be used for storage ofstate, and such a circuit is described as sequential logic. When used in afinite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) orclocked(synchronous or edge-triggered); the simple ones are commonly called latches.The wordlatchis mainly used for storage elements, while clocked devices are described asflip-flops.A latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.Flip-flops can be divided into common types: theSR("set-reset"),D("data" or "delay"),T("toggle"), andJKtypes are the common ones. The behavior of a particular type can be described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output,Qnextin terms of the input signal(s) and/or the current output,

Procedure:1. The IC chip is fixed on the bread board in the trainer kit2. The + 5v is connected to the 14 th pin and 7th pin is grounded.3. Connections are made as per the logic diagram.4. The input switches are connected to the input terminals and LED s are connected to the output terminals.5. The truth table is verified by applying different inputsResult: Thus the JK, SA, D And T Flip-flops were constructed and the outputs are verified using truth table.

Viva Questions:1.What is a flip-flop2. What is the other name for flip-flop?3.What are the applications of Flip-Flops?4. What is meant by race around condition in flip-flops?5. How do you convert one type of Flip-flop into another?

EXPERIMENT: 2b) SHIFT REGISTERSAIM: i) To study the working of basic shift register and verify its truth table. ii) To construct ring counter and Johnson counter from the basic shift register and verify the truth table. iii) To study the shift register IC 7495 and its working as1) Serial in Serial out shift register2) Serial in Parallel out shift register3) Parallel in Parallel out shift register4) Parallel in Serial out shift registerCOMPONENTS REQUIRED: IC 7495, Patch Cords & IC Trainer Kit. Theory: Indigital circuits, ashift registeris a cascade offlip flops, sharing the sameclock, in which the output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the "bit array" stored in it,shifting inthe data present at its input andshifting outthe last bit in the array, at each transition of the clock input. More generally, ashift registermay be multidimensional, such that its "data in" and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel.Shift registers can have bothparallelandserialinputs and outputs. These are often configured asserial-in, parallel-out(SIPO) or asparallel-in, serial-out(PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are alsobi-directionalshift registers which allow shifting in both directions

The 7474 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Preset and clear are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output Shift Register CountersTwo of the most common types of shift register counters are introduced here: the Ring counter and the Johnson counter. They are basically shift registers with the serial outputs connected back to the serial inputs in order to produce particular sequences. These registers a re classified as counters because they exhibit a specified sequence of states.

Ring Counters A ring counter is basically a circulating shift register in which the output of the most significant stage is fed back to the input of the least significant stage. The following is a 4 -bit ring counter constructed from D flip -flops. The output of each stage is shifted into the next stage on the positive edge of a clock pulse. If the CLEAR signal is high, all the flip -flops except the first one FF 0 are reset to 0. FF0 is preset to 1 instead.

Since the count sequence has 4 distinct states, the counter can be considered as a mod-4 counter. Only 4 of the maximum 16 states are used, making ring counters very inefficient in terms of state usage. But the major advantage of a ring counter over a binary counter is that it is self-decoding. No extra decoding circuit is needed to determine what state the counter is in. Clock PulseQ3Q2Q1Q0

00001

10010

20100

31000

Johnson CounterJohnson counters are a variation of standard ring counters, with the inverted output of the last stage fed back to the input of the first stage. They are also known as twisted ring counters. An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered to be a mod-2n counter. The circuit below shows a 4-bit Johnson counter.

The state sequence for the counter is given in the table .Clock PulseQ3Q2Q1Q0

00000

10001

20011

30111

41111

51110

61100

71000

PROCEDURE: Place the ICs on the bread board of digital IC trainer kit. Make connections as shown in the circuit diagram. Apply input and Verify the Truth Table and observe the outputs.

Study of 7495 Shift register

The 7495 is a 4-Bit Shift Register with serial and parallel synchronous operating modes. The serial shift right and parallel load are activated by separate clock inputs which are selected by a mode control input. The data is transferred from the serial or parallel inputs to the Q outputs synchronous with the HIGH to LOW transition of the appropriate clock input. The LS95B is a 4-Bit Shift Register with serial and parallel synchronous operating modes. It has a Serial input and four Parallel (A-D) Data inputs and four Parallel Data outputs (QAQD). The serial or parallel mode of operation is controlled by a Mode Control input(S) and two Clock Inputs (CLK1) and (CLK2). The serial (right-shift) or parallel data transfers occur synchronous with the HIGH to LOW transition of the selected clock input. When the Mode Control input is HIGH, CLK2 is enabled. A HIGH to LOW transition on enabled CLK2 transfers parallel data from the P0P3 inputs to the QAQD outputs. When the Mode Control input (S) is LOW, CLK1 is enabled. A HIGH to LOW transition on enabled CLK1 transfers the data from Serial input (DS) to Q0 and shifts the data in QA to QB, QB to QC, and QC to QD respectively (right-shift). A left-shift is accomplished by externally connecting Q3 to C, Q2 to B, and Q1 to A, and operating the 95B in the parallel mode (S =HIGH). For normal operation, S should only change states whenboth Clock inputs are LOW. However, changing S from LOW to HIGH while CLK2 is HIGH, or changing S from HIGH to LOW while CLK1 is HIGH and CLK2is LOW will not cause any changes on the register outputs.

PROCEDURE: Place the ICs on the bread board of digital IC trainer kit. Make connections as shown in the circuit diagram. Apply input and Verify the Truth Table and observe the outputs.

Result: The working of basic shift register and its use as ring counter and Johnson counter were studied. The use of IC 7495 as different shift registers was also studiedVIVA Questions:What are shift registers? What are their applications?How will use a shift register to multiply and divide a number by 2?What is a Universal shift register?What are the different types of shift registers? Explain in detail.What is a bidirectional shift register?