Is It Cost-Effective to Achieve Very Is It Cost-Effective to Achieve Very High Fault Coverage for Testing High Fault Coverage for Testing Homogeneous SoCs with Core-Level Homogeneous SoCs with Core-Level Redundancy?Redundancy?

Lin Huang and Qiang XuLin Huang and Qiang XuCUHK Reliable Computing Laboratory (CURE)CUHK Reliable Computing Laboratory (CURE)The Chinese University of Hong KongThe Chinese University of Hong Kong{lhuang,qxu}@cse.cuhk.edu.hk{lhuang,qxu}@cse.cuhk.edu.hk

Observations on Manufacturing Observations on Manufacturing Test CostTest Cost

Traditional manufacturing Traditional manufacturing test requests sufficiently high test requests sufficiently high defect coveragedefect coverage

Manufacturing test cost - a Manufacturing test cost - a great share of production great share of production costcost

Most test patterns are for the Most test patterns are for the last several percentages of last several percentages of defect coveragedefect coverage

If we are able to relax this If we are able to relax this coverage requirement , coverage requirement , manufacturing cost can be manufacturing cost can be dramatically reduceddramatically reduced

Test Pattern Number

Pro

bab

ility

01

0.5

Proposed StrategyProposed Strategy

Manycore processor era provides us such an Manycore processor era provides us such an opportunityopportunity

Traditional Traditional yield-driven redundantyield-driven redundant cores aims to cores aims to improve the manufacturing yieldimprove the manufacturing yield

We propose to introduce a few We propose to introduce a few test cost-driven test cost-driven redundantredundant cores in addition to yield-driven spares, cores in addition to yield-driven spares, to relax the defect coverage requirement of each to relax the defect coverage requirement of each corecore

If test cost reduction exceeds the If test cost reduction exceeds the manufacturing cost increment, the total manufacturing cost increment, the total production cost can be reducedproduction cost can be reduced

Problem FormulationProblem Formulation

ConsiderConsider– A homogeneous manycore system with A homogeneous manycore system with m+n+sm+n+s cores cores– ss yield-driven redundancy and yield-driven redundancy and nn test cost-driven test cost-driven

sparesspares– Those that contain Those that contain m+nm+n pass-test cores are sold pass-test cores are sold– Eventually guarantee Eventually guarantee mm cores are defect-free for sold cores are defect-free for sold

chips to functionchips to function Given Given

– The maximum acceptable test escape rateThe maximum acceptable test escape rate– The ratio between the manufacturing cost per core to The ratio between the manufacturing cost per core to

its test costits test cost Determine Determine ss and and nn to achieve the minimum to achieve the minimum

production cost per sold chip under product quality production cost per sold chip under product quality constraintconstraint

Case Study: Case Study: A Homogeneous manycore system A Homogeneous manycore system functions with no less than 16 defect-functions with no less than 16 defect-free coresfree cores

rr: cost ratio of test over : cost ratio of test over manufacturingmanufacturing

nn: test cost-driven redundant core : test cost-driven redundant core numbernumber

ss: yield-driven redundant core number: yield-driven redundant core number

CCmanumanu: normalized manufacturing : normalized manufacturing costcost

CCtesttest: normalized test cost: normalized test cost

CCprodprod: normalized production cost: normalized production costrr nn ss CCmanumanu CCtesttest

Yield Yield (%)(%)

CCprodprod

HH

00 55 21.4621.46 10.2810.28 93.6693.66 33.8933.89

11 33 20.3420.34 6.686.68 89.8389.83 30.0730.07

22 22 20.3420.34 4.454.45 87.3887.38 28.3728.37

MM

00 44 20.3420.34 3.413.41 89.8189.81 26.4526.45

11 33 20.3420.34 2.232.23 89.8389.83 25.1225.12

22 22 20.3420.34 1.481.48 87.3887.38 24.9824.98

LL

00 44 20.3420.34 1.541.54 89.8189.81 24.3624.36

11 33 20.3420.34 1.001.00 89.8389.83 23.7623.76

22 22 20.3420.34 0.670.67 87.3887.38 24.0424.04

Thank you for your attentionThank you for your attention!!

Looking forward to seeing you at Poster Looking forward to seeing you at Poster

7.17.1