Light-Weight Encryption Processor Verilog Code

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    /*"------------------------------------" Light-Weight Encryption Processor "" S_Box.v "" By : "

    " Waheeb Al-Rafati "" Ahmad Shdifat "-----------------------------------*/module S_Box(

    output [7:0] S_Box_Out,input [7:0] Data

    );

    reg [7:0] S_Box_Output;assign S_Box_Out = S_Box_Output;

    always @(Data) begincase(Data)8'h00: S_Box_Output

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    8'h16: S_Box_Output

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    8'h40: S_Box_Output

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    8'h6a: S_Box_Output

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    8'h94: S_Box_Output

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    8'hbe: S_Box_Output

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    8'he8: S_Box_Output

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    /*"------------------------------------" Light-Weight Encryption Processor "" Sixteen_Bytes_S_Box.v "" By : "

    " Waheeb Al-Rafati "" Ahmad Shdifat "-----------------------------------*/module Sixteen_Bytes_S_Box(output [127:0] Output_Wires,input [127:0] Input_Wires);

    S_Box Byte01 (Output_Wires [007:000], Input_Wires [007:000]);S_Box Byte02 (Output_Wires [015:008], Input_Wires [015:008]);S_Box Byte03 (Output_Wires [023:016], Input_Wires [023:016]);S_Box Byte04 (Output_Wires [031:024], Input_Wires [031:024]);S_Box Byte05 (Output_Wires [039:032], Input_Wires [039:032]);

    S_Box Byte06 (Output_Wires [047:040], Input_Wires [047:040]);S_Box Byte07 (Output_Wires [055:048], Input_Wires [055:048]);S_Box Byte08 (Output_Wires [063:056], Input_Wires [063:056]);S_Box Byte09 (Output_Wires [071:064], Input_Wires [071:064]);S_Box Byte10 (Output_Wires [079:072], Input_Wires [079:072]);S_Box Byte11 (Output_Wires [087:080], Input_Wires [087:080]);S_Box Byte12 (Output_Wires [095:088], Input_Wires [095:088]);S_Box Byte13 (Output_Wires [103:096], Input_Wires [103:096]);S_Box Byte14 (Output_Wires [111:104], Input_Wires [111:104]);

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    S_Box Byte15 (Output_Wires [119:112], Input_Wires [119:112]);S_Box Byte16 (Output_Wires [127:120], Input_Wires [127:120]);

    endmodule//end Sixteen_Bytes_S_Box.v

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    /*"------------------------------------" Light-Weight Encryption Processor "" Shift_Rows.v "" By : "

    " Waheeb Al-Rafati "" Ahmad Shdifat "-----------------------------------*/module Shift_Rows(output [127:0] Output_Wires,input [127:0] Input_Wires,input CLK);

    reg [127:0] Output;assign Output_Wires = Output;always @ (posedge CLK) begin

    Output

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    /*"------------------------------------" Light-Weight Encryption Processor "" Add_Key.v "" By : "

    " Waheeb Al-Rafati "" Ahmad Shdifat "-----------------------------------*/module Mix_Columns(output [127:0] Output_Wires,input [127:0] Input_Wires,input CLK);

    reg [127:0] Output;assign Output_Wires = Output;

    always @ (posedge CLK ) beginOutput [007:000]

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    Output [039:032]

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    4:88], 1'b0} ^ Input_Wires [95:88] ^ 8'h1B : {Input_Wires [94:88], 1'b0} ^ Input_Wires [95:88]);

    Output [095:088]

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    /*"------------------------------------" Light-Weight Encryption Processor "" Add_Key.v "" By : "

    " Waheeb Al-Rafati "" Ahmad Shdifat "-----------------------------------*/module Add_Key(output [127:0] Output_Wires,input [127:0] Input_Wires,input [7:0] Key);

    assign Output_Wires [007:000] = Input_Wires [007:000] ^ Key;assign Output_Wires [015:008] = Input_Wires [015:008] ^ Key;assign Output_Wires [023:016] = Input_Wires [023:016] ^ Key;assign Output_Wires [031:024] = Input_Wires [031:024] ^ Key;assign Output_Wires [039:032] = Input_Wires [039:032] ^ Key;

    assign Output_Wires [047:040] = Input_Wires [047:040] ^ Key;assign Output_Wires [055:048] = Input_Wires [055:048] ^ Key;assign Output_Wires [063:056] = Input_Wires [063:056] ^ Key;assign Output_Wires [071:064] = Input_Wires [071:064] ^ Key;assign Output_Wires [079:072] = Input_Wires [079:072] ^ Key;assign Output_Wires [087:080] = Input_Wires [087:080] ^ Key;assign Output_Wires [095:088] = Input_Wires [095:088] ^ Key;assign Output_Wires [103:096] = Input_Wires [103:096] ^ Key;assign Output_Wires [111:104] = Input_Wires [111:104] ^ Key;

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    assign Output_Wires [119:112] = Input_Wires [119:112] ^ Key;assign Output_Wires [127:120] = Input_Wires [127:120] ^ Key;endmodule

    //end Add_Key.v

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    /*"------------------------------------" Light-Weight Encryption Processor "" Processor.v "" By : "

    " Waheeb Al-Rafati "" Ahmad Shdifat "-----------------------------------*/module Processor(output [127:0] Round_1_Output_Wires,output [127:0] Round_2_Output_Wires,input [127:0] Input_Wires,input [7:0] Key_Wires,

    input CLK,input Reset_Processor,input Start_Wire,output Encryption_Done_Wire);

    parameter IDLE_State =3'b000;

    parameter Shift_Rows_State =3'b001;

    parameter Mix_Columns_State =3'b010;

    parameter Buffer_Round_1_Result_State =3'b011;

    parameter Buffer_Round_2_Result_State =3'b100;

    parameter Prepare_Round_2_State =3'b101;

    parameter Encryption_Done_State =3'b110;

    reg [127:0] Input_Buffer;reg [127:0] Round_1_Output_Buffer;reg [127:0] Round_2_Output_Buffer;reg Encryption_Done;

    wire [127:0] S_Box_Input_Wires;

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    wire [127:0] S_Box_Output_Wires;wire [127:0] Shift_Rows_Output_Wires;wire [127:0] Mix_Columns_Output_Wires;wire [127:0] Add_Key_Output_Wires;

    assign S_Box_Input_Wires = Input_Buffer;assign Round_1_Output_Wires = Round_1_Output_Buffer;assign Round_2_Output_Wires = Round_2_Output_Buffer;

    reg [2:0] Next_State;reg Round;

    assign Encryption_Done_Wire = Encryption_Done;

    Sixteen_Bytes_S_Box Block00 (S_Box_Output_Wires, S_Box_Input_Wires);Shift_Rows Block01 (Shift_Rows_Output_Wires, S_Box_Output_Wires, CLK);Mix_Columns Block02 (Mix_Columns_Output_Wires, Shift_Rows_Output_Wires, CLK);Add_Key Block03 (Add_Key_Output_Wires,Mix_Columns_Output_Wires,Key_Wires);

    always @(posedge CLK or posedge Reset_Processor orposedge Start_Wire)

    if (Reset_Processor) beginInput_Buffer

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    Round_1_Output_Buffer

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    000000000;Round_1_Ou

    tput_Buffer

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    /*"------------------------------------" Light-Weight Encryption Processor "" Test_Bench.v "" By : "

    " Waheeb Al-Rafati "" Ahmad Shdifat "-----------------------------------*/module tb;

    reg CLK,Reset;reg [127:0] Input_Data;wire [127:0] Round_1_Output;wire [127:0] Round_2_Output;

    reg [7:0] Key;reg Start;

    Processor Block(Round_1_Output, Round_2_Output, Input_Data, Key, CLK, Reset, Start, Done);

    initial CLK = 0;initial forever #10 CLK = ~CLK;

    initial begin

    Reset = 1'b1;Start = 1'b0;Input_Data = 128'h1615141312111009080706

    0504030201;Key = 8'h55;#10 Reset = 1'b0;Start = 1'b1;#10 Start = 1'b0;

    endalways @(posedge Done)

    $stop;

    endmodule//end Test_Bench.v

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    /*"------------------------------------" Light-Weight Encryption Processor "" Run.tcl "" By : "

    " Waheeb Al-Rafati "" Ahmad Shdifat "-----------------------------------*/# TCL FILE FOR WAHTEST EXAMPLE

    cd "D:/Project/"

    # to delete lib

    ##vmap -del mydes#vdel -all -lib mydes

    # to create lib#vlib aesvmap aes aes

    # compile vlog files (must have a testbench)

    vlog -reportprogress 300 -work aes \"Sixteen_Bytes_S_Box.v"\"Test_Bench.v"\"Shift_Rows.v"\"Mix_Columns.v"\"Add_key.v"\"S_Box.v"\"Processor.v"\

    # load the testbenchvsim -voptargs=+acc \

    aes.tb# load the signalsadd wave sim:/tb/*add wave sim:/tb/Block/Next_Stateadd wave sim:/tb/Block/Round

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    # run the simulation

    run -all

    //end run.tcl


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