library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity RS232_test is Port ( clk_50MHz : in STD_LOGIC; rst : in STD_LOGIC; RS232_rx : in STD_LOGIC; RS232_tx : out STD_LOGIC; LED : out STD_LOGIC_VECTOR (7 downto 0));end RS232_test;architecture Behavioral of RS232_test iscomponent uart_transceiver is port( sys_rst: in std_logic; sys_clk: in std_logic; uart_rx : in std_logic; uart_tx : out std_logic; divisor : in std_logic_vector(15 downto 0); rx_data : out std_logic_vector(7 downto 0); rx_done: out std_logic; rx_bsy: out std_logic; tx_data : in std_logic_vector(7 downto 0); tx_wr : in std_logic; tx_done: out std_logic);end component;signal RXByte,TXByte, debug: std_logic_vector(7 downto 0);signal tx_req: std_logic;signal tx_end: std_logic;signal rx_ready,rx_busy: std_logic;type stateType is (receiving, transmitting);signal state: stateType;begin RS232: uart_transceiver port map ( sys_rst => rst, sys_clk => clk_50MHZ, uart_rx => RS232_rx, uart_tx => RS232_tx, divisor => x"001B", rx_data => RXByte, rx_done => rx_ready, rx_bsy => rx_busy, tx_data => TXByte, tx_wr => tx_req, tx_done => tx_end); Mirror: process (clk_50MHz, rst)begin if rst = '1' then TXByte