Traditional and Advanced Flow Characterization Techniques ...
Library Characterization Flow
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Transcript of Library Characterization Flow
Library Characterization
Satish Kumar Grandhi(https://sites.google.com/site/satishkumargrandhi2/)
Its Impact on Semiconductor Industry & the flow
Let’s start off on a Funny NoteWhy Choose Library Characterization as a career ??
Very little manual effort, need only little extra intelligence Effort – 30% , Enjoyment – 70% ; No need to work over weekends Only one issue : Convergence (Kills u big time) Double Edged Sword; Little Chance of firing . But, Very few players in this
business, no great chances of jumping around . Most Important ; It keeps your options wide open
Physical Design, STA
Circuit Design
EDA Tool Developme
nt
Acknowledgements Heart Felt Thanks to
Masamb Electronics, Anupam Kumar Sinha in specific Naveen Kumar Kotha (LSI Bangalore), Rachit I. Kushalappa (TI, Bangalore)
& Naresh ANNE (AMD USA) Wiki, EDABoard & LTSPICE yahoo group NANGATE for providing open source 45nm STD cell library package All prof’s with US universities (You guys don’t hide your work in the
internal repositories, hats off to you) Collegues @ NXP, Cypress & ST MicroElectronics
Check out my weblink on Library Characterization for latest updated version of these slides & for more info
Speaker guarantees no originality in this work ; It is a mix of material accumulated from various sources
We are as dwarfs sitting on the shoulders of giants -- Sir Issac Newton
Contents
Necessity & the Impact Fundamental Terminology Glancing Through .LIB Characterization Methodology Case Studies : Inverter & D-Flop Advanced Topics References
Two Great Laws
Moore’s Law On April 19, 1965 Moore predicted the most important law ever proposed in Semiconductors.
Amdahl's law states that the performance improvement to be gained from using some faster mode of execution is limited by the fraction of the time the faster mode can be used
Missing 3rd law, the NLDM law
How are these related ??
How to Implement them ?
Two Generic Flows
Reference : Allen Holberg, Gatech and Laker, Upenn Class Room Lectures
INTEL Processor’s Growth
* All the predictions are based on wiki…could be approximate
Characterization Terminology
Input Slew & Output Load Slew rate : Represents the maximum rate of change of signal Output Load : Total amount of capacitance at the output node
Timing - Combinational
Transition Delay Time a system needs to switch between two different stable states, when responding to a stable input signal
Propagation Delays Time it takes for the output signal to switch after the input signal has been applied.
Timing – Sequential 1 Setup & Hold
Minimum time the data signal has to be present at the input pin of a memory cell before/after the write signal arrives.
General Methodology employed : Binary Chop
Timing - Sequential 2 Recovery / Removal
Minimum time delay that has to maintained between an asynchronous clear/set signal and before/after the clock of the cell is triggered.
Method Used : Binary Chop
Timing – Sequential 3 Minimum Pulse Width
Minimum width of control signal in order for the cell to detect it.
If the clock signal active period is smaller than this minimum time, you cannot be sure that the cell will have stored the input’s value properly.
Timing Unateness
Positive Unate
Negative Unate
Non Unate
Power – Short circuit If a path exists from power supply to ground, it results in continuous
flow of current and results in static power dissipation CMOS Technology has neglible static power consumption (biggest
advantage and reason as to why CMOS is so very popular).
Power - Dynamic Power dissipated during the charging and discharging of the output
Load capacitance.
Pdyn = CL * Vdd2 * f
Power - Leakage The power consumed by the sub threshold currents and by reverse
biased diodes in a CMOS transistor Major Sources :
Sub threshold condition Gate Leakage current
* Check out Reference6
Wire Load Models No info on interconnect parasitic
before Physical Design
Attempts to predict the capacitance and resistance of nets in the absence of placement and routing information
Excellent Paper : Steve Golson, "Resistance is Futile! Building Better Wireload Models" (Link)
/* Wire load table */ wire_load("ABC") { capacitance : 1.774000e-04; resistance : 3.571429e-03; area : 7.559700e-02; slope : 5.000000; fanout_length( 1, 1.3207 ); fanout_length( 2, 2.9813 ); fanout_length( 3, 5.1135 ); fanout_length( 4, 7.6639 ); fanout_length( 5, 10.0334 ); fanout_length( 6, 12.2296 ); fanout_length( 8, 19.3185 ); }
Library Characterization Flow
Methodology
* Prototype Copied from Liberty NCX manual
Sensitization Set of logic conditions leading to transition; This logic condition setup
process is called sensitization.
In other words, it generates the stimulus at the cell input pins necessary to produce a simulation measurement of the desired characteristic, such as delay or slew.
No simulations performed, analytically derives the functionality of the cell from Boolean expressions, truth tables, state tables, and flip-flop latch groups defined in the input library or template files.
Load Sharing Facility (LSF)
Goal : Give many users processes "fair share" of resources (CPU, memory , ….)
Commands : bjobs, bqueues, bhist, bkill, bswitch, bpause, bresume
How Simulator Works ??
Create Spice Deck for each
case
Input Setup Sanity Check
Arc List for each Cell
Develop Sensitization
Vector’s
Launch Them on LSF
Fetch the Results
Generate .LIB (final masala )
Capacitance Characterization
Buffer comparison method calculates by comparing the output slope of three identical reference buffers.
Charge calculation method monitors the total current (charge) flowing through each input pin and integrates it over a period of time
Power Characterization
Calculates the current consumed and convert into power Find paths from input pins to outputs, look for every valid pin
combination of the cell and simulate it. Plus, some input combinations don't change any output. But, results
in power consumption For example:
Clocks, sets, resets etc. that do not change the output because it already had the proper state
Input changes without a clock change Also, Leakage power
Case Study: Inverter & D-Flop
.Measure (Spice Command)
Prints the results of specific user defined analyses
With this command you can measure rise and fall times, length of a pulse, delays, voltages, etc.
ELDO - .extract Spectre – {export}???
CS 1 : Inverter ARCS :
IN OUT
Measurements : Rise, Fall
Sensitization Vectors IN : 01, 10 OUT : 10, 01
IRMS .MEASURE TRAN irms RMS I(VDC) from 20n to 60n
irms: RMS(i(vdc))=1.12327e-005 FROM 2e-008 TO 6e-008
IAVG .MEASURE TRAN iavg AVG I(VDC) from 20n to 60n
iavg: AVG(i(vdc))=-3.27957e-007 FROM 2e-008 TO 6e-008
IMAX .MEASURE TRAN imax MAX I(VDC) from 20n to 60n
imax: MAX(i(vdc))=0.000114917 FROM 2e-008 TO 6e-008
IMIN .MEASURE TRAN imin MIN I(VDC) from 20n to 60n
imin: MIN(i(vdc))=-0.000220052 FROM 2e-008 TO 6e-008
ILEAK_IN1 Vin IN 0 PWL 0 0 10n 1.8 20n 1.8 ileak_in1: AVG(i(vdc))=8.19303e-011 FROM 1e-008 TO 2e-008.MEASURE TRAN ileak_in1 AVG
I(VDC) from 10n to 20nILEAK_IN0 vin IN 0 PWL 0 1.8 10n 0 20n 0 ileak_in0: AVG(i(vdc))=-4.95193e-010 FROM
1e-008 TO 2e-008 .MEASURE TRAN ileak_in0 AVG I(VDC) from 10n to 20n
Attribute
Spice Command Output Characterized Value (Log File Extract)
IN_CAP .MEASURE TRAN intg_i_in INTEG I(Vin) FROM 0n to 10n
intg_i_in: INTEG(i(vin))=-1.60204e-014 FROM 0 TO 1e-008
.MEASURE TRAN incap_in param= ABS(intg_i_in/0.9)
incap_in: abs(intg_i_in/0.9)=1.78004e-014
Cap Measurements
Power Measurements
Attribute Spice Command Output Characterized Value (Log File Extract)
OUT_RISE_10 .MEAS t1r WHEN V(out)=0.1*V(vdd) TD=0 RISE=2
t1r: v(out)=0.1*v(vdd) AT 3.01462e-008
OUT_RISE_90 .MEAS t2r WHEN V(out)=0.9*V(vdd) TD=0 RISE=2
t2r: v(out)=0.9*v(vdd) AT 3.01826e-008
OUT_FALL_90 .MEAS t1f WHEN V(out)=0.9*V(vdd) TD=0 FALL=2
t1f: v(out)=0.9*v(vdd) AT 2.0044e-008
OUT_FALL_10 .MEAS t2f WHEN V(out)=0.1*V(vdd) TD=0 FALL=2
t2f: v(out)=0.1*v(vdd) AT 2.00772e-008
IN_RISE_50 .MEAS tdr1 WHEN V(in)=0.5*V(vdd) TD=0 RISE=2
tdr1: v(in)=0.5*v(vdd) AT 2.005e-008
OUT_RISE_50 .MEAS tdr2 WHEN V(out)=0.5*V(vdd) RISE=2
tdr2: v(out)=0.5*v(vdd) AT 3.01651e-008
IN_FALL_50 .MEAS tdf1 WHEN V(in)=0.5*V(vdd) TD=0 FALL=2
tdf1: v(in)=0.5*v(vdd) AT 3.015e-008
OUT_FALL_50 .MEAS tdf2 WHEN V(out)=0.5*V(vdd) TD=0 FALL=2
tdf2: v(out)=0.5*v(vdd) AT 2.00633e-008
RISE TRANSITION
.MEAS trise PARAM t2r-t1r trise: t2r-t1r=3.63951e-011
FALL TRANSITION
.MEAS tfall PARAM t2f-t1f tfall: t2f-t1f=3.32203e-011
CELL RISE .MEASURE tdelay_rise PARAM tdr2-tdr1 tdelay_rise: tdr2-tdr1=1.01151e-008
CELL FALL .MEASURE tdelay_fall PARAM tdf2-tdf1 tdelay_fall: tdf2-tdf1=-1.00867e-008
Timing Calculations
Technology Impact Simulated a 3 Input NAND gate (all
inputs set to '1') using cadence GPDK180 & NANGATE's 45nm models
With shrinking gate length, the leakage current increases
Tech/Measurement GPDK180 Nangate's 45
ISubthreshold -3.92E-12 -5.94266e-009
Igatea 6.04236e-019 2.10647e-009
Igateb 2.29347e-019 5.37746e-10
Igatec 4.98678e-019 5.37746e-10
Ref : ITRS Roadmap 2005
CS 2 : D Flip Flop Consider a Asynchronous flop with set &
Reset pins. Possible arcs to be characterized :
Clk -> Q (delay) D -> Clk (setup & Hold) Set/ Reset -> Clk (Recovery & Removal)
Power & cap characterization
(Each instance is a 3 input nand gate)
Various Arcs in Scan Flop
( Snapshot from Reference 3 )
Setup Analysis** For Setup Time AnalysisVIN2 D 0 pwl 0 0 4.99995n 0 5.99995n 1.8 11n 1.8 12n 0 24n 0 24.9995n 0 25.9995n 1.8.MEASURE TRAN setup_time **** Constrained pin is falling+ trig V(D) val = 0.9 rise= 1**** Related pin is rising+ targ V(CLK) val = 0.9 rise = 2
Setup time=1.955e-008 FROM 5.49995e-009 TO 2.505e-008
From STA Point of View
--Very primitive, will improve in the days to come
CAP on a net Total o/p node cap =
Sum of { all input caps of driven cells + wire Capacitance + O/p Node Capacitance }
Delay Calculation
UINV0 (NET0, I2)UAND1 (O1, I1, NET0)UNOR2(O2, O1, NET0)
Advanced Topics
State Dependent Delays Timing arcs depend on the state of pins other than Input & Output Multiple timing models are used to describe ‘a’ arc Consider a 2 I/P XOR Gate
timing () {related_pin : "A";when : "B";sdf_cond : "(B == 1'b1)";timing_sense : negative_unate;
cell_fall(Timing_data_X1) {values ("0.012959,0.015005,……..……………………………………………
timing () {related_pin : "A";when : "!B";sdf_cond : "(B == 1'b0)";timing_sense : positive_unate;
cell_fall(Timing_data_X1) {values ("0.036818,0.038956, ……..……………………………………………
Negative Delays A large input slope and a cell that reacts either very
quickly
Load Cap Characterization When output slew transition = Max_Slew(max_tout), the output
loading = Max_load
Tri State Delay Measurement
Cannot be measured using conventional voltage levels
Measured by looking at the current through the output pin.
Test Equipment consists of
Current detector on the output of the tristate cell
Pull-up and pull-down resistors that can be switched on/off independently
Measuring Normal-tri state delays
Switch on both pull-up and pull-down resistors; produce a short current flows at the output pin.
When the cell enters tristate mode the output pin will be isolated from the rest of the cell, the path from supply to output cut, and current through the output pin will stop.
Current monitoring device detects when the value goes below a certain threshold (pre-defined) which is the required delay.
Tri State to High state delays
Activate only the pull-down resistor
Switch off the pull-down resistor
Push the Circuit into Tri State Mode
Enable the cell so that output rise ‘s
References1) Sung Mo Kang and Yusuf Leblebici, "CMOS Digital Integrated Circuits-
Analysis and Design", Tata McGraw Hill, Third Edition, New Delhi, 2003
2) J. Bhasker & Rakesh Chadha, “Static Timing Analysis for Nanometer Designs: A Practical Approach”
3) Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, “Digital Integrated Circuits: A Design Perspective”
4) RACHITH I. KUSHALAPPA, "AutoLibGen : An open source tool for automation of Standard Cell Library characterization for VDSM designs", M.E Thesis, NITK Surathkal, 2008
5) NARESH ANNE, "Design and Characterization of a standard cell library for the freePDK 45 process ", M.S Thesis, Oklahoma State University, 2010 (link)
References….6. HSpice Simulation and Analysis Users Guide, Version Y-2006.09,
Sep 20067. Synopsys NCX User guide, Version B-2008.12, December 20088. An Excellent Lecture on Leakage power & possible reduction
Techniques by R. Saleh, Uni of British Columbia (Link)9. Nangate 45nm Open Cell Library (link)10. Excellent Tutorial on HSPICE (Link)11. LTSPICE Yahoo Group (Link)12. Last, but not the least, extensive knowledge I gained by interacting
with Library char teams @ NXP, Cypress & ST microelectronics which can’t be put in words