LG G8000 Service Manual
description
Transcript of LG G8000 Service Manual
2. PERFORMANCE
- 7 -
2. PERFORMANCE
2.1 H/W Features
Item Feature Comment
Li-Ion, 1050 mAh
Standard Battery Size: 39.5 * 67 * 5.4t (mm)
Weight: 31g
Extended Battery No Extended Battery
AVG TCVR Current Min: ?mA(Pwr Level 19), Max: ?mA(Pwr Level 5)
Standby Current < ? mA
Talk time Min : 2hr40min (2hr30min)
Max : 5hr20min(5hr)
Stand by time Up to 200 hours
Charging time 3 hours
RX Sensitivity GSM, EGSM: -108 dBm, DCS: -107 dBm
TX output power GSM, EGSM: 33(32) dBm (Level 5)
DCS: 30(29) dBm (Level 0)
GPRS compatibility Class 10
SIM card type Plug-In SIM 3V/5V
Display Main : 65535 Color-TFD(176X220)
Sub : Mono(84X40)
Status Indicator : 7-color LED
Key pad :
Status Indicator & Keypad • 0 ~ 9, #, *, Navigation Key, Up/Down Side Key
• Side Key, Confirm Key, Record Key
• Send Key, END/PWR Key,Function Key
ANT Fixed Type
EAR Phone Jack Ear-Mike connector
PC Synchronization Yes
Speech coding EFR/FR
Data and Fax Yes
Vibrator Yes
Speaker Yes
Voice Recording Yes
C-Mic Yes
Receiver Yes
Travel Adapter Yes
Options Hands-free kit, CLA, USB Cable, DTC
2.2 Technical Specification
2. PERFORMANCE
- 8 -
Item Description Specification
GSM
TX: 890 + n 0.2 MHzRX: 935 + n 0.2 MHz (n = 1 ~ 124)
EGSM1 Frequency Band TX: 890 + (n - 1024) 0.2 MHz
RX: 935 + (n - 1024) 0.2 MHz (n = 975 ~ 1024)
DCSTX: 1710 + (n-512) 0.2 MHzRx: 1805 + (n-512) 0.2 MHz (n = 512 ~ 885)
2 Phase ErrorRMS < 5 degreesPeak < 20 degrees
3 Frequency Error < 0.1 ppm
GSM, EGSM
Level Power Toler. Level Power Toler.
5 33 dBm 2dB 13 17 dBm 3dB
6 31 dBm 3dB 14 15 dBm 3dB
7 29 dBm 3dB 15 13 dBm 3dB
8 27 dBm 3dB 16 11 dBm 5dB
9 25 dBm 3dB 17 9 dBm 5dB
10 23 dBm 3dB 18 7 dBm 5dB
11 21 dBm 3dB 19 5 dBm 5dB
4 Power Level 12 19 dBm 3dB
DCS
Level Power Toler. Level Power Toler.
0 30 dBm 2dB 8 14 dBm 3dB
1 28 dBm 3dB 9 12 dBm 4dB
2 26 dBm 3dB 10 10 dBm 4dB
3 24 dBm 3dB 11 8 dBm 4dB
4 22 dBm 3dB 12 6 dBm 4dB
5 20 dBm 3dB 13 4 dBm 4dB
6 18 dBm 3dB 14 2 dBm 5dB
7 16 dBm 3dB 15 0 dBm 5dB
2. PERFORMANCE
- 9 -
Item Description Specification
GSM, EGSM
Offset from Carrier (kHz). Max. dBc
100 +0.5
200 -30
250 -33
400 -60
600 ~ 1,200 -60
1,200 ~ 1,800 -60
1,800 ~ 3,000 -63
3,000 ~ 6,000 -65
5 Output RF Spectrum 6,000 -71(due to modulation)
DCS
Offset from Carrier (kHz). Max. dBc
100 +0.5
200 -30
250 -33
400 -60
600 ~ 1,200 -60
1,200 ~ 1,800 -60
1,800 ~ 3,000 -65
3,000 ~ 6,000 -65
6,000 -73
GSM, EGSM
Offset from Carrier (kHz) Max. (dBm)
400 -19
600 -21
1,200 -21
6 Output RF Spectrum 1,800 -24(due to switching transient)
GSM
Offset from Carrier (kHz) Max. (dBm)
400 -22
600 -24
1,200 -24
1,800 -27
7 Spurious EmissionsConduction, Emission StatusConduction, Emission Status
2. PERFORMANCE
- 10 -
Item Description Specification
GSM, EGSM
8 Bit Error RatioBER (Class II) < 2.439% @-102 dBm
DCS
BER (Class II) < 2.439% @-100 dBm
9 RX Level Report Accuracy 3 dB
10 SLR 8 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 0 -12
11 Sending Response 1,000 0 -6
2,000 4 -6
3,000 4 -6
3,400 4 -9
4,000 0 -
12 RLR 2 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 2 -7
500 * -5
13 Receiving Response 1,000 0 -5
3,000 2 -5
3,400 2 -10
4,000 2
* Mean that Adopt a straight line in between 300 Hzand 1,000 Hz to be Max. level in the range.
14 STMR 13 5 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)
-35 17.5
-30 22.5
16 Sending Distortion-20 30.7
-10 33.3
0 33.7
7 31.7
10 25.5
17 Side tone Distortion Three stage distortion < 10%
18 <Change> System frequency ≤ 2.5 ppm(13 MHz) tolerance
2. PERFORMANCE
- 11 -
Item Description Specification
19 <Change>32.768KHz tolerance ≤ 30 ppm
At least 80 dB under below conditions:20 Ringer Volume 1. Ringer set as ringer.
2. Test distance set as 50 cm
21 Charge VoltageFast Charge : < 650 mA
Slow Charge: < 60 mA
Antenna Bar Number Power
5 -85 dBm ~
4 -90 dBm ~ -86 dBm
22 Antenna Display 3 -95 dBm ~ -91 dBm
2 -100 dBm ~ -96 dBm
1 -105 dBm ~ -101 dBm
0 ~ -105 dBm
Battery Bar Number Voltage
0 3.62 V~
23 Battery Indicator1 3.62 ~ 3.71 V
2 3.71 ~ 3.79 V
3 3.79 ~ 3.93 V
4 3.93 V~
24 Low Voltage Warning3.5 0.03 V (Call)
3.62 0.03 V (Standby)
25 Forced shut down Voltage 3.28 0.03 V1 Li-Ion Battery
26 Battery TypeStandard Voltage = 3.7 V
Battery full charge voltage = 4.2 V
Capacity: 1050 mAh
Switching-mode charger
27 Travel Charger Input: 100 ~ 240 V, 50/60 Hz
Output: 5.2 V, 1.5 A
3. TECHNICAL BRIEF
3.1 ReceiverThe receiver part consists of a dual band (GSM & DCS) antenna switch, two RF SAW filters, anexternal dual RF VCO and a transceiver IC (TRF6150). All active circuits for a complete receiverchain with the exception of RF VCO are contained in the transceiver IC (TRF6150).
The TRF6150 chip set has direct conversion structure, so the received RF signal is directlyconverted to base band I and Q signal by the transceiver IC (IF frequency is 0 Hz), which containstwo LNAs and three direct conversion demodulators for E-GSM, DCS and PCS. The demodulated Iand Q signals pass two base band AGC amplifiers and a channel filter, which are on both I and Qsignal paths. The RF front-end circuit is shown Figure 3-1.
Figure 3-1. RF front-end circuit
3. TECHNICAL BRIEF
- 12 -
3. TECHNICAL BRIEF
- 13 -
3.1.1 RF front end
RF front end consists of an antenna, a dual band antenna switch, two RF SAWs and two LNAs for E-GSM, DCS band, which are contained in the transceiver IC (TRF6150).
The RF received signals (GSM 925MHz ~ 960MHz, DCS 1805MHz ~ 1880MHz) are input via theantenna or coaxial connector. An antenna matching circuit is between the antenna and theconnector.
The antenna switch (FL103) is used to control the Rx and TX paths, which has two control signalsVC1 and VC2 that are connected to 4-Input NOR Gate (U102) to switch either TX or RX path on.When the RX path is turned on, the received RF signal, which has passed through the dual bandantenna switch, is filtered by an appropriate RF SAW filter for better stop band rejection. The filteredRF signal is amplified by an LNA integrated in the transceiver IC(TRF6150) and pass to a directconversion demodulator. This process is the same both GSM and DCS.
The logic and current is given below. Table 3-1.
Table 3-1. The logic and current
3.1.2 Demodulator and Baseband Processing
IF stage is not necessary in this system because the receiver is based on direct conversionarchitecture. So the RX LO frequency is the same as input radio frequency. The amplified signal atLNA stage passes to a direct conversion demodulator and is mixed down to generate I&Q BBsignals. The BB I&Q signals pass via two integrated baseband amplifiers with digitally programmablegain and two fully integrated baseband channel filters to the baseband A/D converters which iscontained in baseband chipset. Figure 3-2 shows RX path block diagram.
3.1.3 DC offset compensation
The transceiver IC(TRF6150) is based on direct-conversion architecture. This implies that a parasiticDC offset may appear at the output of the IQ demodulator. To reduce the static offset due tocomponents mismatch and LO self-mixing, the IC includes a hardware DC offset compensationcircuit on both I and Q base band paths. The transceiver IC uses a divider by 2 for LO generation inEGSM and a multiplier by 2 in DCS to minimize the DC offset generated by self mixing and the LOradiation. In addition, a quadrature demodulator gain mismatch calibration system is used to reducethe signal distortion.
VC1 VC2
GSM TX 2.7 V 0 V
DCS TX 0 V 2.7 V
GSM/DCS RX 0 V 0 V
Figure 3-2. RX path block diagram
Table 3-2. Gain and Noise Figure of RX path
Table 3-3. Total Gain and Noise Figure of RX path
3. TECHNICAL BRIEF
- 14 -
Ant. switch RF SAW Filter I,Q demodulator (LNA+Mixer)
Gain(dB)GSM -0.6 -2.5 26
DCS -0.7 -2.4 23
NF(dB)GSM 3
DCS 3.5
Total Gain Total Noise FigureGSM, EGSM 22.9 dB 7.2 dBDCS 19.9 dB 7.4 dB
3. TECHNICAL BRIEF
- 15 -
3.2 SynthesizerThe TRF6150 includes two synthesizer parts. Two synthesizers consist of an IF synthesizer, which isan integer-N synthesizer, and a RF synthesizer, which is a fractional-N synthesizer. The TRF6150 isa transceiver IC suitable for GSM and DCS GPRS up to class 12 applications. So, synthesizers usea number of techniques to improve lock time, making them well suited to GPRS.
The main fractional-N synthesizer (RF synthesizer), which includes a RF VCO with external tankcircuits, is necessary for both transmitting and receiving operation. The RF VCO works only whenthe transmitting operation is on. The main fractional-N synthesizer has frequency band from 1294MHz to 1356 MHz. Output frequency of the RF VCO is set by the factional number, prescaler andcounter. A buffer amplifier follows the RF VCO. The purpose of the buffer is to give reverse isolationand prevent any frequency pulling of the VCO when the transceiver is powered UP and DOWN.
A dual band external VCO, which uses the PLL block of the main fractional-N synthesizer, isnecessary for transmitting and receiving operation. The dual band means that it can support GSM,DCS frequency operation. For transmitting operation, the OPLL block of the TRF6150 directlymodulates the dual band external VCO with I and Q signals. For receiving operation, the externalVCO output frequency band is from 902 to 940MHz for DCS Rx and from 1850 to 1920MHz for GSMRx. The frequency of the signal from the external VCO is divided by 2 for GSM Rx and is doubled by2 for DCS Rx operation before entering into the direct conversion mixer.
The auxiliary integer-N synthesizer (IF synthesizer), which includes an IF VCO with external tankcircuits, is necessary for transmitting operation only. The IF VCO has a frequency band from 832MHz to 858 MHz. Output frequency of IF VCO is settled by prescaler and counter. The fractionalcounter in the RF synthesizer just differs from the IF synthesizer. The IF VCO is also followed by abuffer amplifier, which is to give reverse isolation and prevent any frequency pulling of the VCOwhen the transceiver is powered UP and DOWN.
A fixed reference frequency of 1.3MHz for Rx (or 2.6MHz for Tx) is generated by a reference dividerfrom the external applied 13 MHz crystal oscillator.
The phase frequency detector with charge pump provides programmable output current, which coulddrive the capability and the pulse width.
The counter and mode settings of the synthesizer in the TRF6150 are programmed via 3-wireinterface.
Table 3-4. 3-wire BUS of Synthesizer in the TRF6150
Pin Number DescriptionTSPCLK 11 Serial clock input to the synthesizerTSPDATA 12 Serial data input to the synthesizerTSPEN 13 Input latches the serial data transferred to the synthesizer
Figure 3-3. Synthesizer internal Block Diagram
3. TECHNICAL BRIEF
- 16 -
PFD
6 bitsA
3bitsB
8/9P/P+1
Delay
16/17P/P+1
7 bitsA
4 bitsB
4 bitsFN
: 5/ 10
PFD: 2
TANK
TANK
832 ~ 858MHz
IF SYNTHESIZER2.6MHz
RX : OPENTX : CLOSED
RF SYNTHESIZER
2.6/1.3MHz
1294 ~ 1356MHz
Dual band VCO : 902 ~ 940MHz DCS Rx
1850 ~ 1920MHz GSM Rx
13MHzor
26MHz
The IF and RF output frequencies of the TRF6150 are set by programming the internal divider registers.The frequency setting equations of the IF and RF frequencies are as follows.
is the output frequency of the IF VCO (the auxiliary integer-N synthesizer) and fRFout is the outputfrequency of the RF VCO (the main fractional-N synthesizer). The frequency band of the RF VCO is from1294MHz to 1356 MHz, and the frequency band of the IF VCO is from 832MHz to 858Mhz, whichfrequency bands are only for the transmitting operation.
Figure 3-4. Synthesizer circuit
3. TECHNICAL BRIEF
- 17 -
U105TRF 6150
CLK 11
DATA 12
EN 13
AUXCP 14
CRF 16
MAINSPUP14
MAINCP 5
VC
C7
22
AU
XV
CO
P 2
3
AU
XV
CO
N 2
4
35 MAINVCO
59 T
XR
XC
P
58 R
2
57 M
AIN
SP
UP
2
AFC R131
C142
X101
VC-TCXO-208C
C146
R128R123R124
TSPENTSPDATA
TSPCLK
C175
R140
C174
R141
C178
L109
C179
R142
C176 C177
R143 L110
D103
R139
R137
C184
C183
C185R145
C167 L105
C164 L108
C156
R109
R11
0
R11
1
C118
C117
R107
C116VT 13
FL101
ENFVF382S18
D102HVC369B
AUX.PLL
Ser
ial
Inte
rfac
e
MAINPLL
PFD
60
SMV 1233-074
3.3 Transmitter The Transmitter part contains TRF6150 active parts, PAM, coupler, dual schottky diode and dualband VCO. The TRF6150 active parts consist of the vector modulator and offset phase-locked loopblock (OPLL) including down-converter, phase detector, and APC IC for power control. The VCOfeed the output frequencies into PAM and TRF6150 for Tx local frequency. The peak output powerof the PAM is controlled by means of a closed feedback loop. A dual band directional coupler isused to control the RF output from the PAM. The PAM outputs from the directional coupler pass tothe antenna connector via an integrated dual band antenna switch module.
Figure 3-5.Transmitter Block Diagram
3. TECHNICAL BRIEF
- 18 -
CLARATRF6150
LF PFD
PF08122B
IN
IP
QN
QP
HBRX
LBTX
HBTX
TXRXcp
OMIXrf
HBswitch
LBswitch
TXRXswitch
Vreg3
CRFLF :5/10 :2
7bitsA
4bitsB
6bitsA
3bitsB
8/9P/P+1
LF
TANK
TANK
16/17P/P+1
4bitsFN
Vapc FILT
DETD
DETR
APC DAC
APCEN
AUXcp
AUXvcop
AUXvcon
MAINcp
Delay
PA CONTROLLER
Serial Control Logic & Resisters
VR4in
CLK
EN
DATA
90˚
/2
MAINvco
R3
MAINspup2
R 2
MAINspup1
LDC15D190A0007A
BAT15-05W
VC1
VC2
SHS-M090B
ENFVF382S18
EGSMDCS
L.B./L.P. L.B./H.P. H.B./L.P. H.B./H.P.
L.BON/OFF
H.BON/OFF
RX/TXSWITCH
0 0
0 0
00
1 1
1 1
1 1 ON=0/OFF=1RX=1/TX=0
VC1 VC2
TX
RX
TX
RXGSM
DCS
2.6V
2.6V
0V
0V
0V 0V
0V0V
RESETZ
2.6/1.3MHZ
1294~1356 MHz
832~858 MHz
416-429MHz
IFout = (P*A + B)*13MHz
RFout_tx = (P*A + B + FN/13)*2.6MHz
RFout_rx = (P*A + B + FN/13)*1.3MHzRFout_rx = (P*A + B + FN/13)*1.3MHzRFout_rx = (P*A + B + FN/13)*1.3MHzRFout_rx = (P*A + B + FN/13)*1.3MHz
TX
RX
3. TECHNICAL BRIEF
- 19 -
3.3.1 Tx Modulator
The Tx I & Q signals from BB analog chipset are fed to the TRF6150 Tx modulator, where they aremodulated onto either a Tx of 880 MHz(for GSM-Tx) or 1710 MHz(for DCS-Tx) by the quadraturemixer inside the U604. The Tx LO signal(1294 – 1356 MHz, 426.4 MHz) is fed from the internal mainand aux. VCO.
The modulator provides more than 40dBc of carrier and unwanted side-band rejection and producesa GMSK modulated signal. The BB software is able to cancel out differential DC offsets in the I/Q BBsignals caused by imperfections in the D/A converters. The Tx-Modulator implements a quadraturemodulator. The frequency input signal is split into two precise orthogonal carriers, which aremultiplied by the BB modulation signal IP/IM and QP/QM. It is used as reference signal for the OPLL.
Figure 3-6. Tx IF Modulator and OPLL Circuit
51
59 58
62
OMIXRF
VREG3
MAINSPUP2R2
57
TXRXCPFL101
ENFVF382S18
R113R114
1710 - 1785MHz(TX, DCS)880 - 915MHz(TX, GSM)
TXVCO
LBSW
10
VT
GSM_OUT
11
13
1VCC
C123
C110
R107
C117C116
C118
R109
6DCS_OUT
DCS_SWPWR_SW
8 9
GSM_SW
HBSW
TXRXSW
GND2,5,7 12,14
R110 R111
TRF6150U105
11
TSPCLKTSPDATATSPEN
18 QN
19 QP
22 RESETZ
QP
IP
IM
QM
RESETCL
R505
R506 C502
R50120 IN
21 IPR502
R129
C501
C143
DATA
1312R124 R123 R128
CLK EN
:2
PFD
AUX PLLN-integer
MAIN PLLN-fractional
TXRXSW
LBSW
HBSW
GSM TX DCS TX
0 0
0 1
1 0
L153
3.3.2 OPLL
The down converter contained inside of the TRF6150 (U105) mixes the Tx RF frequency with the RFVCO signal from the ENFVF382S18 (FL101) to generate a ‘feedback’ signal at 414.4MHz forGSM,EGSM and DCS operation. The ‘feedback’ signal passes to one port of the phase detector.The GMSK ‘reference’ signal from the Tx IF modulator passes via a second limiter to the other inputport of the phase detector. The phase detector generates an error current proportional to the phasedifference between the ‘feedback’ signal from the down-converter and the ‘reference’ signal from theTx IF modulator.
The error current is filtered by a second order low-pass filter to generate an output voltage, whichdepends on the GMSK modulation and the desired channel frequency. This voltage controls thetransmit VCO such that the VCO output signal, centered on the correct RF channel is frequencymodulated with the original GMSK data. The center frequency of the transmit VCO is offset from theRF VCO frequency by 414.4MHz for GSM, EGSM and DCS oper ation.
3.3.3 Power Amplifier
The PF08122B (U101) is Dual band power amplifier for EGSM (880 to 915 MHz) and DCS (1710 to1785 MHz). The efficiency of module is the 55% at 35 dBm for E-GSM and the 50% at 32.5 dBm forDCS for 3.5 V nominal battery use.
This module should be operated under the GSM burst pulse. To avoid permanent degradation, CWoperation should not be applied. To avoid the oscillation at no input power, before the input is cut off,the control voltage Vapc should be control to less than 0.5 V. We have to improve thermalresistance, the through holes should be layouted as many as possible on PCB under the module.And to get good stability, all the GND terminals and the metal cap should be soldered to groundplane of PCB.
Figure 3-7. Power Amplifier and its Control Part Circuits
3. TECHNICAL BRIEF
- 20 -
LDC15D190A0007A
N101
Directional Coupler
INOUT1
GND
B1
B2
2,6
4
53
8
U101 PF08122B
C186
L150
C191
R135
R133
R134
PAM+
H : GSM, L : DCS
C153
VBAT
C154 C130 C125
9,10,11,12 7
1
5
6
3
4 GSM
DCS
GND
Vapc
GSM
DCS
Vdd2
Vdd1
Bias CircuitVctl
2
8
C119
C150
C133
C198
U105TRF6150
48
VAPC
C131
R116R112
46 DETD
45 DETRR138
R117
D101 BAT15-05w
C134
R119
R120
R103
47
FILT
8
APC
9
APCEN
R126
C188
R125
PA_LEVEL
PA_ON
FL103SHS-M090B
7
C132
C107
C135C136
C199
C120
L191
3. TECHNICAL BRIEF
- 21 -
3.3.4 PA Circuit and Control
The power amplifier control circuit ensures that the RF signal is regulated to the required limits ofoperation. RF power is controlled by driving the power control pins of power amplifier and sensing.The resultant RF output power via a directional coupler (N101). The RF sense voltage is peakdetected using an schottky diode of BAT15-05W (D101). This detected voltage is compared to theDAC voltage in the TRF6150 to control the output power.
An internal input signal (PA_LEVEL) from CALYPSO, which is digital BB chipset (U503), is appliedto the APC IC in TRF6150 during the PA_ON mode and a directional coupler near the antenna feedsa portion of the RF output signal back to the APC IC and peak detector converts this signal to a lowfrequency feedback signal that balances the amplifier when this signal is equal to the RAMP inputsignal level.
3.4 13 MHz ClockThe 13 MHz clock (VC-TCXO-208C) consists of a TCXO (Temperature Compensated CrystalOscillator), which oscillates at a frequency of 13 MHz.The 13MHz clock is used within the Synthesizer block of the TRF6150, BB Analog chip-set(NAUCICA_CS), and Digital (CALYPSO). The inverter IC, TC7SZ04AFE buffers the output toNAUCICA_CS and CALYPSO.
Figure 3-8. VCTCXO Circuit
VC-T CXO-208CX101R121
R913
R130C147
GND 2
VCONT 1
3 OUT
4 VCC
R131
C142
C140
R913
Pin#3@ U104
13MHz
CRF@TRF6150
AFC
C139
GND 3
A 2
NC 1
4 Y
5 VCC
TC7SZ04AFEU103
3.5 Power Supplies and Control SignalsThree Regulators are integrated in the TRF6150 to provide DC power to the RF blocks (RegulatorR1, R2, R3). The Regulator R1 is used to provide DC power to the receiver, the transmitter and thePA control loop of the TRF6150. The Regulator R2 is used to provide DC power to the DC offsetcompensation circuit, the auxiliary synthesizer, the main synthesizer and VCOs. The Regulator R3is used for the external Rx/Tx VCO, switchplexer control buffer. An external regulator is used toprovide DC power to the VCTCXO (X101).
Table 3-5. Regulator Specification
Figure 3-9. External Regulator Circuit
3. TECHNICAL BRIEF
- 22 -
Regulator Voltage Powers Enable Signal
Regulator R1, R2, R3 Receiver, Transmitter,(These are all integrated 2.8 V 0.1 V Synthesizers, VCOs
in the TRF6150)
LP3985IBPX_2.8V (U104) 2.85 V 0.1V VCTCXO TCXO_EN
R132
U104LP3985IBPX_2.8V
TCXO_EN
VBAT_RF2.85V_OUT
1 VEN
2 GND
3 VOUT
BYPASS 5
VIN 4
C148 C149
RADIO_TEMP
R181
R182
R183PT101
3. TECHNICAL BRIEF
- 23 -
3.6 Digital Baseband (DBB) Processor
Figure 3-10. Top level block diagram of the Calypso G2 (HERCROM400G2)
3.6.1 General Description
CALYPSO is a chip implementing the digital base-band processes of a GSM/GPRS mobile phone.This chip combines a DSP sub-chip (LEAD2 CPU) with its program and data memories, a Micro-Controller core with emulation facilities (ARM7TDMIE), internal 8Kb of Boot ROM memory, 4M bitSRAM memory, a clock squarer cell, several compiled single-port or 2-ports RAM and CMOS gates.
The chip will fully support the Full-Rate, Enhanced Full-Rate and Half-Rate speech coding.
CALYPSO implements all features for the structural test of the logic (full-SCAN, BIST, PMT, JTAG
boundary-SCAN).
1MbitSRAM
1MbitSRAM
1MbitSRAM
1MbitSRAM
Write
buf
Memoryprotect
Unit
Boot ROMExternalARM7
MemoriesMEMIF
Debug Unit
ARM7
cDSPs28c128
BRIDGE
MCU top-cell
RREA bus
DSP subchip
8K API
GSM time
Ck32khz
IT Alarm
32KHz CRYSTAL
RTC
ULPD
TSP
TPU
SIM
PWL
UARTirda
UARTmodrn
3.6.2 Block Description
CALYPSO architecture is based on two processor cores ARM7 and DSP using the generic RHEAbus standard as interface with their associated application peripherals.
CALYPSO is composed from the following blocks:
• ARM7TDMI CPU core
• DSP subchip
• ARM peripherals:
General purpose peripherals• ARM Memory Interface for external RAM, Flash or ROM• 4 Mbit Static RAM with write-buffer
Application peripherals• ARM General purposes I/O with keyboard interface and two PWM modulation signals• UART 16C750 interface (UART_IRDA) with
- IRDA control capabilities (SIR)- Software flow control (UART mode).
• UART 16C750 interface (UART_MODEM) with
- hardware flow protocol (DCD, CTS/RTS)- autobaud function
• SIM Interface.
• TPU (Time Processing Unit) : Processing for GSM time base
• TSP (Time Serial Port) : GSM data interface with RF and ABB
Memory Interface : External/Internal Memory Interface
nCS0 : FLASH1, 16bit access, 3 wait state
nCS1 : Pseeudo - SRAM, 16bit access, 3 wait state
nCS2 : Not Used
nCS3 : Not Used
nCS6 : Int SRAM, 32bit access, 0 wait state
* Calypso internal 39MHz machine 3 wait state is necessary for the 80ns access because of 25nsmachine cycle. (25*4 = 100ns)
3. TECHNICAL BRIEF
- 24 -
3. TECHNICAL BRIEF
- 25 -
3.6.3 External Devices connected to memory interface
Table 3-6. External Device Spec connected to memory interface
3.6.4 RF Interface (TPU, TSP block)
Calypso uses this interface to control Nausica_CS (ABB Processor) and Clara (RF Processor) withGSM Time Base
Table 3-7. RF Interface Specification
TSP (Time Serial Port)
Resource Interconnection Description
TSPDO ABB & RF main Chip Control Data
TSPEN0 ABB ABB Control Data Enable Signal
TSPEN1 RF main Chip RF Control Data Enable Signal
TPU (Time Processing Unit) Parallel Port
TSPACT00 RESET_RF RF main Chip Reset Signal
TSPACT05 PA_ON Power Amp ON signal
Interface SPECWrite Read
Device Name Maker Access AccessTime Time
FLASH 1 TH50VPF5683DASB Toshiba 80ns 80nsSRAM TH50VPF5683DASB Toshiba 70ns 70ns
3.6.5 SIM interface
SIM interface scheme is shown in (Figure 3-11).
SIM_IO, SIM_CLK, SIM_RST ports are used to communicate DBB with ABB and the Charge Pumpin ABB enables 3V/5V SIM operation.
Table 3-8. SIM Interface
Figure 3-11. SIM Interface
3.6.6 UART Interface
The model has two UART Drivers as follow :
- UART1 : Interface and Communication with Helen UART2
- UART2 : Interface and Communication With Helen UART1
Table 3-9. UART Interface Specification
3. TECHNICAL BRIEF
- 26 -
SIM (Interface between DBB and ABB)SIM_RST SIM card async/sync reset
SIM_PWCTRL SIM card power activation
SIM_IO SIM card bidirectional data line
SIM_CLK SIM card reference clock
20K 20K
SIM_PWCTRL
SIM_IO
SIM_CLK
SIM_RST
SIO3 SIO5 IOVDD
CLK
RSTSRST3 SRST5
SCLK3 SCLK5
SVDD
Naucica
CARD
UART MODEM (UART1)Resource Name NoteTX_MODEM TXD Transmit Data
RX_MODEM RXD Receive Data
CTS_MODEM CTS Clear To Send
RTS_MODEM RTS Request To Send
GPIO 11 DTR Data Terminal Ready
GPIO 12 DCD Data Carrier Detect
UART IRDA (UART2)TX_IRDA TX Transmit Data (UART2)
RX_IRDA RX Receive Data (UART2)
3. TECHNICAL BRIEF
- 27 -
3.6.7 GPIO map
In total 16 allowable resources, This model is using 12 resources except 4 resources dedicated toSIM and Memory. GPIO(General Purpose Input/Output) Map, describing application, I/O state, andenable level, is shown in below table.
Table 3-10. GPIO Map Table
3.7 Analog Baseband (ABB) Processor
3.7.1 General Description
Nausica CS is Analog Baseband (ABB) Chip supports GSM900, DCS1800, GPRS Class 10 with
Digital Basband Chip (Calypso G2) Nausica_CS processes GSM modulation/demodulation and power management operations.
Block Description- Audio Signal Processing & Interface- Baseband in-phase (I), quadrature (Q) Signal Processing- RF interface with DBB (time serial port)- Supply voltage regulation- Battery charging control- Switch ON/OFF- 3V/5V SIM card Interface- 4 internal & 5 external ADC channels
I/O # Application I/O Resource Inactive State Active StateI/O (0) _HEL_SYS_RST O GPIO HIGH (Helen Reset released) LOW (Helen is reset)I/O (1) CAL_TX_MBOX O GPIO HIGH LOW
HIGH (UART Modem LOW (UART modemI/O (2) CAL_UART_SEL O GPIO connected to Keypad isconnected to Helen
connector) UART2)I/O (3) MOTOR_EN O GPIO LOW HIGHI/O (4) HEL_TX_MBOX I GPIO LOW HIGHI/O (5) SIM_PWCTL O SIMI/O (6) BAT_SENSE I GPIO LOW HIGHI/O (7) DTC_SENSE I GPIO LOW HIGH
I/O (8) HS_HF_SW O GPIO LOW (Audio out path HIGH (Audio out path isis connected to EarJack) connected to HandsFree)
I/O (9) NOT USED
I/O (10) MM_AUDIO_C_H O GPIO HIGH (Nausica VDR is LOW (Nausica VDR isconnected to Helen) connected to Calypso)
I/O (11) CAL_UART_DTR I GPIO LOW HIGHI/O (12) CAL_UART_DCD O GPIO LOW HIGH
I/O (13) EAR_SPEAKER_SW O GPIO HIGH (Audio out is LOW (Audio out path isconnected to Speaker) connected to Earjack)
I/O (14) NBHE O MEMORY
I/O (15) NBLE O MEMORY
3.7.2 Audio Signal Processing & Interface
Audio signal processing is divided Uplink path and downlink path.
The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signaland then transmit it to DBB Chip. This transmitted signal is reformed to fit in GSM Frame format anddelivered to RF Chip. MICBIAS is 2.5V level.
The downlink path amplifies the signal from DBB chip and outputs it to Receiver (or Speaker).
Figure 3-12. Audio Interface Block Diagram
3. TECHNICAL BRIEF
- 28 -
AUXI : 4.6dB28.2dB
MICAMP25.6dB
ADC2.5dB
UL Filter3.5dB
PGA :Gain 0dB+12dB -12dBStep 1dB
Sidetone :+1dB -23dBMute
DL Filter0dB
PGA :Gain 0dB+6dB -6dBStep 1dB
DigitalModulator
0dB
DAC &SmoothingFilter 0dB
EARAMP1dB
AUXAMP-5dB
BUZZERPulse WidthModulation1MHz
VolumeControl :0dB -24dB+Mute
SLR = 8 +/- 3dB
RLR = 2 +/- 3dB
365mVrms
Sensitivity-49.3dBv/Pa
1.385Vrms
Sensitivity106.7dBspl/Vrms
32.5mVrms
692mVrms
0V to AVDD
VREF 1.75V
+3dBm0 Full Scale
+3dBm0 Full Scale
620mVrms
1.237Vrms
Audio
Figure 3-13. Audio Section Scheme
3. TECHNICAL BRIEF
- 29 -
3.8.3 Audio
EARP
EARN
C523
C522C521
Nausica_CS
From Calypso(Handsfree Speaker) (Handsfree Speaker)
Nausica
AUXOPAUXON
From CalypsoHF_MIC(FromHandsfree Mic)Speaker_Output_To_MIDI
To OMAP1510
R84
9
1K
27pC812
C81
50.
1u
C81727p
10uC854
R90
6
R90
5
12
OB
G-1
5S44
-C2
MIC
801
C80
90.
1u
27pC814
SP
171KR84
8
R815
1K
C85727p
SP
18
MICBIAS
MICN
MICP
C80710p
R803 0
0
R846
R82
2
1K
HEL_IO_MEM_2.8V
470
R871
COM1C3
A3COM2
B2
G1
G2
B3G
ND
B1
C2IN1
A2IN2
C1NC1
A1NC2
C4NO1
NO2A4
B4
V+
MAX4684EBCU803
R82
3
1K
SP
15
C9040.1u
0R883
R884 0
10uFC889
10pC808
C80247p
220n
C82
1
SP
14
NO2 A4
V+
B4
COM1C3
A3COM2
B2
G1
G2
B3
GN
DB
1
C2IN1
A2IN2
C1NC1A1NC2
C4NO1
U805MAX4684EBC
1KR80
4
SP
13
15R
828
R812
0
R82
4
10K
220n
C81
0
0R881
2 54
13
6
Q803 UMD2N
R81
3
47pC813
123456
J8016D
5
GN
D2
SM
F05
C
D80
1 D1
1 3D
24
D3
D4
5
AVDD
AVDD Q810DTC144EE
BC
E
47pC819
R882 0
10uC806
0R814
10pC804
R81
6
EAR_SPEAKER_SW
KEY_ROW1
HF_SPK_PHS_HF_SW
AUXI
STEREOJACK_DET
HF_SPK_N
Audio Voice Mode-Audio Voice Mode is 5 Mode.
Table 3-11. Audio Voice Mode Table
Voice Mode controlled by Two analog switch (dual)Headset, SpeakerPhone and HandsFree Mode is controlled by Two analog switch (dual).
Two Geneal Purpose IO Signal (HS_HF_SW, EAR_SPEAKER_SW) from calypso control
two analog switchs (U803, U805).
Table 3-12. Analog Switch Contol ModeUplink
The microphone (Zebra Type) is touched to the main PCB. The uplink signal is passed to MICIPand MICIN pins of Nausica_CS. The MICBIAS voltage is supplied from Nausica_CS (dedicatedmode only) through R815 and R849.
When the headset is inserted, STEREOJACKDET outputs High state and HS_HF_SW,EAR_SPEAKER_SW outputs Low states.
Figure. 3-14 Uplink Path
ModeNausica_CS in/out Port IN OUT
Receiver Mode MICP, MICN EARP, EARNHeadset Mode AUXI AUXOP, AUXONSpeaker Phone Mode MICP, MICN AUXOP, AUXONHandsFree Mode AUXI AUXOP, AUXON
3. TECHNICAL BRIEF
- 30 -
HS_HF_SW EAR_SPEAKER_SW Mode
Low Low Headset
Low High SpeakerPhone
High Don’t care HandsFree
Biasgenerator
Sigma deltaMod. 2.48dB
Microphoneamplifiter25.6dB
Auxiharyamplifier4.6dB28.2dB
MICBIAS
MICIP
MICIN
AUXI
SINEFilter
UPLinkIIRbandpassfilter 3.52dB
PGA+12.....-12dB
To voiceserial
interface
Fs3=8KHzFs2=40KHzFs1=1KHz
Side Tone to Voice Downlink
3. TECHNICAL BRIEF
- 31 -
DownlinkThe downlink signal is passed from EARP and EARN pins of Nausica_CS. When the headset isinserted and OMAP1510 detects ‘STEREOJACK_DET’ signal (High Active), OMAP1510 informsCalypso of inserting jack
And then, Calypso makes Nausica_CS switches the downlink path from ‘EARP’ and ‘EARN’ to‘AUXOP’ and ‘AUXON’.
Figure. 3-15 Downlink Path
Speaker PhoneIn speakerphone mode, Calypso makes ‘SPKER_EN’ to High state and AUXOP signal is passed to
speaker (located in upper Folder Case) through two analog switches (U803,U805) AND Melody IC(U807).
MM (Multimedia)_AudioIn MM_Audio mode, There are two path ( Multimedia speaker and Multimedia Headset) for
multimedia audio.
OMAP1510 makes ‘MMAUDIO_CAL_HEL’ to High state and multimedia audio signal fromOMAP1510 is passed to speaker (located in upper Folder Case) or headset through MUX switches(U555), Nausica_CS(U501) and external voice path (Speakerphone, Headset).
Table 3-13. Analog Switch Contol Mode
MMAUDIO_CAL_HEL State Mode
High Multimedia Audio Mode
Low Voice Mode
Auxiliaryamplifier -5dB
DAC andLPF
Earphone ampifier 1dB
EUZZERPWM
AUXOP
AUXON
EARP
EARN
BUZZOP
4bit outputsigma_deltamodulator
REceive PGA(-6dB -+6dBstep 1dB
DownLinkBandpassFilter IIR
Side Tonefrom uplink
VolumeControl
From voiceserial
interface
Fs3=8KHzFs2=40KHzFs1=1KHz
3.7.3 Baseband Codec (BBC)
Baseband codec is composed of baseband uplink path (BUL) and baseband downlink path (BDL).BUL makes GMSK Gaussian Minimum Shift Keying) modulated signal which has In-phase (I) com-ponent and quadrature (Q) component with burst data from DBB. This modulated signal istransmitted through RF section via air.
BDL process is opposite procedure of BUL. Namely, it performs GMSK demodulation with inputanalog I&Q signal from RF section, and then transmit it to DSP of DBB chip with 270KHz data ratethrough BSP.
Figure 3-16. Baseband Codec Block Diagram
3. TECHNICAL BRIEF
- 32 -
CosTable
SineTable
Anti-aliasingFilter
Anti-aliasingFilter
Sigma-DeltaModulator
Sigma-DeltaModulator
SINCFilter
SINCFilter
FIRFilter
FIRFilterOffset
Reg.
OffsetReg.
M
----
----
++++
++++
Fs=6.5MHzFs=1.08MHzFs=270.8kHz
TimingControl
OffsetReg.
Low-passFilter
Low-passFilter
10-bitDAC
10-bitDAC
6-bitDAC
6-bitDAC
BurstBuffer1
BurstBuffer2
GMSKModulator
OffsetReg.
16X270kHz
270kHz
from TSP
from BSP
to BSP Downlink Block
Uplink BlockBaseband Codec
BULQM
BULQP
BULIM
BULIP
BDLQM
BDLQP
BDLIM
BDLIP
M
3. TECHNICAL BRIEF
- 33 -
3.7.4 Voltage Regulation (VREG)
There are 5 LDO (Low Drop Output) regulators in ABB chip.
The output of these 5 LDOs are as following table. (Figure 3-17) shows the power supply relatedblocks of DBB/ABB and their interfaces.
Figure 3-17. Power Supply Scheme
Table 3-14. LDO Output Table
U505
D510
0.1uF
R550
C524 X501
Output Voltage UsageVR1 1.8V Digital Core of DBBVR1B 2.0V Digital Core of ABBVR2 2.8V Memory Interface of DBBVR2B 2.8V Digital I/Os of DBB & ABBVR3 2.8V Analog Block
3.7.5 ADC Channels
ABB ADC block is composed of 4 internal ADC (Analog to Digital Converter) channels and 5 externalADC channel. This block operates charging process and other related process by reading batteryvoltage and other analog values.
Table 3-15. ADC Channel Spec
3.7.6 Charging
Charging block in ABB processes charging operation by using VBAT, ICHG value through ADCchannel. Battery Block Indication and SPEC is as follow.
Figure 3-18. Battery Block Indication
Charging method : CC-CV
Charger detect voltage : 4.0V
Charging time : 3h
Icon stop current : 100mA
Charging current : 540mA
CV voltage : 4.2V
Full charge indication current (icon stop current) : 100mA
Low battery alarma. Idle : 3.62Vb. Dedicated : 3.50V
Low battery alarm interval :Idle : 3 minDedicated:1 min
3. TECHNICAL BRIEF
- 34 -
ADC 9 channels
Resource Name
VCHG VCHG
VBAT VBAT Charging Management
ICHG ICHG
VBACKUP VBACKUP Backup Battery
ADCIN1 RADIO_TEMP Temperature Sensing
ADCIN2 BATT_Thermister Battery Temperature Detect
ADCIN3 Not Used
ADCIN4/TSCXP Not Used
ADCIN5/TSCYP Not Used
4.2 ~ 3.93V 3.93 ~ 3.79V 3.79 ~ 3.71V 3.71 ~ 3.62V 3.62 ~ 3.5V
Switch-off voltage : 3.28V
Charging temperature adc range~ -20 °C : not charging operation.-20 °C ~ 47 °C : charging.47 °C~ : not charging operation.
3.7.7 Switch ON/OFF
Power State : Defined 4 cases as follow
- Power-ON : mobile is powered by main battery or backup battery.- Power-OFF : mobile isn’t any battery.- Switch-ON : mobile powered and waken up from switch-off state.- Switch-OFF : mobile is powered to maintain only the permanent function (ULPD).
To enter into Switch-ON state, one of following 4 condition is satisfied.
- PWR-ON :pushed after a debouncing time of 30ms.- ON_REMOTE : After debouncing, when a falling edgeis detected on RPWON pin.- IT_WAKE_UP : When a rising edge is detected on RTC_ALARM pin.- CHARGER_IC :When a charger voltage is above VBAT+0.4V on VCHG.
3.7.8 Memories
• 64Mbit/32Mbit Flash/SRAM MCP64Mbit Flash + 32Mbit SRAM
• 16 bit parallel data bus
• ADD01 ~ ADD22
3. TECHNICAL BRIEF
- 35 -
3. TECHNICAL BRIEF
- 36 -
3.8 Multimedia Processor (HELEN)
Figure 3-19. Top Level Block diagram of Helen OMAP1510
3.8.1 General Description
The OMAP1510 processor features 1st generation TI OMAP architecture with the OMAP3.1 gigacellas its core building block. The OMAP1510 processor provides application developers with an open,easy-to-use programming environment by supporting popular os and programming languages. TheOMAP1510 performs all personal communication system tasks such as PDA, PIM tasks.
The OMAP1510 device includes the MPU subsystem, the DSP subsystem, a memory interfacetraffic controller, general-purpose peripherals, dedicated multimedia application peripherals, andmultiple interfaces. The MPU is the master of the platform, and it has access to the entire 16M bytesof memory space and to the 128K bytes of I/O space of the DSP subsystem. Additionally, the MPUand DSP share access to the internal SRAM and external memory interface.
3. TECHNICAL BRIEF
- 37 -
3.8.2 Block Description
The OMAP1510 device has the following features:
_Ability to support reduced instruction set computer (RISC) and DSP operating systems
TI925T MPU subsystem with:Instruction cache (16K bytes) and data cache (8K bytes)Memory management unit (MMU)A 17-word write buffer (WB)
DSP subsystem (C55x••DSP core and subsystems) with:Internal 32K-word dual-access RAM (DARAM), 48K-word single access RAM (SARAM), 16K-word ROMSoftware-configurable instruction cache (12K words, 128-bit line size, 2-way set-associative +RAM set) Hardware accelerators for video processing, pixel interpolation, and motion estimation Six-channel DMA controller for high-speed data movement without DSP intervention
DSP MMU for address translation and access permission checksSystem DMA controller with:
Six ports and nine independently programmable generic channelsAn additional dedicated DMA channel tied to the liquid crystal display (LCD) controllerAbility to transfer 8-,16-, or 32-bit data between the external memory, the MPU, and peripheralswith byte alignment and packing capability Ability to perform simultaneous transfers (single or multiple burst), if no resources conflict Low-power design (no clocking when idle)
Two external memory interfaces, allowing glueless hookup to:A 16-bit bus interface to external memory interface slow (EMIFS), such asflash/SRAM/ROM/page-mode ROM/SB flash/DPRAM), with 128M bytes of memory space A 16-bit bus interface to external memory interface fast (EMIFF), such as memory SDRAM, with64M bytes of memory space
JTAG port for test, debug, and emulation Clock management:
One digital phase-locked loop (DPLL) and three clock management units for MPU, DSP, andtraffic controller clock generation and management System power management for idle mode and power-down functions
Peripherals available for the OS, general-purpose housekeeping, and application-specific functions:
For the MPU:Three 32-bit timersA 16-bit watchdog timerAn interrupt handlerAn LCD controllerConfiguration registersMcBSP2 (multichannel buffered serial port)Inter-integrated circuit (I2C) interfaceMicroWire interfaceKeyboard interfaceUniversal serial bus (USB) function and host interfaceCamera interfaceFive MPUIO general-purpose input/output signals in default multiplexing mode; five more
3. TECHNICAL BRIEF
- 38 -
availablethrough alternative pin multiplexing modes32-kHz timerPulse-width tone (PWT) modulePulse-width light (PWL) moduleReal-time clock (RTC) moduleMultimedia card (MMC), serial data (SD) card interface, or memory stick interfaceHDQ and 1-Wire serial interfaceTwo light emitting diode (LED) pulse generator modulesFrame adjustment counter
For the DSP:Three 32-bit timersA 16-bit watchdog timerAn interrupt handlerMcBSP1: Multichannel buffered serial portMcBSP3: Multichannel buffered serial portMCSI1: Multichannel serial voice interfaceMCSI2: Multichannel serial voice interface
Shared peripherals:UART1: UART modem with autobaud (16C750 compatible)UART2: UART modem with autobaud (16C750 compatible)UART3: UART modem with IrDA (16C750 compatible)Fourteen general-purpose input/output (GPIO)Mailbox
3.8.3 External Device Description
Table 3-16. Helen External Memory
Interface SPEC
Device Name Maker Write Access Time Read Access Time
Flash1 TH50VPF5683DASB TOSHIBA 70ns 70ns
Flash2 TC58FVB641XB-70 TOSHIBA 70ns ` 70ns
SRAM TH50VPF5683DASB TOSHIBA 70ns 70ns
MIDI YMU762 YAMAHA
3. TECHNICAL BRIEF
- 39 -
3.8.4 GPIO Map
Helen has 8 ARMIO and 14 GPIO ports. Each port can be configured as input or output.
Table 3-17. GPIO Map Table
Table 3-18. ARMIO Map Table
I/O # Application I/O Resource Inactive State Active StateStateI/O (0) USB_DETECT I USB LOW HIGHI/O (1) CAMERA_POS_DET I GPIO LOW (Front) HIGH (Rear)I/O (2) YMU762_IRQ I GPIO HIGH LOWI/O (3) KEYPAD_LED_ON O GPIO LOW HIGHI/O (4) MAIN_LCD_CD_SEL O GPIO LOW (Data) HIGH (Command)I/O (5) Not Implemented On
ChipI/O (6) HEL_FOLDER_DET I GPIO LOW (Close) HIGH (Open)I/O (7) HEL_IND_LED_O O GPIO LOW HIGH
I/O (8) HSPEAKER_EN O GPIO LOW HIGH( 3.0V LDO OFF) ( 3.0V LDO On)
I/O (9) HEL_IND_LED_G O GPIO LOW HIGH
I/O (10) Not Implemented OnChip
I/O (11) PC_IRDA_SEL O GPIO HIGH (UART3 is connected LOW (UART3 is connectedto Receptacle) to IrDA)
I/O (12) SUB_LCD_CD_SEL O GPIO LOW (Data) HIGH (Command)I/O (13) HF_CALL_OFF_ON O GPIO LOW HIGHI/O (14) EL_ONOFF O GPIO LOW HIGH
I/O (15) HEL_IND_LED_B O GPIO LOW HIGH
I/O # Application I/O Resource Inactive State Active StateStateI/O (0) HEL_TX_MBOX O GPIO LOW HIGHI/O (1) MAIN_LCD_RES O GPIO HIGH LOWI/O (2) SUB_LCD_RES O GPIO HIGH LOWI/O (3) YMU762_RST O GPIO HIGH LOWI/O (4) MAIN_LCD_LED_ON O GPIO LOW HIGHI/O (5) _HF_DET I GPIO LOW HIGHI/O (6) STEREOJACK_DET I GPIO LOW HIGHI/O (7) CAL_TX_MBOX I GPIO LOW HIGH
3.8.5 Helen Power
There are 5 LDO (Low Drop Output) regulators and 1 DC-DC converter for Helen and Melody IC.Fig. 3-20 shows the power supply related blocks for Helen and Melody IC. Table 3-19 shows theoutput level of each power source.
Figure 3-20. Helen Power sources
Table 3-19. Helen & MIDI LDO Output Level Table
C831
10u
ADJ43 EN
2 GNDIN1 OUT5
MIC5219BM5
U809
C86110u
C8880F
100K
R84
4
BYPASS 4
2 GND
VEN3
VIN1
VOUT5
LP3985IM5X-3.3U810
R80
7
200K
U813
TC7SZ08AFE
A12 B
GND3
VCC5
4Y
330pC853
Q802DTC144EE
BC
E
10u
P11 P2 2
P33 4
P4
C866
L801
4.7uH
47uFC852
5
U812NCP500SN18T1
EN3 GND2NC 4
VIN1 VOUT
D11
D223
D3D4
67D5
D6 8
G4
5 S
Q801NTHS5441T1
R80
8
150K
R85
7
270K
C85133u
C8630.01u
VBAT
C85510u
300K
R81
0
C85610u
3 GND24NC
1 VDD 5VOUT
R85
5
180K
U890
R1111N151B-TR
CE
D80
2
MB
RM
120L
T3
R821
10K
3
5 VINU808LTC1701BES5
2G
ND
RUN4
1SW
VFB
R811
0
100K
R869
470pC858
C830470p
R87
5
1M
VRIO
R87
8
12K
C82910u
R84
2
20K
10uC900
R84
3
2.2K
4ADJEN3 GND21 IN 5OUT
VBAT
U804
MIC5219BM5
ONNOFF_BUF
HEL_CORE_1.5V
SPK_VDD
USB_PWR
AVDD
LCD_1.8V
HEL_PLL_1.5V
HEL_IO_MEM_2.8V
USB_VDD
ONNOFF_TO_BUF
SPEAKER_EN
Output Voltage Usage Enable Control
HEL_CORE_1.5V 1.5V Digital Core of Helen ON_nOFF(from Nausica)
HEL_PLL_1.5V 1.5V DPLL of Helen ON_nOFF
LCD_1.8V 1.8V Main LCD Module ON_nOFF
HEL_IO_MEM_2.8V 2.8V IO pin of Helen and Melody IC ON_nOFF
ACDD or SPK_VDD 3.0V Audio analog switch, Speaker SPEAKER_ENamp of Melody IC (Helen GPIO)
USB_VDD 3.3V USB module of Helen USB_PWR (receptacle)
- 40 -
3. TECHNICAL BRIEF
- 41 -
3.8.6 Camera & Camera FPC Interface
The Camera module is connected to main board with 21-pin FPC connector (21FXL-RSM1-TB). Itsinterface is dedicated camera interface port in Helen. The camera port supply 8MHz master clock tocamera module and receive 4MHz pixel clock, vertical sync signal, horizontal sync signal and 8bitsYUV data from camera module. The camera module is controlled by I2C port in Helen.
Table 3-20. Interface between Camera module and main board (in Camera Module)
3.8.7 Display & LCD FPC Interface
LCD module include devices in table 3-21.
Table 3-21. Devices in LCD Module
Device TypeMain LCD 176 x RGB 220 65K Color TFD LCD
Sub LCD 84 x 40 mono FTN LCD
Main LCD Backlight White LED
Sub LCD Backlight Deep Blue EL
PIN. SYMBOL FUNCTION I/O REMARKS
1 NC -
2 VDD_L 2.8V P
3 VDD_H 2.8V P
4 GND Ground P
5 SCL Serial Clock Signal for I2C -
6 XRST Reset Signal -
7 HSYNC Horizontal Sync Signal O
8 SDA Serial Data for I2C I
9 D6 YUV Data O
10 D7 YUV Data O
11 D4 YUV Data O
12 D5 YUV Data O
13 VSYNC Vertical Sync Signal O
14 D1 YUV Data O
15 D2 YUV Data O
16 DCK Pixel Clock Signal O
17 D0 YUV Data O
18 D3 YUV Data O
19 GND Ground P
20 CKIN Master Clock Signal I
21 NC -
3. TECHNICAL BRIEF
- 42 -
3. TECHNICAL BRIEF
LCD module is connected to key board with 30-pin FPC connector (AXK830145J) and Speaker,Receiver, Vibrator is connected by soldering the leads to 6 pads in LCD module. The main LCD is controlled by McBSP2 Port(in SPI Mode) in Helen and the sub LCD is controlled byuWire Port in Helen.
Table 3-22. Interface between LCD module and Speaker, Receiver, Vibrator
PIN. SYMBOL FUNCTION I/O REMARKS
SPK TERMINAL
1 E- Ear Piece Minus O
2 S+ Loud Speaker Plus O
3 E+ Ear Piece Plus O
4 S- Loud Speaker Minus O
MOTER PAD TERNINAL
1 MB MOTOR Power O
2 MG MOTOR Ground O
- 43 -
Table 3-23. Interface between LCD module and main board (in LCD Module)
3. TECHNICAL BRIEF
PIN. SYMBOL FUNCTION I/O REMARKS
1 Motor GND Ground P
2 Motor Batt MOTOR Power P
3 NC Not Connect -
4 NC Not Connect -
5 EAR PIECE+ Ear Piece Plus I Serial data transfer line
6 EAR PIECE- Ear Piece Minus I
7 LOUD SPK+ Loud Speaker Plus I
8 LOUD SPK- Loud Speaker Minus I
9 NC Not Connect -
10 NC Not Connect -
11 LED- LED cathode P
12 LED+ LED anode P
13 EN On/Off EL ON/OFF signal I
14 VDDL Power supply for internal logic (1.8V) P
15 VDD(VDDI) Power supply for system and I/O logic (2.8V) P
16 VDD(EL) Power supply for EL Driver (2.8V) P
17 GND(EL) Ground for EL & EL Driver P
18 GND(LCD) Ground for system P
19 SDA_S Sub Display data I
20 SCK_S Sub Serial Data clock -
21 RS(A0)_S Sub Serial Data command select signal I
22 XCS_S Sub Chip select signal I
23 XRES_S Sub Reset signal -
24 VDDL Power supply for internal logic (1.8V) P
25 SD0_M Main Serial data I
26 XWR_M Main Write signal I
27 A0_M Main Data command select signal I
28 XCS_M Main Chip select signal I I
29 XRES_M Main Reset signal I I
30 GND(LCD) Ground for system P
3.8.8 Main LCD Backlight Illumination
There are 6 white LEDs in main LCD backlight circuit which are driven by ‘PWL_MAIN_LCD_BL’ linefrom Calypso. PWL is used for backlight brightness control.
Figure 3-21. Charge Pump Circuit for Main LCD Backlight
Figure 3-22. Main LCD Backlight Circuit
* R1, R2, R3 : 47ohm
* LED1, LED2, LED3 : NACW215T (Nichia)
3. TECHNICAL BRIEF
- 44 -
C65110u
R658 470
4.7
R627
100K
R62
9
R62
8
100K
R64
7
C612
1u
VBAT_2
1uC606
U602 SC600BIMSTR
CF1+2 9CF1-
10CF2+
CF2- 7
6EN
4 FID0
FID15
GND 83 VIN
1 VOUT
C67
622
0p
C60
51u
MAIN_LCD_LED+
PWL_MAIN_LCD_BL
MAIN_LCD_LED+
GND
- 45 -
3. TECHNICAL BRIEF
3.8.9 Sub LCD Backlight Illumination
A family of Deep blue EL is used for Sub LCD backlight and Citizen’s ELD-3410 is used for its driver.GPIO_14(EL_ONOFF) in Helen does ON or OFF the ELD-3410 inverter, which include the inductorin itself.
3.8.10 Indicator Illumination
Indicator LED illumination circuit can make 7 colors using multi-color LED. Multi-color LED consistsof orange LED, green LED and blue LED. GPIO_7 (HEL_IND_LED_O), GPIO_9 (HEL_IND_LED_G)and GPIO_15 (HEL_IND_LED_B) in Helen do ON or OFF its own LEDs.
Figure 3-23. Indicator Illumination Circuit
In case of power off mode (ON_OFF=Low), if TA is inserted, NC7SB3157P6X multiplexer isswitched to charger and orange LED is turned-on. In other case (ON_OFF=High), Multi-color LED iscontrolled by GPIO_7 (HEL_IND_LED_O), GPIO_9 (HEL_IND_LED_G) and GPIO_15(HEL_IND_LED_B) in Helen
R62
0
100
4A3 B0
B112 GND
6S5VCC
NC7SB3157P6XQ602
0.1uC666
R619
10K
R68
1
10
34
LN
J717
W80
RA
1
LD
601
12
LD
603
LN
J717
W80
RA
1
12
34
2
56
31
4
EMX1Q603
10KR624
10
R68
2
R60
1
56
R623
20K
VBAT
20K
R625
R62
1
47K
2.7K
R66
1
12
34
LN
J717
W80
RA
1
LD
602
VBAT
R62
2
33150
R62
6
2
56
31
4
EMX1Q604
ONNOFF
HEL_IND_LED_O
HEL_IND_LED_B
CHARGER
HEL_IND_LED_G
3.8.11 Keypad Illumination
There are 16 Blue LEDs in key board backlight circuit, which are driven by ‘GPIO_3’ line from Helen.
Figure 3-24. Keypad Backlight Control Circuit on Main Board
Figure 3-25. Keypad Backlight Circuit
- 46 -
3. TECHNICAL BRIEF
LD6
LD3
39R3
LD2
LD11
R2
39
LD1
LD9
LD5
C20.1uLD
14
LD12
LD8
LD16
LD7
VBAT
R4
39
LD4
LD10
39R1
LD13
LD15
KEY_LED-
2.7K
R61
1
12
R614
R612
12
31
4
EMX18Q601
2
56
KEY_LED-
GPIO_3 >>
3. TECHNICAL BRIEF
- 47 -
3.8.12 Key pad
There are 26 key buttons and 3 side keys in Fig. 3-26 shows the Keypad Circuit .
Table 3-24. Key matrix mapping Table
Figure 3-23. Indicator Illumination Circuit
KEY_ROW[4] KEY_ROW[3] KEY_ROW[2] KEY_ROW[1] KEY_ROW[0]
KEY_COL[0] Soft Option Navigate Clear Navigate•
KEY_COL[1] Function 3 Navigate OK Back
KEY_COL[2] Function 2 SEND Navigate Function 1
KEY_COL[3] # 9 3 6
KEY_COL[4] 0 8 5 2
KEY_COL[5] * 7 4 1
KB12
10K
R9
KB23
KB9
KB22
R6
10K
KB1
KB7
KB15
KB8
KB13
KB10
KB5
KB21
V2.8
KB2
KB26
KB14
KB3
KB6
KB17
KB25
2KR7
10K
R8
KB16
KB19
10K
R5
KB20
KB18
KB11
KB24
KB4
_END_ONOFF
KEY_COL0
KEY_
ROW
4
KEY_
ROW
3
KEY_
ROW
2
KEY_
ROW
1
KEY_
ROW
0
KEY_COL1
KEY_COL2
KEY_COL3
KEY_COL4
KEY_COL5
- 48 -
3. TECHNICAL BRIEF
3.8.13 Folder ON/OFF Detection
GPIO_6(HEL_FOLDER_DET) detects the folder ON or OFF.
Figure 3-27. Folder ON/OFF Detection Circuit
3.8.14 Camera Position Detection
GPIO_1 detects the camera position (front or back).
Figure 3-28. Camera Position Detection Circuit
V2.8
C110p
51K
R11
3G
ND
2O
UT
VD
D1
A32
12E
LHU1
0.1uC3
HEL_FOLDER_DET
SP
42
C60110p
R646 10K
A32
12E
LH
U60
1
3G
ND
2O
UT
VD
D1
HEL_IO_MEM_2.8V
0.1uC602 R
680
51K
R602
>>GPIO 1
3. TECHNICAL BRIEF
- 49 -
3.8.15 USB Interface
The universal serial bus (USB) function module supports the implementation of a full-speed devicefully compliant with the USB 1.1 standard. It provides an interface between the MPU core (TI925T)and the USB wire and handles USB transactions with minimal TI925T intervention. The modulesupports one control endpoint (EP0), up to 15 IN endpoints, and up to 15 OUT endpoints. The exactendpoint configuration is software programmable.
The specific items of a configuration are for each endpoint, the size in bytes, the direction (IN, OUT),the type (bulk/interrupt or ISO), and the associated number. The module also supports three DMAchannels for IN endpoints and three DMA channels for OUT endpoints for either bulk/interrupt or ISOtransactions.
Table 3-25. USB Signal Interface for Helen
Figure 3-29. USB W2FC Function Connection
R1,R2 Value depends on transceiverR3 1.5K Ohm+/-5%R4,R5 Weak pulldown (optional, see text)C1U1
Low ESR cap,minimum 120 uFTransient suppessor, such as SN65220, SN65240, or SN75240
UBS Funtion
UBS.DP UBS differential (+) line
UBS.DM UBS differential (-) line
UBS.PUEN UBS clock (6 MHz)
UBS.CLKO UBS pullup enable
UBS.VBUS UBS VBUS detect input
3. TECHNICAL BRIEF
- 50 -
3.8.16 USB detect
USB is detected by Helen GPIO
Figure 3-30. USB Detect Circuit
3.8.17 IrDA
This model supports SIR IrDA. Helen’s UART3 module support IrDA or UART. Uses both two mode.During the normal operation, UART path is connected to IrDA. There is a Quad2:1 Mux to selectIrDA. If external connection by UART is needed, the quad 2:1 mux set the UART path to receptacle.
Figure 3-31. Helen UART3 IrDA Path
100K
R80
2 2
45
31
UMC4NQ809R896
1K
HEL_IO_MEM_2.8V
USB_DETECT
USB_VDD
C8010.47u
1B1
1B23
2A7
2B15
2B26
93A
3B111
103B2
124A
144B1
4B213
GND8
1S
16VCC
15_OE
U802SN74CBTLV3257DGVR
1A4
28
3TXD
6VCC
U801CIM-80S7B-T
GND7
1LEDA
LEDK2
RXD4
5SD
SHIELD
HEL_IO_MEM_2.8V
HEL_UART_PC_RX
PC_IRDA_SEL
HEL_UART_IRDA_TX
HEL_UART_PC_TX
HEL_UART_IRDA_RX
IrDA Transceiver
signals ToReceptacle
3. TECHNICAL BRIEF
- 51 -
3.8.18 Vibrator
Activating vibrator, Calyso makes ‘MOTOR_EN’ to High state (2,8V) and MOTOR_BATT outputsHigh. And then, MOTOR_BATT signal connects with vibrator device and vibrator device is activated.
Figure 3-32. Vibrator Circuit
3.8.19 Hands Free Detect
Hands Free is detected by Helen GPIO.
Figure 3-33. Handsfree Detect Circuit
R82
6
0
UMT2907AQ805
B
C
E
DTC144EEQ804
10
R82
9
VBAT
R82
7
47K
C8320.1u
R825
2KMOTOR_EN
MOTOR_BATT
2
45
31
UM
C4N
Q80
8
HEL_IO_MEM_2.8V
10K
R86
8
R80
1
100K
HF_Detect_Signal_From_Receptacle
3. TECHNICAL BRIEF
- 52 -
3.8.20 MELODY IC
Figure 3-34. Handsfree Detect Circuit
Table 3-25. Supply Volt. Table
0.1uC849
10uC846
0
R840
C847390p
VSS
_CS29
_IRQ3
31_RD
4_RST
28_WR
EQ1
EQ213
14 EQ3
HPOUT_L
10 HPOUT_R11
IOVDD 32
2 LEDMTR19
NC5
6PLLC
SPOUT117
SPOUT218
SPVDD15
16SPVSS
VDD 7
VREF 9
8
30A0
1CLK1
D027
D126
D225
D324
D42322
D5 21D6 20D7
12
YMU762U807
R834 3.3K
C84
868
n
8.2K
R835
R83
7
82K
1000pC844
C85047p
R836
8.2K
0R818
R841
0
HEL_IO_MEM_2.8V
0.1uC843SPK_VDD
R817
0.1uC828
C845 0.022u
HEL_CLK_12M_OUT
LOUD_SPKP
LOUD_SPKM
Speaker_Output_From_Analog_Switch
_YMU762_IRQ
_YMU762_RST
HEL_NFOEHEL_NFCS_3
HEL_NFWE
HEL_FADD(1)
HEL_DATA(3)HEL_DATA(2)HEL_DATA(1)
HEL_DATA(7)HEL_DATA(6)HEL_DATA(5)HEL_DATA(4)
HEL_DATA[0] HEL_DATA(0:15)
HE
L_D
AT
A(0
:15)
Supply Voltage Usage Enable Control
HEL_IO_MEM_2.8V 2.8V Digital VDD of Melody IC ON_nOFF (from Nausica)
SPK_VDD 3.0V Analog VDD of Melody IC ON_nOFF
4. CALIBRATION S/W USER GUIDE VER 1.0
4.1 IntroductionThis document describes the construction and the use of the Software used for the Calibration ofGSM/GPRS Multimedia Mobile. The Calibration menu and their results are displayed by a PCterminal connected to the GSM/GPRS Multimedia Mobile.
This Calibration Software includes APC Calibration, AGC Calibration and *Flash File Systemaccess (Read/Write) to apply Calibration results to the Phone. This Calibration Software is called‘CALMON’. From now on, the Calibration Software will be called CALMON in this document.
4.2 CALMON Environment
4.2.1 H/W Environment
• PC with RS-232 Interface & GPIB card installed • GSM/GPRS Mobile Set• HP8960 Instrument• Power Supply• Etc (GPIB cable, Serial Cable, RF Cable, Power Cable)
4.2.2 S/W Environment
• National Instrument GPIB & Visa (2.60 full) Driver Install
• HP8960 Vxi driver
• CALMON Exe Files
• OS : Win98, Win2000 & WinXP
• Serial Port Configuration(Baud rate : 115200 / Char length : 8bit / Parity : No / Bits stop : 1bit )
*Flash File System – Make a Flash the hierachy, organization and naming of files and directories.FFS is used for storing many kinds of data and configuration parameters that should be non-volatileacross power-cycles. This includes RF calibration parameters(,and so on) adjusted andprogrammed during Calibration and production test.
4. Calibration S/W User Guide Ver 1.0
- 53 -
4. Calibration S/W User Guide Ver 1.0
- 54 -
4.2.3 Configuration Diagram of Calibration Environment
Figure 4-1. Calibration Configuration
When you calibrate the Mobile, make a configuration of Calibration environment like Figure1.
For making the CALMON can control each instrument and Phone, Using GPIB cable, connectInstrument and the PC (in fig.4-1,e.g. it’s notebook PC) and using Serial Cable, Make a connectionof the Phone and the PC, also. To supply the Phone with electricity, use Power cable from Powersupply.
When Rx Calibration (AGC) is run, connect HP8960 to the Phone’s antenna with RF cable. Thus,CALMON can control the Instrument (HP8960) to run Rx Calibration with the Phone that receivedthe RF signal from the instrument controlled by CALMON.
When Tx Calibration (APC) is run, vice versa CALMON control the Phone’s operation so theinstrument receive the power signal through the RF cable and measure the signal to do the TxCalibration.
HP8960
PS2521G
NoteBook
GPIB Cable
Power Cable
RF Cable
Serial Cable
4.3 Calibration Explanation
4.3.1 Overview
In this section, it is explained calibration items in the CALMON. Also, the Explanation includestechnical information such as basic Formula of Calibration and settings for Key parameters in eachCalibration Procedure.
At first, when any of Calibration is done, the Results are displayed in the CALMON Result Window.And in some case, as user’s choice the Result of Calibration will be stored in Flash File System fornon-volatile across power cycle.
Thus,for using Flash File System, Flash File System(From now on ‘FFS’) should be formattedbefore anything else and should have hierarchy of directories in advance to be stored for calibrateddata after the Calibration is done.
Calibration Items of CALMON
• General Items- APC Calibration- AGC Calibration
• Item from Specific requirementFlash File System AccessBattery Calibration
4.3.2 APC Calibration (*Auto Power Control )
APC Calibration is for adjusting voltage level that can make the wanted level output in antenna andadjusting Ramping shape at assigned level to be able to remain in Spec. Mask. So, there are twosteps for APC calibration.
- APC DAC Calibration for each Power Index (using a Standard Channel)- Ramp coefficients calibration for each Power Index.. (using a Standard Channel)- APC DAC calibration for each defined Channel. (using Standard Power Level)
# Standard Channel for EGSM (channel 40) / Standard Channel for DCS (channel 700)
*Actually this is not “Automatic”, but “Pre-defined” level according to each boards.We need to find out what voltage level can make the wanted level output in antenna.(We need toknow the DAC value for each power level in the point of layer1 software.)
4. Calibration S/W User Guide Ver 1.0
- 55 -
4.3.2.1 APC DAC Calibration for each power indexThe TX power levels needs to be calibrated in order to achieve the required accuracy
To calibrate the TX power levels the following steps have to be performed for both bands :
1. Setup the mobile to transmit on the channel specified in Table 4.1.
2. Setup up the power level that needs to be calibrated.
3. Calibrate the power level according to Table 4.1.
4. If output power is higher than specified in Table 4.1. then decrease the APC level.
5. If output power is lower than specified in Table 4.1. then increase the APC level.
6. Proceed with the steps above until all power levels both bands have been calibrated.
Table 4-1 EGSM900 and GSM1800 Power level settings
4. Calibration S/W User Guide Ver 1.0
- 56 -
Power level EGSM900 @ channel 40 [dBm] GSM1800 @ channel 700 [dBm]
0 - 30
1 - 28
2 - 26
3 - 24
4 - 22
5 33 20
6 31 18
7 29 16
8 27 14
9 25 12
10 23 10
11 21 8
12 19 6
13 17 4
14 15 2
15 13 0
16 11 -
17 9 -
18 7 -
19 5 -
4.3.2.2 Ramp Up/Down Calibration for each Power IndexRamp Up/Down Calibration is to adjust Ramp Template Up/Down Coefficients for Ramping shapeat assigned level to remain in Spec. Mask for defined Power Levels of both band.
There are 16 Indexes for both Up and Down Ramp Template. Each Ramp Template has 31Coefficients (0 to 30), The Important thing of Ramp Up/Down Calibration is maintenance of Sum ofindexes’ coefficients, Up and Down separately. The sum has to be 128 exactly.
So, Special Consideration needs to maintain specific sum value ‘128’ and to make Ramping shapein Spec.Mask at the same time.
4.3.2.3 APC DAC Calibration for Each ChannelWhen APC DAC Calibration is done for each Power Index, APC DAC for predefined channelsshould be calibrated for both GSM and DCS to make each Channel have Wanted Transmit Power.Standard Power Level Indexs for each band are for GSM Index is 10, for DCS Index is 5. So, At firstget the APC DAC Calibrated Value at Standard Power Level Index and based on this calibratedvalue from Standard Power Level, do the calibration for each Channel in Table 4.2. In this case,Default Channel Calibration Value is set to 128. After Channel Calibration, If output power is higherthan specified value then decrease Channel Calibration Value at lower than 128. If output power islower than specified value then increase Channel Calibration Value at higher than 128
Table 4.2 Specified Arfcn Limits and Test Arfcns for Apc Channel calibration
4.3.3 AGC Calibration
The AGC block generates automatic gain control from the digital baseband signal and then feeds itto the analog IF variable gain amplifier (VGA) to maintain a constant, in-band signal and interferencepower for the A/D converters. Adjusting G_magic, make Power level received by Mobile equal tocalculated power level by itself. - G_magic Calibration for Both Band (GSM, DCS)
4.3.3.1 G_magic CalibrationTo calibrate GMagic the following steps have to be performed for both bands:
1. Setup the mobile to receive on the ARFCN specified in Table 4.3.
2. Set the AGC in the receiver to the gain specified in Table 4.3.
3. Set the generator level to TL specified in Table 4.3.
4. Write *INI_AFC value to MS
5. Set Test frequency as specified in 0 plus 67Khz.
6. Measure PM1.
7. Set Test frequency as specified in 0 minus 67Khz.
8. Measure PM2.
9. Calculate PMAV = (PM1 +PM2 )/2.
*INI_AFC value can be obtained by performing the VCTCXO Calibration procedure, if that hasn’talready been done.
4. Calibration S/W User Guide Ver 1.0
- 57 -
Arfcn Limit for Apc Channel Test Arfcn For Apc Channel Calibration Calibration
EGSM900 20, 40, 62, 80, 100, 124, 992, 1023 10, 30, 51, 71, 90, 112, 983, 1007
DCS1800 558, 604, 650, 696, 742, 788, 834, 885 535, 581, 627, 673, 719, 765, 811, 857
10. Calculate GMagic = (PMAV – AGC – TL)x2.
TL is the test signal level in dBm
PMAV is an average over the two power measurements by the DSP
AGC is the IF gain in dB
11.Download GMagic to MS.
* Note : Instead of step 5 to 8 you could also test only at the ARFCN center frequency modulated bya pseudo–random bit sequence (PRBS).
Table 2.3 Test settings for calibrating GMagic
4.3.4 Flash File System
Flash File System (FFS) is used for storing many kinds of data and configuration parameters thatshould be non-volatile across power-cycles. This includes RF calibration parameters and SystemConfiguration, Production Adjustment, Test Data, User/MMI Data — Volume, SMS, Melodies, etc -adjusted and programmed during Calibration and production test.
Flash File System is consist of the Hierarchy of directories and files. These are lists of directoriesand files using in CALMON. Mosts are for RF Calibration parameters.
4. Calibration S/W User Guide Ver 1.0
- 58 -
/gsm/rf/ 4 GSM RF calibration and configuration.
/gsm/rf/afcdac Initial AFC DAC value.
/gsm/rf/afcparams AFC parameters
/gsm/rf/tx/ramps.900 RF Transmitter PA ramps for GSM/EGSM
/gsm/rf/tx/ramps.1800 RF Transmitter PA ramps for DCS
/gsm/rf/tx/levels.900 RF Transmitter levels table for GSM/EGSM
/gsm/rf/tx/levels.1800 RF Transmitter levels table for DCS
/gsm/rf/tx/calchan.900 RF Transmitter channel calibration for GSM/EGSM
/gsm/rf/tx/calchan.1800 RF Transmitter channel calibration for DCS
/gsm/rf/tx/caltemp.900 RF Transmitter temperature calibration for GSM/EGSM
/gsm/rf/tx/caltemp.1800 RF Transmitter temperature calibration for DCS
/gsm/rf/rx/agcglobals RF Receiver AGC global parameters
/gsm/rf/rx/agcwords RF Receiver AGC gain programming words table
/gsm/rf/rx/il2agc RF Receiver AGC il2agc tables
/gsm/rf/rx/calchan.900 RF Receiver channel calibration for GSM/EGSM
Receive Band Test ARFCN AGC setting [dB] TL [dBm] Test frequency [MHz]EGSM900 40 34 ˜ -74.5 943.0
GSM1800 700 34 -74.5 1842.8
4. Calibration S/W User Guide Ver 1.0
- 59 -
So, this is a Flash File System structure.And Flash File System Access is for Accessing to Read and Write Control through the Flash.
*This directory contains RF calibration data and tables adjusted during production. It also containsfiles that are only used during development for overriding compiled-in default data and parametersfor the RF.
4.3.5 Battery Calibration
The battery sensor uses the baseband ADC to read the battery voltage (Vbat), and the ADC internalreference voltage is the largest contributor to measurement inaccuracy. Measuring the ADC slopeand offset makes it possible to correct this in the SW.
To calibrate the Battery Voltage the following steps have to be performed :1. Set the Power supply Voltage to 4.2V specified in Table 4.4.2. Read ADC value and Compare whether Adc value is in between Lower Limit and Upper Limit.
3. if it is, Save it to FactorySettingData.cc2cv_Voltage value.4. Set the Power supply Voltage to 3.35V specified in Table 4.4.5. Read ADC value and Compare whether Adc value is in between Lower Limit and Upper Limit.6. if it is, Save it to FactorySettingData.shutdown_Voltage value.7. Proceed with the steps above until two Voltage levels have been calibrated.
Table 4.4 Battery Calibration Settings
/gsm/rf/rx/calchan.1800 RF Receiver channel calibration for DCS
/gsm/rf/rx/caltemp.900 RF Receiver temperature calibration for GSM/EGSM
/gsm/rf/rx/caltemp.1800 RF Receiver temperature calibration for DCS
/gsm/rf/rx/agcparams.900 RF Receiver AGC parameters for GSM/EGSM
/gsm/rf/rx/agcparams.1800 RF Receiver AGC parameters for DCS
Voltage Level Lower Limit Upper Limit4.2V (cc2cv_Voltage) 0x250 0x290
3.35V (Shutdown_Voltage) 0x1d0 0x210
4. Calibration S/W User Guide Ver 1.0
- 60 -
4.4 Program Operation
4.4.1 APC DAC Calibration
Figure 4-2. APC DAC Calibration Basic Settings Window
• Basic SettingTarget Control
- Band : You can select Band either GSM900 (EGSM) or DCS1800. If changethe band, Arfcn will be changed automatically by the available value of selected Band.
- TCH : You can read current Target’s Tch Arfcn.- Tx Power Level : You can change the Tx Power level of Target.
Usually APC Level and Ramp template Index are followed accordingly by the value of TxPower Level.but, You can also change these parameters’ value.
- Update all values : You can read all values of current Window’s parameter from the Target
Instrument Control
- Tx Power Level : You can change the Tx Power level of Instrument - Cable Loss : Compensate the Cable Loss through the RF Cable
4. Calibration S/W User Guide Ver 1.0
- 61 -
4.4.1.1 APC Measurement Window
Figure 4-3. APC Measurement Window
Fig4-3 is a APC Measurement Window. In the Fig 4-3, it’s the measurement of Tx Power Level 5
• Tx Power Measurement
When click the Meas.start, measure the Target’s Tx Power read from the instrument by thevalue of current selection of Power Level. And the value measured from the instrument iscompared with the Expected power pre-defined by the specification. So, decide whether thiscompared value is in allowable Margin from specification or not. If it is, then fill Mask Test itemgreen and write ‘Pass’ (). If not, it will be filled red and written ‘Fail’. Statistics for MeasuredMS tx Power : it shows measured Tx Power Value. And in addition, Avg., Min / Max, Differencebetween Expected Power and Measured power, Variance from Avg. etc statistical results aredisplayed. When you do the Measurement, you can select whether you consider Cable loss ornot. Measured margin : to check how much margin measured power have from upper andlower limit specified.
- 62 -
4.4.1.2 APC DAC Calibration Window
Figure 4-4. APC DAC Calibration Window
• APC DAC Calibration
APC Calibration is adjusting APC DAC that can make the wanted level output in antenna. Standard Channel for EGSM is Traffic channel 40 and for DCS is Traffic channel 700.Each band has different range of Power Level for Calibration. 5 to 19 for EGSM. 0 to 15 for DCS.When click CAL Start, APC DAC Calibration starts, It’s working Automatically through thelevels pre-defined from the EGSM900 to the DCS1800 band. You can just check the APC DAC Result shown from the List Box and if you have more time tocheck, compare the Tx power by this calibrated APC DAC with Tx Power specified andcheck the accuracy of APC DAC Calibration. Or see the Progress bar is running to the 100%end. Processing time is the time taken during the entire APC DAC Calibration Procedure. After allProcedure has done, the Calibrated data has to be stored in Flash File System . Fortunately, it’sstored automatically in flash after APC DAC Calibration is completed.
4. Calibration S/W User Guide Ver 1.0
- 63 -
4. Calibration S/W User Guide Ver 1.0
4.4.1.3 APC Ramp Calibration Window
Figure 4-5. APC Ramp Calibration Window
• APC Ramp Calibration
APC Ramp Calibration is for both GSM and DCS band, to adjust Ramp Template Up/DownCoefficients for Ramping shape at assigned level can remain in Spec.Mask per each PowerLevel. As you see the Red Box in the Fig 4-5, there are 16 Indexes for both Up and Down RampTemplate each. And each Ramp Template Index has its coefficients, 31 Coefficients (0 to 30).You can change each coefficient value, but the sum of all coefficients has to be 128. In this Window the upper part of Figure, there is basic setting menu for parameters. But that’ssimilar to APC DAC Calibration.so, section 4.1 will help you. When click the Meas.start, the window will show you the avg. Tx Power of current PowerLevel and the plot for Ramping Shape from current Ramp Index’s Coefficients’ values. They are from the instrument. And you can change the visual part of the graph as Full or Risingedge,etc.
- 64 -
4.4.1.4 APC Channel Calibration
Figure 4.6. APC Channel Calibration
When APC DAC Calibration is done for each Power Index, APC DAC for predefined
channels should be calibrated for both GSM and DCS to make each Channel have Wanted
Transmit Power. Standard Power Level Indexs for each band are for GSM Index is 10, for
DCS Index is 5. So, At first get the APC DAC Calibrated Value at Standard Power Level
Index and based on this calibrated value from Standard Power Level, do the calibration for
each Channel predefined in Table 4.2. In this case, Default Channel Calibration Value is set
to 128. After Channel Calibration, If output power is higher than specified value then
decrease Channel Calibration Value at lower than 128.
When click the Chan Cal start, it will start to run automatically from EGSM900 to
DCS1800 Band for each Arfcn predefined. So, Whole Results will shown in List Box.
is APC DAC of Standard Channel , is Calibration results for each channel, APC’s
Compensated Value for each Channel.
4. Calibration S/W User Guide Ver 1.0
- 65 -
4.4.2 AGC Calibration Window
Figure 4-7 AGC Calibration Parameters Control Window
• Basic SettingTarget Control
- AFC Settings : Read INI_AFC DAC value from the Target.and also you can write anothervalue you want to change. But when you try to do AGC Calibration precisely,you should set the Calibrated INI_AFC value to the Target.
- AGC gain : Set the AGC gain Value to 34dB. It’s calculated based on the IL(Input Level = -74.5) from the Target.
- AGC Algorithm : To get the AGC G-Magic, Disable the AGC algorithm from L1.-
AGC Parameters : G-Magic Value will be updated automatically after the AGC Calibration iscomplete. And the other AGC Parameters (LNA ~)will have appropriate valuefrom the definition.
- Measurement setup : You can choose the option to see the result you want.You can choose any of three selection (RSSI,DSP-PM and G-Magic)and also you can choose multiple selection. And the results will bedisplayed as you chose. The results will be updated moment bymoment.
Miscellaneous Control
- Cable Loss : Compensation for loss from RF cable between the instrument and theTartget.You can set the value per Band. (It is defined at the every Cable)
4. Calibration S/W User Guide Ver 1.0
- 66 -
4. Calibration S/W User Guide Ver 1.0
4.4.2.1 AGC Calibration Measurement Window
Figure 4-8. AGC Calibration Measurement Window
• AGC Calibration Measurement
After the Basic Setting from Fig 4-6, based on the set value of AGC Calibration Parameters fromcurrent window, CALMON (CALMON’s AGC Calibration Measurement Menu) does AGCMeasurement and displays the result. Measurement result that you already chose ( from fig 4-6) will be displayed. Figuring out from fig4-7, all of measurement options are chosen. RSSI,DSP-PM, G-Magic results are shown. When you click the AGC Measurement, Measurementstart. And if you click again, it will stop. DSP-PM from target PM mean from received PMvalues. RSSI, difference between the very first Power Level from instrument transmits andactually received Power Level that target received. only when you choose the Îth option, youcan also check the Cable Loss consideration . Calculated G-Magic.
- 67 -
4.4.2.2 AGC Calibration Window
Figure 4-9. AGC Calibration Window
• AGC CalibraitonAGC calibration is for Adjusting G_magic, make Power level received by Mobile equal tocalculated power level by itself. So, you have to find out proper value of G-Magic. When you clickthe
AGC Calibration, it will start. It’s programmed to run automatically from EGSM900 to DCS1800Band. So, after AGC Calibration, you can get the calibrated G-Magic for each Band. Duringthe AGC Calibration, when calculate the G-Magic, DSP-PM accumulated value is used inProgram internally. So, here is selective option for the count of DSP-PM accumulation. CurrentCount is 10. When AGC Calibration is done, calibrated G-Magic has to be non-volatile to beapplied permanently for the Target’s Performance. So, Calibrated G-Magic value has to bestored in Flash RF part. you can choose this storing option. And also you can save thecalibrated data to file and load calibrated data from file. Just click the Save Config button orLoad Config button. Feel free to choose the File name to save or load and directory in the dialogwindow.
4. Calibration S/W User Guide Ver 1.0
- 68 -
4.4.3 Flash File Window•
Figure 4-10. Flash File Window
It is intended to access Flash more simply like we access and control PC files at personalcomputer. when you click the Select File utton, following window will come.(Figure 4-9) Using
this window, you can load Flash File Data to file of PC or load the Flash file data from
PC file without difficulty. The content of the Red Box is the selected flash file. There are morefiles’ list in fig 4-12.Once you selet the file you want, you can read () or write ()the contents of flash file data on theListBox (), you can see the contents of /gsm/rf/tx/levels.900 file in figure 4-10.
4. Calibration S/W User Guide Ver 1.0
- 69 -
4. Calibration S/W User Guide Ver 1.0
Figure 4-11. Select File Save or Backup or Restore
There is a caution for you to use Flash File System.The hierarchy of directories and files is not configured in the beginning. Flash is like blank space atfirst. But downloading the Boot source and Application source, Flash has its own blueprint for theadvanced operation. First, you should do Format the Flash before using Flash File System like youformat the Floppy diskette before you use. And second, make the hierarchy of directory as Fig 4-12.
- 70 -
4. Calibration S/W User Guide Ver 1.0
Figure 4.12. ‘’Diretory/directory/File” Window from Flash File System
Although you do not format flash and make any directory in it, you will access flash nevertheless.Then following message window will come up. This window will ask you would want to format
flash and create directories in flash. You can make complete both just clicking ‘OK’ button.
Figure 4.13. Flash File Open Error Window
- 71 -
4. Calibration S/W User Guide Ver 1.0
4.4.4 Battery Calibration Window.
Figure 4.14. Battery Calibration Window
If you want to measurement ADC value, first You should choose the Voltage. When you chose it,
CALMON would set the power supply voltage to the value that you’ve chosen. And
FactorySettingData.cc2cv_voltage means the value reading ADC register from Target after setting
the target’s Vbat to 4.2V. and in additiions, between Upper and Lower Limit, CALMON compare
the value with the Limits and notify it as you see the Mask Test ‘Pass’( or ‘Fai l ’). If you want
Calibration of AD, then click the Cal.stop, CALMON will do Battery Calibration for both Voltage
Level one by one.
5. DOWNLOAD
5.1 Download Setup
5.1.1 Download Equipment
1) Data Kit 2) Desktop or Notebook PC3) Download tools4) Mobile phones of this model
5.2 Download Procedure
5.2.1 General Purpose
This document gives a guideline for upgrading software of this model using UART or USB port.
5.2.2 Download Environment
This model has two micro-processor, i.e., Calypso and Helen. In order to download or upgradeTarget SW* of each processor, the following working environments should be prepared:
- The model’s Data Link Kit is connected to COM1, COM2 or USB serial port in the Desktop orNotebook PC.
- Download tools that are copied to Desktop PC or Notebook PC.• X-monitor : Download tool for Calypso software.• FlashRW : Download tool for Helen software.
- Target SW* downloaded to mobile phones of this model.
Note: Target SW* means any necessary software to be downloaded to the mobile phone.
5.2.3 Download Procedure for Calypso Software
A. Unzip download tool for calypso processor (x-monitor.zip) in PC.B. Execute x-monitor.exe. And then select the “Target ” Menu shown in Figure 5-1. Then, choose
“Connect” in the Target Menu.
- 72 -
5. DOWNLOAD
Warning
You must use the Data Link Kit and Download tools for each processor that are provided from themanufacturer. Otherwise downloading process won’t properly
- 73 -
Figure. 5-1
C. A table will be displayed as shown in Figure 5-2. Then press the arrow-button and choose acorrect serial port. And press “OK” button.
Figure. 5-2
D. As the following window shown in Figure 5-3. is displayed, connect the phone to Data Link Kit andpower on it. If the connection is succeeded, the following screen will show the contents as shownin Figure 5-4.
5. DOWNLOAD
- 74 -
Figure. 5-3
Figure. 5-4
E. Click on “Flash” on the top menu and select “Get type” item as shown in Figure 5-4. and select“Erase and Program Appli Only+Boot” item as shown in Figure 5-5.
5. DOWNLOAD
- 75 -
Figure. 5-5
F. Finally choose the target SW that you want to download. And then you can see the followingwindow in Figure 5-6.
Figure. 5-6
G. If the downloading procedure is succeeded, and then the following window is shown.
5. DOWNLOAD
- 76 -
Figure. 5-7
5.2.3 Download Procedure for Helen Software
A. Executable used to load the software on Helen is FlashRW.exe. It is available in FlashRW.zip.Create directory and then unzip all files in FlashRW.zip into the directory.
B. Start FlashRW application, FlashRW opens a RS232 port automatically at startup. FlashRW supports an USB port also. To change the attribute of serial port, click serial portconfiguration button and change your serial options in following screen.
Figure. 5-8
5. DOWNLOAD
- 77 -
[ In the case of using RS232 port ]C. Following screen will be displayed if there is no error to open RS232 port in PC. Default serial
configurations are 115200-8-N-1.
Figure. 5-9
5. DOWNLOAD
- 78 -
D. Connect G8000 phone to data link kit and power on G8000 after click “connect” button. If theconnection is succeeded, the following screen will be displayed in the log window as shown infigure 5-9.
Figure. 5-10
5. DOWNLOAD
- 79 -
[ In the case of using RS232 port ]Note: Please make sure that LG-USB driver is installed correctly in PC.
C. Contrary to RS232 mode, FlashRW in USB mode is waiting for a target detection automaticallywhen FlashRW is startup or click the connect button like as following screen. Please make surethat data link kit is unplugged at this step.
Figure. 5-11
5. DOWNLOAD
- 80 -
D. Connect G8000 phone to data link kit and press power key until target flash writer codeisprogrammed successfully or target work manager identified correctly. If the connection issucceeded, the following screen will be displayed in the log window as shown in figure 5-9.
Figure. 5-12
5. DOWNLOAD
- 81 -
E. Before the download, please make sure that each files are selected correctly. In order to choosethe target SW that you want to download, click each “File Select” button indicate in Fig 5-9. Adialog open to select m0 or cp64 extension file. In case of choosing m0 extension file, this one iscompressed in a cp64 extension file.
F. Select your TargetSW using check box.
G. Click download button. Once load is finished, informations regarding loaded file are displayed likeas follow.
Figure. 5-13
5. DOWNLOAD
- 82 -
5.3 USB Driver Installation / Removal
5.3.1 Objective
This document is for installation of USB host driver when using FlashRW USB version.
It’s for Windows 2000. You never install this driver on Windows 98, Me OS. This can lead to a BlueScreen.
5.3.2 Windows Driver Installation
* Windows Driver Installation with Care
Only one driver relative to the USB device should be installed
First of all, delete data about previous driver file or installation file in Registry and WinNT systemrelative Folder. (Refer to the Removal of Driver)
- Put “ram_flashwriter_usb_v100.m0” into a flash writer code Select opening in FlashRW tool. (Referto the FlashRW manual in detail)
- Download FlashRW ver2.2.1 and change Serial Port Configuration from COM port to USB beforeyou install USB driver. Insert USB cable to PC or Notebook and cell phone. Power on the phonethen you can see the picture 1 below.
- For instance, here we install LG03_KJHusb.sys and LG_G8000_usb04.inf.
1) Copy those files into a temporary folder.*.inf file is for installation and *.sys for driver.
2) First of all, You can use “Add new hardware” from control panel or Plug and Play function to installthe driver.
5. DOWNLOAD
- 83 -
Proceed after Picture 1. 1) Be careful the new hardware installation pop-up magic tool beforepower on the cell phone. Just
cancel it.
Figure. 5-14
2) Select “No, Select new hardware from the item”.
Figure. 5-15
5. DOWNLOAD
- 84 -
.
3) Select other device from Picture 3. This is recommended.
Figure. 5-16
4 ) Click “Select from Disk” and select LG_G8000_usb04.inf file from the folder you made.
Figure. 5-17
5) How to check whether the driver file is installed properly or not:Go and check if G8000_usb is a new device from the control panel.
5. DOWNLOAD
- 85 -
5.3.3 Windows Driver Removal
How to remove driver information registered on Registry :Use lg_02Cusb.sys on this document for example.
1) Let the Registry window pop on with regedt32 keyword input.
Figure. 5-18
5. DOWNLOAD
- 86 -
2) Delete the contents in the 3 folders within the square box from the picture2.
Figure. 5-19
3) Picture3 shows the contents to be deleted from the folders. Refer to the Vid and Pid in order todelete the folders relative to the device. Vid is Vendor ID and Pid is Product ID. Only administratoris authorized to edit registry in Windows 2000. If you see the message which tells no authority toyou, then click Security (blue colored circle in the picture 3) from the menu and terminate it.
5. DOWNLOAD
- 87 -
Figure. 5-20
Figure. 5-21
5. DOWNLOAD
- 88 -
5 ) Delete LG03_usb folder from the folders in the Service. If you delete the contents within theServices, then you do not need to give any authority.
Figure. 5-22
6 ) Repeat from 3) to 5) for the (Controlset001, Controlser002, Currentcontrolset) folders.Warning! Do not really care whether there are all the folders we refer here or not.
7 ) Delete *.sys file relative to the USB in the WINNT\System and drivers folders.
8 ) Delete *.inf, .pnf files relative to the USB in the WINNT\inf folder. (Mostly oem.inf/pnf files)
5. DOWNLOAD
- 89 -
6. TROUBLE SHOOTINGFigure. 6-1 shows a measurement set-up.
Figure 6-1. Measurement set-up
6. TROUBLE SHOOTING
- 90 -
TOP & BOTTOM
Fig 6-2
Fig 6-3
6. TROUBLE SHOOTING
SW101
N101
FL103
U102
D101
FL101
U105
U101
FL101
FL104
FL105
6.1 Rx Trouble (EGSM)
- 91 -
6. TROUBLE SHOOTING
Check FL105 or Peripheral circuit
FL103 pin 2 RF signal is over -63dBm
Check FL103 or Peripheral circuit
FL105 pin 4, 6 RF signalis over -66dBm
FL101 pin 3 LO signalis over -23dBm
FL102 pin 5, 7 LO signalis over -26dBm
Check FL101 or Peripheral circuit
Check FL102 or Peripheral circuit
Rework Calibration(Over G_MAGIC 170)
Sector Power -85dBmU105 18, 19, 20, 21
I/Q signal is over 60mVCheck U105
NO
NO
NO
NO
NO
NO
(High Frequency Probe)
@ 947.4MHz
YES
YES
YES
YES
@ 947.4MHz
@ 1854.8MHz
YES
R501, R502, R505, R506I/Q signal is over 60mV
Check R501, R502, R505, R506or Peripheral circuit
(Oscilloscope)
@ 1854.8MHz
Set up Test with CalMon(62CH, Sector Power-60dB, AGC 24dB
FL103 : Antenna S/W FL105 : Rx SAW Filter
FL102 : BalunFL101 : Dual VCO
U105 : RF Main Chip
- 92 -
6.2 Rx Trouble (DCS)
6. TROUBLE SHOOTING
FL103 pin 6 RF signalis over -63dBm
FL104 pin 4, 6 RF signalis over -63dBm
FL101 pin 4 LO signalis over -23dBm
FL102 pin 5, 7 LO signalis over -26dBm
Check FL103 or Peripheral circuit
Check FL104 or Peripheral circuit
Check FL101 or Peripheral circuit
Check FL102 or Peripheral circuit
FL102
Rework Calibration(Over G_MAGIC 170)
Sector Power -85dBmU105 pin 18, 19, 20, 21I/Q signal is over 60mV
Check U105
NO
NO
NO
NO
(High Frequency Probe)
@ 1842.8MHz
YES
YES
NO
YES
YES
@ 921.4MHz
YES
R501, R502, R505, R506I/Q signal is over 60mV
Check R501, R502, R505, R506or Peripheral circuit
NO
YES
(Oscilloscope)
@ 1842.8MHz
@ 921.4MHz
Setup Test with CalMon(700CH, Sector Power -60dBm, AGC 24dB)
FL103 : Antenna S/W FL105 : Rx SAW Filter
FL102 : BalunFL101 : Dual VCO
U105 : RF Main Chip
- 93 -
6.3 Tx Trouble
6. TROUBLE SHOOTING
Setup Test with CalMonGSM:1CH, DAC value 600
DCS:512CH, DAC value 700Power Level: GSM 5, DCS 0
Test DC Voltage : 4.0 V
Check Main VCO RF Signal (pin 35) of U105. Can you observe RF Signal?
(GSM : 1319.2MHz, DCS : 1294.2MHz)
Check the voltage level of U105 (pin59) and FL101 (pin 9). Is it similar to
Fig.(GSM), Fig.(DCS)?
Check Aux VCO RF Signal (pin 23 or 24) of U105. Can you observe RF
Signal(GSM : 858, DCS: 832MHz)?
Check theTx IQ Signal levelof U105 (pin18~21) (R501,502,505,506).
Is it the same as Fig 7-15.
YES
NO
NO
NO
NO
Check all VCC level of U105Are they all O.K?
Check or change U105 andperipheral circuit between U105
(pin 59) and FL101 (pin 9)
Check or change U105, D102 andperipheral circuit
Check or change U105, D103 andperipheral circuit
Check or change U501 andperipheral circuit
Check or change U503 or U501and peripheral circuit
YES
NO
Check CLK, DATA, EN(pin 11, 12, 13) ofU105 Are the signals similar to Fig 7-13.
NO
NO
YES
YES
YES
YES
YES
1
TXRXSWpin 12
HBSWpin 11 High
LowLow
Low
GSM DCSTruth Table
LBSWpin 10 Low High
U503 : CALYPSO (BB Digital Main Chip)
U501 : NAUSICA_CS (BB Analog Main Chip)U101 : PAM (PF08122B)
U105 : RF Main Chip (TRF6150)FL101 : Dual VCO (ENFVF382S18)FL103 : Antenna S/W (SHS-M090B)
N101 : Directional coupler (LCD15D190A0007A)
D101 : Shottky Diode (BAT 15-05W)
D103 : Dual VaractorDiode (SMV1233-074)
D102 : Varactor Diode (HVC369B)
Check the switch pins of FL101pin(10, 11, 12). Are they the same as the
truth table?
Check or change U503 andperipheral circuit
Check or change U105(pin1, 2, 64)
- 94 -
6. TROUBLE SHOOTING
Is the amplified RF signal of U101(GSM:pin4, DCS:pin5) over 27dBm?
Is the input power of FL103(GSM:pin10, DCS:pin8) over 25dBm?
Is the output voltage level of(pin 48) over 1.5V?
Is the PA_ON signal level of U105( pin 9) high( about 2.8V)?
ChangeU105
NO
Is the PA_Level signal voltage of U105(pin 8) over 1.2V (GSM), 1.5V (DCS) ?
YES
NO
YES
Check or change peripheral circuitbetween output pins of FL101 and
input pins of U101
NO
Is the input voltage level of U101(pin 2) over 1.5V?
YES
YES
NO
NO
Is the Modulated RF signal of FL101(GSM:pin1, DCS pin6) over 3dBm? (GSM
890.2MHz, DCS 1710.2MHz)
Is the Modulated RF signal of U101(GSM:pin1, DCS pin8) over -2dBm? (GSM
890.2MHz, DCS 1710.2MHz)
YES
NO
YES
1
YES
NO
YES
NO
Check or change FL101 andperipheral circuit
Check calibrationcalibration
change FL103
Check or changeD101 and
peripheral circuit.
ChangeU503
ChangeU501
ChangeU101
Check or change peripheralcircuit between U105 (pin 48)
and U101(pin 2)
- 95 -
6.4 Voice Function Trouble
6. TROUBLE SHOOTING
Yes
Connect the phone to networkEquipment and setup call.
Setup 1KHz tone out.
Yes
Yes
No
No
No
START
Does sine wave apperat C523?
Does sine wave apperat number 3 pin in key B'd CN2
Receiver SoderingOK?
Change the FPCB
Change the Main B'D
Change the Key B'D
Resoldering Receiver
A. Receiver
B. Speaker
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Connect the phone to networkEquipment and setup call.
Setup 1KHz tone out.
START
Does sine wave apperat R814?
Does sine wave apperat C850?
Does sine wave apperat number 4 pin in key B'd CN2
Receiver SoderingOK?
Change the FPCB
Change the Main Board
Change the Key B'd
Change the Key Board
Resoldering or Change U810
U809Regulator output=3.0volt?
Resoldering
- 96 -
C. Microphone
6. TROUBLE SHOOTING
Yes
Yes
Yes
Connect the phone to networkand setup call.
Check the MIC bias levelat pad of MIC+
Cheak the signal level at C809, C815 after putting
audio signal in MIC
Yes
Yes
Yes
No
No
START
Is the level of MIC+ =2.0V,MIC- =0.3v ?
A fwe hundred of mVof sivgnal are measured?
Change the MIC
Rwsoldering of R815, R849, R848
Resoldering of C809, C814, C817 and Reass the phone
- 97 -
6.5 Display Function Trouble
A. LCD
6. TROUBLE SHOOTING
Is power supplied tocircuit ?
START
Connection OK ?
Check the connection betweenLCD module and FPCb.
Check the connection betweenFPCB and main board
Check the data line at theLCD connector
Change LCD module
Does data appearon the data line ?
Yes
Yes
Yes
Refer to power-on trouble
Reconnect FPCBor LCD module
ResolderingLCD connector
No
No
No
B. Camera
- 98 -
6. TROUBLE SHOOTING
START
Check the signal lines atthe Camera connector
No
No
Coonection OK ? Reconnect camera module
Yes
Yes
Do signals appearon the data line ?
Change Camera module
Any Other Problem
Check the connection ofthe Camera module and
Main Board
- 99 -
6.6 Other Function Trouble
A. Vibrator
6. TROUBLE SHOOTING
Yes
Yes
Yes
No
No
No
START
Enter into UI menu andSelect the vibrator
Does high level state appearat number 3 pin of Q805?
Does high level state appearat number 30 pin in Key B'd
Vibrator solderingOK?
Change the FPCB
Change the key board
Resolding R827, R829, R826, R825and change Q804, Q805
Resolding vibrator
- 100 -
B. Charger
6. TROUBLE SHOOTING
START
Is the TA voltage 5.2V ?
No
No
Check the pin and batteryconnect terminals of
I/O connector
Connection OK ? Change I/O connector
Yes
Yes
No
No
Change TA
Is it chargingproperly after
changing Q501 ?
Yes
Yes
End
Is it chargingproperly after
changing D501 ?End
Change the board
C. USB
- 101 -
6. TROUBLE SHOOTING
START(Measure during the state of USB madule running)
Input power(U801, pin1) is 5V?
Output power(U810, pin5) is 3.3V?
USB pullup(U811, pin5) is 3.3V?
High level on USB detect(Q809, pin4)?
Change the board
Change U 810
Check host USB port or USB cable
Change Q 809
Resoldering R 877
Yes
Yes
Yes
Yes
No
No
No
No
- 102 -
7. STAND ALONE TEST AND TEST POINTS
7.1 Testing Set-up
7.1.1 Received RF Level and Checks
This section shows the typical RF levels expected throughout the receiver path. A block diagramshowing the locations of the RF measurement points and levels is shown in Figure. 7-3.
Receiver Testing Set-upTo check the receiver the following conditions have to be set:
1. On a signal generator or a GSM/DCS test box, output a CW signal of amplitude = -60 dBm ateither: 947.4 MHz (CH62) when testing the GSM RX path or 1842. 6 MHz (CH699) whentesting the DCS RX path.
2. Set the DC power supply to 4.0 V.
Note: All RF values shown are only intended as a guide figure and may differ from readings takenwith other test equipment and leads. Lead and connector losses should always be taken intoaccount when performing such RF measurements.
Testing ReceiverUsing a suitable high frequency probe measure the RF levels at the relevant points shown in Figure.7-3 and compares your measurements with those shown in the diagram. If there are any majordifference between the readings taken and those indicated then further investigation of that particularpoint will be required. It will also be necessary to ensure that all the following power supplies andsignals are present which control this part of the receiver circuit:
1. The Control Signal of Antenna switch (see Figure 7-11 )2. Vreg 1,2,3 (see Figure 7-7 )3. 2V85_VCTCXO (see Figure 7-8)4. 13MHz(see Figure 7-12)5. CLK, DATA, EN (see Figure 7-13)6. RX IP, IN, QP, QN (see Figure 7-16,19)7. Vtune(see Figure 7-17,18)
7. STAND ALONE TEST AND TEST POINTS
- 103 -
7.1.2 Transmitted RF Level and Checks
This section shows the typical RF levels expected throughout the transmitter path. A block diagramshowing the locations of the RF measurement points and levels is shown in Figure 7-5.
Transmitter Testing Set-upTo check the transmitter the following conditions have to be set:
1. Configure the testing equipments as Figure equipment setup.
2. Set the GSM/DCS test equipment to be stand-alone mode (asynchronous mode).
3. Set the BCH and TCH ARFCN ‘62’ for EGSM900 or ‘700’ for DCS1800 on GSM/DCS testequipment.
4. Set the DC power supply 4.0volts.
5. Initialize target on service software.
6. Set TCH and BCH value to be same with GSM/DCS test equipment on service software.
7. Select GSM or DCS mode on service software.
8. Set DAC ‘600’ for EGSM900 or ‘700’ for DCS1800 on service software.
9. Click Test.
1. Set the DC Power supply to 4.0 V.
2. Power up the GSM/DCS test set and then establishing a call with an attached mobile on activemode.
3. Select Channel, TX Level and Input Level according to which parameter is required.
Note: All RF values shown are only intended as a guide figure and may differ from readings takenwith other test equipment and leads. Lead and connector losses should always be taken intoaccount when performing such RF measurements.
Testing TransmitterUsing a suitable high frequency probe measure the RF levels at the relevant points shown in Fig. 7-5and compare your measurements with those shown in the diagram. If there are any major differencebetween the readings taken and those indicated then further investigation of that particular point willbe required. It will also be necessary to ensure that all the following power supplies and signals arepresent which control this part of the transmitter circuit:
1. The Control Signal of Antenna Switch(see Figure. 7-9, 10)
2. Vreg 1,2,3 (see Figure. 7-7)
3. 2V85_VTCXO (see Figure. 7-8)
4. 13 MHz (see Figure. 7-12)
5. PA_ON, PA_LEVEL, Vapc (see Figure. 7-14)
6. TX IP, IN, QP, QN (see Figure. 7-15)
7. STAND ALONE TEST AND TEST POINTS
- 104 -
7.2 Testing Points
7.2.1 RF components
7.2.1.1 TOP Side
Figure 7-1-1. RF components (Top side)
7. STAND ALONE TEST AND TEST POINTS
FL102 FL104
FL105D102D103U105
- 105 -
7.2.1.2 Bottom Side
Figure 7-1-2. RF components (Bottom side)
7. STAND ALONE TEST AND TEST POINTS
SW101
FL103 U102 D101 U104 U103 X101
N101 U101 FL101
- 106 -
Table 7-1. RF components
7.2.2 Test point of RX Levels
Figure 7-2. Test point of RX Levels
7. STAND ALONE TEST AND TEST POINTS
Reference Reference
U105 RF main chipset FL101 Dual RF VCO
FL103 Antenna Switch X101 VCTCXO
U101 PAM FL102 Balun
N101 Coupler FL105 GSM RF SAW Filter
U102 NOR Gate FL104 DCS RF SAW Filter
U103 Inverter SW101 Mobile Switch
U104 LDO D101 Dual Schottky Diode
D102 Varactor Diode D103 Varactor Diode
5
6
4
3
1
2
- 107 -
7. STAND ALONE TEST AND TEST POINTS
CLA
RA
CLA
RA
CLA
RA
CLA
RA
TR
F61
50T
RF
6150
TR
F61
50T
RF
6150
LF
EG
SM
: 92
5~96
0 M
Hz
EG
SM
: 92
5~96
0 M
Hz
EG
SM
: 92
5~96
0 M
Hz
EG
SM
: 92
5~96
0 M
Hz
DC
S :
1805
~18
80 M
Hz
DC
S :
1805
~18
80 M
Hz
DC
S :
1805
~18
80 M
Hz
DC
S :
1805
~18
80 M
Hz
IN INININ IP IPIPIP QN
QN
QN
QN
QP
QP
QP
QP
/ 2 / 2/ 2
/ 2
90 9090
90o ooo
90 9090
90o ooo
SA
ES
D94
2MC
L0T
00S
AE
SD
942M
CL0
T00
SA
ES
D94
2MC
L0T
00S
AE
SD
942M
CL0
T00
HG
42U
P3
HG
42U
P3
HG
42U
P3
HG
42U
P3
DC
Sln
anD
CS
lnan
DC
Sln
anD
CS
lnan
DC
Sln
apD
CS
lnap
DC
Sln
apD
CS
lnap
GS
Mln
anG
SM
lnan
GS
Mln
anG
SM
lnan
GS
Mln
apG
SM
lnap
GS
Mln
apG
SM
lnap
Bal
unB
alun
Bal
unB
alun
RX
LOP
RX
LOP
RX
LOP
RX
LOP
RX
LON
RX
LON
RX
LON
RX
LON
HB
RX
HB
RX
HB
RX
HB
RX
FL1
02F
L102
FL1
02F
L102
TX
RX
cpT
XR
Xcp
TX
RX
cpT
XR
Xcp H
Bsw
itch
HB
switc
hH
Bsw
itch
HB
switc
hLB
switc
hLB
switc
hLB
switc
hLB
switc
hT
XR
Xsw
itch
TX
RX
switc
hT
XR
Xsw
itch
TX
RX
switc
h
CR
FC
RF
CR
FC
RF
AF
CA
FC
AF
CA
FC
CLK
13M
CLK
13M
CLK
13M
CLK
13M
:5/1
0:5
/10
:5/1
0:5
/10
:2 :2:2:2
7bits
7bits
7bits
7bits A AAA
4bits
4bits
4bits
4bits B BBB
16/1
716
/17
16/1
716
/17
P/P
+1
P/P
+1
P/P
+1
P/P
+1
4bits
4bits
4bits
4bits
FN
FNFN
FN
VR
4in
VR
4in
VR
4in
VR
4in
x 2
x 2
x 2
x 2
Ser
ial C
ontr
ol
Ser
ial C
ontr
ol
Ser
ial C
ontr
ol
Ser
ial C
ontr
ol
Logi
c &
Lo
gic
&
Logi
c &
Lo
gic
&
Res
iste
rsR
esis
ters
Res
iste
rsR
esis
ters
CLK
CLK
CLK
CLK
EN
EN
EN
EN
DA
TA
DA
TA
DA
TA
DA
TA
R3
R3
R3
R3
MA
INsp
up2
MA
INsp
up2
MA
INsp
up2
MA
INsp
up2
R 2
R 2
R 2
R 2
VC
1V
C1
VC
1V
C1
VC
2V
C2
VC
2V
C2
SH
S-M
090B
SH
S-M
090B
SH
S-M
090B
SH
S-M
090B
RX
mix
Qp
RX
mix
Qp
RX
mix
Qp
RX
mix
Qp
RX
mix
Qn
RX
mix
Qn
RX
mix
Qn
RX
mix
Qn
RX
mix
IpR
Xm
ixIp
RX
mix
IpR
Xm
ixIp
RX
mix
InR
Xm
ixIn
RX
mix
InR
Xm
ixIn
TE
ST
vco
TE
ST
vco
TE
ST
vco
TE
ST
vco
DE
CR
Xm
ixD
EC
RX
mix
DE
CR
Xm
ixD
EC
RX
mix
902.
5~94
0 M
Hz
902.
5~94
0 M
Hz
902.
5~94
0 M
Hz
902.
5~94
0 M
Hz
1850
~19
20 M
Hz
1850
~19
20 M
Hz
1850
~19
20 M
Hz
1850
~19
20 M
Hz
BIA
Sre
fB
IAS
ref
BIA
Sre
fB
IAS
ref
VC
1V
C1
VC
1V
C1
VC
2V
C2
VC
2V
C2
TX
TXTX
TX RX
RX
RX
RX
TX
TXTX
TX
RX
RX
RX
RX
GS
MG
SM
GS
MG
SM
DC
SD
CS
DC
SD
CS
2.6V
2.6V
2.6V
2.6V
2.6V
2.6V
2.6V
2.6V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
0.0V
RE
SE
TZ
RE
SE
TZ
RE
SE
TZ
RE
SE
TZ
2.6/
1.3M
HZ
2.6/
1.3M
HZ
2.6/
1.3M
HZ
2.6/
1.3M
HZ
RF
out_
rx =
(P
*A +
B +
FN
/13)
*1.3
MH
zR
Fou
t_rx
= (
P*A
+ B
+ F
N/1
3)*1
.3M
Hz
RF
out_
rx =
(P
*A +
B +
FN
/13)
*1.3
MH
zR
Fou
t_rx
= (
P*A
+ B
+ F
N/1
3)*1
.3M
Hz
TX
TXTX
TX RX
RX
RX
RX
HB
switc
hH
Bsw
itch
HB
switc
hH
Bsw
itch
LBsw
itch
LBsw
itch
LBsw
itch
LBsw
itch
TX
RX
switc
hT
XR
Xsw
itch
TX
RX
switc
hT
XR
Xsw
itch
Vre
g3V
reg3
Vre
g3V
reg3
Vre
g3V
reg3
Vre
g3V
reg3
LBR
XLB
RX
LBR
XLB
RX
- 62
dBm
- 63
dBm
1 111-
64dB
m
- 66
dBm
2 222
3 3334 444
- 10
dBm
- 13
dBm
6 666 5 555
Fig
ure
7-3
. Rec
evie
r R
E L
evel
s
GS
M:C
H.6
2, -
60d
Bm
DC
S:C
H.6
99, -
60d
Bm
- 108 -
7.2.3 Test point of TX Levels
Figure 7-4. Test point of TX Levels
7. STAND ALONE TEST AND TEST POINTS
5 4
3
910
1,7
2,8
6
12
11
13
- 109 -
7. STAND ALONE TEST AND TEST POINTS
CLA
RA
TR
F61
50
LFP
FD
I N I P Q N Q P
HB
RX
TX
RX
cp
OM
IXrf
90o
R 3
MA
INsp
up2
R 2
VC 1 VC 2
EG
SM
DC
S
416-
429M
Hz
Del
ay 6bits A
3bits B
8/9
P/P
+1
LF
TA
NK
/2
MA
INcp
MA
INsp
up1
LFC
R F:5
/10
:2
T X R X
7bits A
4bits B
16/1
7P
/P+
14b
itsF
N
1294
~13
56 M
Hz
TA
NK
MA
INvc
o
832~
858
MH
z
AP
C
AT
T1
AT
T2
LDC
15D
190A
0007
A
BA
T15
-099
PF
0812
2B
1-3
dBm
2dB
m
GS
M :
975C
H (
1.0V
) ~
124
Ch
(1.5
V)
DC
S :
512C
H (
0.6V
) ~
885
Ch
(1.1
V)
GS
M :
Pw
r Lv
l 5, C
h.62
, 32d
Bm
DC
S :
Pw
r Lv
l 0, C
h.70
0, 2
9dB
m
92d
Bm
36d
Bm
-2dB
m
40d
Bm
32dB
m
534
dBm
633
.5dB
m
11
7 82
10
31.5
dBm
12
GS
M :
15dB
mD
CS
: 18
dBm
13
GS
M :
32dB
mD
CS
: 29
dBm
BA
T15
-05W
Fig
ure
7-5
. Tra
nsm
itte
r R
F L
evel
- 110 -
7.2.4 Control signal test points
Figure 7-6. Control signal test points
7. STAND ALONE TEST AND TEST POINTS
VC1VC2
Vtune
13MHz
LB_SW
HB_SW
Vapc
I/Q
TXRX_SW
PA_LEVEL
PA_ON
CLK,DATA,EN
Regulator_2.85V
- 111 -
Figure 7-7. 2V85_Vreg 1, 2, 3 Output
Figure 7-8. 2V85_VCTCXO Supply Voltage
7. STAND ALONE TEST AND TEST POINTS
- 112 -
Figure 7-9. Antenna S/W control voltage in EGSM_TX
Figure 7-10. Antenna S/W control voltage in DCS_TX
7. STAND ALONE TEST AND TEST POINTS
- 113 -
Figure 7-11. Antenna S/W control voltage in RX
Figure 7-12. 13MHz Clock
7. STAND ALONE TEST AND TEST POINTS
- 114 -
Figure 7-13. CLK, DATA, EN
Figure 7-14. PA_ON, PA_LEVEL, VAPC (GSM Tx Level=7)
7. STAND ALONE TEST AND TEST POINTS
- 115 -
Figure 7-15. Tx I / Q Signal
Figure 7-16. Rx I / Q Signal
7. STAND ALONE TEST AND TEST POINTS
- 116 -
Figure 7-17. PA_ON, Vtune (U105pin 9, GSM 1CH)
Figure 7-18. PA_ON, Vtune (U105 pin 9, DCS 512CH)
7. STAND ALONE TEST AND TEST POINTS
- 117 -
Figure 7-19. RX I/Q Signal (Extended)
7. STAND ALONE TEST AND TEST POINTS
- 118 -
8. DiSASSEMBLY INSTRUCTION
8-1 Disassembly Instruction1. Remove the battery cover- push lockers at both end sides and slide down the battery cover.
Figure 8-1. Removing Battery Cover
2. Remove the battery pack and screws.
Figure 8-2. Removing Screws
8. DiSASSEMBLY INSTRUCTION
1
2
- 119 -
3. Detach the rear cover-use a thin plastic sheet to open the gap between front and rear covers, then detach them carefullywith both hands.
Figure 8-3. Disassembling Rear Cover
4. Remove the SIM connector and bracket, and detach the camera FPCB from the main PCB
Figure 8-3. Detaching SIM Connector and FPCB
8. DiSASSEMBLY INSTRUCTION
21
1
2
3
- 120 -
5. First, remove the main PCB and lift the camera out to detach the frame shield.Then, detach FPCB as shown in the Fig. 8-5.
Figure 8-5. Detaching Main PCB
8. DiSASSEMBLY INSTRUCTION
3
1 2
- 121 -
6. Detach the keypad and mike.
Figure 8-6. Disassembling Keypad and Mike
7. Remove the antenna and window IrDA, and push away the antenna-bushing using a sharp awl.
Figure 8-7. Removing Antenna and Antenna-bushing.
8. DiSASSEMBLY INSTRUCTION
1
2
3
- 122 -
8. Use a pin to remove Cap Screw and remove screws.
Figure8-8. Removing Cap Screws
9. Use a thin plastic sheet to open the gap between the cover folder upper and cover folder lower,then detach the cover folder upper carefully with both hands
Figure8-9. Detaching Upper Cover
8. DiSASSEMBLY INSTRUCTION
21
- 123 -
10. Use a sharp awl to remove the hinge.
Figure8-10. Removing Hinge
11. Detach the front cover from the lower cover.
Figure 8-11. Detaching Front Cover
8. DiSASSEMBLY INSTRUCTION
- 124 -
12. Remove FPCB from the slit of the lower cover.
Figure 8-12. Removing FPCB
13. Detach LCD very carefully and remove FPCB from the connector of LCD Module.
Figure 8-13. Detaching LCD and FPCB
*Note:When you change FPCB, remove 'tape' and 'solder' firstly.
8. DiSASSEMBLY INSTRUCTION
- 125 -
8-2. Assembly Note14. First, insert the camera into the main FPCB before assembling them.
Figure 8-14. Assembling Camera Main PCB
15. When placing the main PCB on the frame shield, push the center of it not to override the topbutton.
Figure 8-15. Assembling Main PCB
8. DiSASSEMBLY INSTRUCTION
3
2
1
- 127 -
9. BLOCK DIAGRAM
9.1 Main Board
9.1.1 Baseband Blockdiagram (Memory & Audio path)
Figure 9-1-1. Main Block diagram.
9. BLOCK DIAGRAM
- 128 -
9.1.2 Baseband Blockdiagram (UART path)
Figure 9-1-2. Main Block diagram.
9. BLOCK DIAGRAM
- 129 -
9.2 LCD Module
Figure 9-2. FPCB Block diagram.
9. BLOCK DIAGRAM
- 130 -
9.3 RF
Figure 8-3. RF Block diagram.
9. BLOCK DIAGRAM
- 131 -
9. CIRCUIT DIAGRAM
Main PCB Circuit (1/5)
Date Changed:
DOC CTRL CHK:
11
D
Page:
2
H
E
QA CHK:
1
H
10
Changed by:
F
Size:R&D CHK:
7 10
9
A
Drawn by:
Drawing Number:
5
8
1
Engineer:
7
12
A
COMPANY NAME
MFG ENGR CHK:
C
G
5
D
3 114 86
City
3
Time Changed:
B
TITLE:
F
E
B
12
9
G
6
Addressmentor
JS Lee
5:38:35 pmTuesday, December 11, 2001mentor 2
CALYPSO_IOTA12 1 8 A
A2
REV:
42
C
C50
227
0p
C514220n
R55
6
VRIO1uC509
R507 0
1SS388
TP525
D515
R542 0
R52
3
C5290.1u
TP505
0FC541
3G
10K
R509
TP526
0.1uC525
0
R54
7
100K
R51
3
D3
VR3OUTH10
VR
EF
F4
VS1B1A1
VS2
VBACKUPVBAT
E5
K2VCC11VCC12
K3D2
VCC2VCC3
G9
VCHGE4
H6VCK
K7VDR
G6VDXVFS
G7
VR1BOUTC1
H1VR1OUT
D1VR2BOUT
E2VR2IN
E1VR2OUT
VR2SEL
TDO
TD
RJ4 K
4T
EN
TEST1C8B8
TEST2A9
TEST3TEST4
B9
TE
ST
RE
SE
TZ
F2
A8TMS
B6TSCXMTSCYM
A6
K6UDRUDX
J6
UENF5
C3UPR
A3VAUX
J3
ON_OFF
F1
OS
CA
SB
10P
WO
NR
EF
GN
DF
3
RESPWRONZF6
A10
RP
WO
N
D7RTC_ALARM
SCLK3C4 B4
SCLK5
B2SDIO3 SDIO5
D4
SRST3B3 D5
SRST5
SVDDA2
TCKB7A7
TDI
C7
GR
ND
2
G10
GR
ND
3
IBIA
SG
1
ICTLE3
INT1F7
INT2H4
C5LCDSYNC
K9MICBIAS
MICINJ8
MICIPK8
NC1G2G3
NC2G4
NC3NC4
H2
NC5H3
NC6J2
D10
E9
BDRH5
K5BDXBFSK
J5
G5BFSR
C10BULIM
C9BULIP
BULQMD9
BULQPD8
BUZZOPK10
CK
13M
A4
F10DAC
EARNH8H9
EARP
FDBKJ1
GR
ND
1K
1
C2
ADIN1B5A5
ADIN2E6
ADIN3ADIN4_TSCXP
D6
ADIN5_TSCYPC6
F8AFC
J7AGNDA1
F9APC
G8AUXGND
H7AUXI
AUXONJ10J9
AUXOP
BDLIME8E7
BDLIP
BDLQME10
BDLQP
PTWLR3012BGGM
U501
2VINVOUT
3
VSS1
R543
S-817A18ANB-CUH-T2U505
NC4
TP502
UPR
36R501
10pC522
0.1uC520
10pC527
1000pC528
0
R549
0.1uC503
1SS
388
D55
1
VRRTC
VRIO
R526 0
R506 36
C515
VR1B
15uF
C599
TP524
VRRTC
0.1u
C5040.1u
200K
R52
7
R52
110
K
R52
012
0K
R54
8
100K
C51310u
R537 100K
VRIO
0R525
VRMEM
R502 36
TP503
10KR530 C506 220n
3G
C5420F
SP
8
0F
TP521
C906
100K
R55
0
TP522
0R541
10p
20KR528
0
R561
C521
10K
R599
R533
R546 270
SP
6
C518
BA
T50
1
6789
0.1u
CN803
G80001
10
2345
R51
6
SP
9
R508
R51
5
0
0R
517
R536
1SS388D512
R535
10K
R50
4
0.033u
9
113B1
3B210
4A12
4B114
134B2
8GND
S1
VCC16
_OE15
C516
SN74CBTLV3257DGVRU502
41A
1B12
31B2
72A
52B1
62B2
3A
62K
R59
8
0.2
R512
VBATVBAT_2
CR
S08
D50
1
0.1uC526
SP
7
TP
504
VBACKUP
0
R552
VRABB
20K R511
VRIO
UPR
R52
4
10K
36R505
Q50
1
D1
1
D2
2 3D
3D
46 7
D5 D6
8
G4
5S
VRIO
NT
HS
5441
T1
C51110u 10u
VBACKUP
VRDBB
C512
10pC517
NL27WZ126USU504
A12
5A2GND
4
OE11
7OE2
8VCC
6Y1Y2
3
UPR
C51
90.
1u
R54
5
R562
VBAT_2
100p
C52
3
220K
R51
0
10uC510
VRMEM
1SS
388
D51
0
C505
R50
310
K
18p
VRIO
VRIO
R569
1K
100KR544
PT
501
TP501
R531
32.7
68K
Hz X
501
crys
tal
12 3
4
VBAT_RF
R51
8
C5240.1u
TP523
C508
1MR519
1u
10K
R56
3
NC7SB3157P6XU555
4A3 B0
1 B12 GND
6S5VCC
N8
VS
S6
VS
S7
P10
P13
VS
S8
G14
VS
S9
E12
VS
SA
NG
A14
VS
SO
VS
SP
LL
E14
C14
VS
SR
TC
VD
DS
_MIF
2G
1B
6V
DD
S_M
IF3
VD
DS
_MIF
4A
4
D13
VD
DS
_RT
C
VD
D_P
LL
F11
VDRN13P14
VDX
VSFRXM13
VS
S1
B1
A10
VS
S10
VS
S11
A7
A2
VS
S12
F1
VS
S2
VS
S3
K1
P2
VS
S4
VS
S5
P4
C7
TX
IR_I
RD
A
C8
TX
_IR
DA
B9
TX
_MO
DE
M
N12VCLKRX
E1
VD
D1
VD
D2
M1
P7
VD
D3
N14
VD
D4
VD
D5
B12 A5
VD
D6
E11
VD
DA
NG
D14
VD
DR
TC
N5
VD
DS
_1_1
VD
DS
_1_2
L14
VD
DS
_2A
11D1
VD
DS
_MIF
1
J13TSPACT11
TSPACT2L12L13
TSPACT3TSPACT4
J10K11
TSPACT5TSPACT6
K13K12
TSPACT7TSPACT8
K14J11
TSPACT9
J14TSPCLKX
H10TSPDITSPDO
H11
TSPEN0H13H12
TSPEN1TSPEN2
H14G12
TSPEN3
SD
IM
9S
DO
K8
B8
SD
_IR
DA
SIM_CDG11
F13SIM_CLK
SIM_IOG13
SIM_PWRCTRLF14
G10SIM_RST
B10TCK
TC
SO
EN
A12
D10TDI
TDOC10
TMSE9
TSPACT0M12M14
TSPACT1
J12TSPACT10
NF
WE
E3
N1NIBOOT
NR
ES
ET
_OU
TN
2
NS
CS
0L
9N
9N
SC
S1
F10ON_OFF
OS
C32
K_I
NC
13
B13
OS
C32
K_O
UT
RESPWRONZD12
A13
RF
EN
B2
RN
W
E8
RT
S_M
OD
EM
RX
IR_I
RD
AA
8
RX
_IR
DA
D8
RX
_MO
DE
MA
9
P9
SC
LK
MCUDIN7M7
MCUDOMCUEN0
M8P8
MCUEN1MCUEN2
L8
NB
HE
F5
E4
NB
LE
NBSCAND11
NCC11
NC
S0
C2
C3
NC
S1
NC
S2
C1
D3
NC
S3
B11NEMU0NEMU1
E10
E2
NF
OE
B14IT_WAKEUP
KB
C0
N4
K5
KB
C1
L5
KB
C2
P5
KB
C3
KB
C4
M5
K6
KB
R0
M6
KB
R1
P6
KB
R2
N6
KB
R3
L6
KB
R4
L7
LT
N10
MC
SI_
CL
KM
CS
I_F
SY
NC
HK
9
MC
SI_
RX
DM
10L
10M
CS
I_T
XD
D6DATA3DATA4
A6DATA5
C6E6
DATA6DATA7
C5B5
DATA8DATA9
D5
D9
DS
R_M
OD
EM
EXT_FIQP1
EXT_IRQM3
F4
FD
P
M2
IDD
Q
IO0
N3
P3
IO1
IO2
L4
M4
IO3
M11BOX
K7
BU
F12
CL
K13
M_O
UT
CL
K32
K_O
UT
C12
CL
KT
CX
OE
13
CS
4D
2
CT
S_M
OD
EM
C9
DATA0B7D7
DATA1
E5DATA10DATA11
B4C4
DATA12
D4DATA13DATA14
A3B3
DATA15
DATA2E7
ADD19L1
G5ADD2
L2ADD20ADD21
L3
ADD3G4G2
ADD4ADD5
G3ADD6
H1H3
ADD7
H2ADD8ADD9
H4
P11
BC
LK
RB
CL
KX
N11
K10BDR
BFSRL11
P12BFSX
XF741979BGGHU503
F3ADD0ADD1
F2
ADD10H5J1
ADD11
J2ADD12ADD13
J3J4
ADD14ADD15
K3K2
ADD16ADD17
K4J5
ADD18
VRRTC
D511
1SS388
270p
C50
1
R53
8
120K
0.022u
VRMEM
DAI_TX
CHARGER
BAT_SENSE
HEL_UART_CNTL_RX
ONNOFF_BUF
ONNOFF
ONNOFF_TO_BUF
CCK32K
CCK32K_CUT
C507
HEL_MCSI_DIHEL_MCSI_DO
MMAUDIO_CAL_HEL
PC_UART_RTS
PA_ON
PA_LEVEL
TSPEN
TSPCLKTSPDATA
IP
QP
IM
QM
DAI_RX
MMAUDIO_CAL_HEL
MOTOR_EN
HS_HF_SW
CAL_TDI
PWL_MAIN_LCD_BL
_HEL_SYS_RST
HEL_UART_CNTL_TX
HEL_UART_DATA_RTSHEL_UART_DATA_CTS
HEL_UART_DATA_TXHEL_UART_DATA_RX
RESETCL
CAL_TX_MBOX
DAI_SYNC
DTC_SENSE
AFCCAL_UART_DCDCAL_UART_DSR
DAI_CLK
TCXO_EN
CAL_TMS
HEL_MCSI_CLK
_RPWON
_CAL_WR
EAR_PIECEM
CAL_TDO
PC_UART_CTS
PC_UART_TXPC_UART_RX
EAR_SPEAKER_SW
HEL_MCSI_FS
CAL_TCK
MICPMICNMICBIAS
AUXI
AUXOPAUXON
RADIO_TEMP
CCK32KCCK13M
_END_ONOFF
CAL_NTRST
CAL_DATA(2)
CAL_DATA(15)
CAL_DATA(14)
CAL_DATA(13)
CAL_DATA(12)
CAL_DATA(11)
CAL_DATA(10)
CAL_DATA(1)
CAL_DATA(0)
CAL_ADD(22)
CAL_ADD(9)
CAL_ADD(8)
CAL_ADD(7)
CAL_ADD(6)
CAL_ADD(5)
CAL_ADD(4)
CAL_ADD(3)
CAL_ADD(21)
CAL_ADD(20)
CAL_ADD(2)
CAL_ADD(19)
CAL_ADD(18)
CAL_ADD(17)
CAL_ADD(16)
CAL_ADD(15)
CAL_ADD(14)
CAL_ADD(13)
CAL_ADD(12)
CAL_ADD(11)
CAL_ADD(10)
CAL_ADD(1)
EAR_PIECEP
CLK13M
CAL_DATA(0:15)
CAL_ADD(1:22)
HEL_TX_MBOX
_CAL_RD
_CAL_CS1
_CAL_CS0
_CAL_BLE
_CAL_BHE
_CAL_FDP
CAL_DATA(9)
CAL_DATA(8)
CAL_DATA(7)
CAL_DATA(6)
CAL_DATA(5)
CAL_DATA(4)
CAL_DATA(3)
9. CIRCUIT DIAGRAM
- 132 -
Main PCB Circuit (2/5)
9. CIRCUIT DIAGRAM
QA CHK:
63
QA CHK:
5
E
1
D
Address
G
Drawn by:
2
Date Changed:
A
4
B
A
4
Size:
5
F
G
102
2
A
H
B
Drawing Number:
1
D
MFG ENGR CHK:
9
G
10
TITLE:
Drawing Number:
111
G
4
Page:
5 11
G
C
E
D
A
8 98 96
F
1 3
11
5
D
6
2
B
TITLE:
D
E
121
9
7
F
Changed by:
H
Address
5
TITLE:
12
113
Engineer:Engineer:
Date Changed:
3
3
REV:
5
Date Changed: Time Changed:
3
Changed by:Changed by:
G
E
8
MFG ENGR CHK:
D
7
G
A
6 12
A
12
B
H
B
F
Page:
5
8
R&D CHK:
11
B
R&D CHK:
1
E
5
F
Drawing Number:QA CHK:
12
4
Engineer:
7
6
Size:
9
3
D
R&D CHK:
C
A
8
7
REV:
4 7 9
8
Time Changed:
6
Address
12114
COMPANY NAME
1
E
COMPANY NAME
10
H
B
DOC CTRL CHK:
2
Drawn by:
10
C
F
2
City
3
City
Page:
1211
E
1084
7
8
MFG ENGR CHK:
9
E
A
104 12
H
DOC CTRL CHK:
REV:
F
D
H
F
COMPANY NAMEDrawn by:
Size:
G
H
2
DOC CTRL CHK:
9
102
Time Changed:
6
B
10
97SMX
C
11
7
H
A2
12 1 8 A
mentor Monday, December 10, 2001 5:25:44 pm 0
A2
12 1 8 A
C CC
1 6 7
C
City
mentor Monday, December 10, 2001 5:25:44 pm
Y.J. SEOK
Y.J. SEOK
0 9
OMAP1509
A2
12 1 8 A
mentor Monday, December 10, 2001 5:25:44 pm 0
18pC908
C651
VBAT_2
10u R645
R62
0
100
12MHz
X601
100K
R68
9
4A3 B0
B112 GND
6S5VCC
R658 470
NC7SB3157P6XQ602
C905
TP
602
18p
HEL_IO_MEM_2.8V
R66
3
10K
0.1uC666
R619
10K
2.7K
R61
1
R68
1
10
R673 270
HEL_IO_MEM_2.8V
SP43
SP
42
R63
510
0K
270R668
18pC910
R616
34
C90918p
LN
J717
W80
RA
1
LD
601
12
LD
603
LN
J717
W80
RA
1
12
34
2
56
31
4
EMX1Q603
12
R614
C60110p
0.1uC653
C6160.1u0.1uC607
4.7
R627
10KR624
10
R68
2
100K
R62
9
R674 270
TP608
47pC674
470
R64
1
R62
8
R612
12
62
789
TP
607
4849
5
50515253545556575859
6
6061
33343536373839
4
4041424344454647
19
2
20212223242526272829
3
303132
1
101112131415161718
CN602
1
2
3
4
R60
1
56
SW601
R646 10K
100K
R64
7
TP
604
R623
20K
A32
12E
LH
U60
1
3G
ND
2O
UT
VD
D1
C61
4
HEL_IO_MEM_2.8V
C672
18p
0F
C612
TP
603
1u
R61
5
10K
VBAT
LCD_1.8V
20K
R625
SW602
1
2
3
4
VBAT_2HEL_IO_MEM_2.8V
R613
10K
R64
01K
10KR610
0.1uC602
R605
10K
C603
HEL_IO_MEM_2.8V
0.1u
TP666
Q666 B
C
E
R62
1
47K
DTC144EE
1uC606
R671 270
HEL_CORE_1.5V
2.7K
R66
1
C6100.1u
TP
606
R607 10K
SP
34
SP
32
SP
33
R68
0
R914 270
18p
TP667
C675
12
34
LN
J717
W80
RA
1
LD
602
C6520.1u
C6090.1u
D699
1SS388
R66
6
10K
R667 270
470
R64
2
270R665
U602 SC600BIMSTR
CF1+2 9
CF1-
10CF2+
CF2-7
6EN
4FID0
FID15
GND83
VIN
1VOUT
270R664
270R672
SP
35
47p
SP
38
C673
B1
VS
S7
B16
VS
S8
B18
VS
S9
WIR
E_N
SC
S0
N14
P15
WIR
E_N
SC
S3
WIR
E_S
CL
KV
19
U18
WIR
E_S
DI
WIR
E_S
DO
w21
VBAT
TP
601
VS
S18
U2
VS
S19
U20
VS
S2
A13
VS
S20
V12
V5
VS
S21
VS
S22
W10
W20
VS
S23
VS
S24
Y15
Y3
VS
S25
VS
S26
E2
VS
S27
F20
G1
VS
S28
A21
VS
S3
VS
S4
AA
1A
A21
VS
S5
AA
7V
SS
6
VD
DS
HV
5_2
E1
VD
DS
HV
5_3
H2
L1
VD
DS
HV
5_4
VD
DS
HV
5_5
P3
VD
DS
HV
5_6
R1
V2
VD
DS
HV
5_7
VD
DS
HV
6A
A11
A11
VS
S1
VS
S10
B2
VS
S11
B5
VS
S12
B7
J20
VS
S13
VS
S14
K2
K20
VS
S15
VS
S16
N1
VS
S17
R21
M2
VD
D8
P12
VD
D9
A15
VD
DS
HV
1_1
VD
DS
HV
1_2
A19
VD
DS
HV
1_3
E21
L21
VD
DS
HV
1_4
U21
VD
DS
HV
1_5
VD
DS
HV
1_6
Y16
AA
2V
DD
SH
V2
Y7
VD
DS
HV
3V
DD
SH
V4_
1A
1A
5V
DD
SH
V4_
2V
DD
SH
V4_
3A
7V
DD
SH
V4_
4B
10B
12V
DD
SH
V4_
5V
DD
SH
V5_
1C
2
TX1Y14
TX2V6
US
B_C
LK
OW
4R
8U
SB
_DM
US
B_D
PP
9V
DD
1A
3
VD
D10
R20
Y1
VD
D11
Y20
VD
D12
Y21
VD
D13
A9
VD
D2
AA
3V
DD
3V
DD
4B
13V
DD
5B
20F
2V
DD
6
J21
VD
D7
G8
SD
AT
A_3
B8
SD
AT
A_4
SD
AT
A_5
D8
SD
AT
A_6
C7
D7
SD
AT
A_7
SD
AT
A_8
B6
C6
SD
AT
A_9
SD
CL
KC
9D
9S
DC
LK
_EN
TCKW18
Y19TDITDO
AA19
W16
TI_
RE
SE
RV
ED
4T
I_R
ES
ER
VE
D6
Y4
V17TMS
M18TX
SA
DD
_7C
12G
11S
AD
D_8
SA
DD
_9D
11
SB
AN
K_0
C10
D10
SB
AN
K_1
T18
SC
L
V20
SD
A
SD
AT
A_0
B9
SD
AT
A_1
G9
H8
SD
AT
A_1
0S
DA
TA
_11
C5
D6
SD
AT
A_1
2S
DA
TA
_13
B4
SD
AT
A_1
4C
4D
5S
DA
TA
_15
C8
SD
AT
A_2
H15
PC
M_S
YN
C
RTS1AA15
W5RTS2
RXL14
V14RX1
RX2R9
B14
SA
DD
_0S
AD
D_1
C14
SA
DD
_10
C11
H10
SA
DD
_11
SA
DD
_12
G10
G12
SA
DD
_2D
13S
AD
D_3
SA
DD
_4C
13H
11S
AD
D_5
D12
SA
DD
_6
G19
NR
ES
ET
PW
RO
NN
RE
SE
T_O
UT
W15 H
9N
SC
AS
NS
DQ
ML
B3
D4
NS
DQ
MU
NS
RA
SA
2
C3
NS
WE
NTRSTY18
Y2
OS
C1_
INO
SC
1_O
UT
W3
W12
OS
C32
K_I
NO
SC
32K
_OU
TR
12
G21
PC
M_B
IT_C
LK
PC
M_C
LK
SG
20
H20
PC
M_D
AT
A_I
NH
18P
CM
_DA
TA
_OU
T
NBSCANY17
NC
E5
V16NEMU0
W17NEMU1
NFADVL4
L3NFBE_0NFBE_1
M8
M7NFCS_0
M3NFCS_1NFCS_2
M4
NFCS_3N8
U4NFOE
NFRDYH7
W1NFRP
NFWEW2
NFWPV4
LCD_PIXEL_15D15
C19LCD_PIXEL_2LCD_PIXEL_3
G14
LCD_PIXEL_4H13A20
LCD_PIXEL_5B19
LCD_PIXEL_6LCD_PIXEL_7
C18D17
LCD_PIXEL_8D16
LCD_PIXEL_9
LCD_VSYNCD14
MEDIA_CLKV11V10
MEDIA_CMD
MEDIA_CSP11W11
MEDIA_DIMEDIA_DO
R11
MP
U_N
RE
SE
TV
15
C20KBC_5KBR_0
G18F19
KBR_1H14
KBR_2KBR_3
E20E19
KBR_4
B15LCD_AC
LCD_HSYNCH12
LC
D_P
CL
KC
15
D18LCD_PIXEL_0LCD_PIXEL_1
B21
LCD_PIXEL_10C17B17
LCD_PIXEL_11LCD_PIXEL_12
G13A17
LCD_PIXEL_13LCD_PIXEL_14
C16
N18GPIO_12
N19GPIO_13GPIO_14
N21
GP
IO_1
5M
20
GPIO_2M14
GPIO_3P18
P20GPIO_4
P19
GP
IO_6
M15
GP
IO_7
GP
IO_8
Y8
W8
GP
IO_9
F18KBC_0
D20KBC_1
D19KBC_2KBC_3
E18C21
KBC_4
FDATA_11P8U1
FDATA_12FDATA_13
U3T4
FDATA_14FDATA_15
V3
N7FDATA_2FDATA_3
P2P4
FDATA_4FDATA_5
P7R2
FDATA_6FDATA_7
R3R4
FDATA_8FDATA_9
T2
R18
GP
IO_0
GP
IO_1
R19
N20
GP
IO_1
1
FADD_20J1L8
FADD_21FADD_22
K4K3
FADD_23L7
FADD_24
FADD_3C1E4
FADD_4FADD_5
D2
FADD_6F4E3
FADD_7FADD_8
J7F3
FADD_9
FCLKN3
N4FDATA_0FDATA_1
N2
FDATA_10T3
CO
NF
V18
R14CTS1
CTS2Y5
EX
T_F
IQW
19
J8FADD_1
FADD_10G4G3
FADD_11FADD_12
G2
FADD_13K8H4
FADD_14FADD_15
H3K7
FADD_16J2
FADD_17FADD_18
J4J3
FADD_19
D3FADD_2
CL
K32
K_C
TR
LA
A20
P13
CL
K32
K_I
N
CL
K32
K_O
UT
Y12Y
9C
OM
_MC
LK
_OU
T
COM_MCLK_REQR10
COM_PCM_CLKY10
COM_PCM_DINAA9W9
COM_PCM_DOUT
COM_PCM_SYNCV9
P14COM_SHUTDOWN
COM_SPI_CLKRV7
Y6COM_SPI_CLKX
COM_SPI_DINP10
AA5COM_SPI_DOUT
COM_SPI_RSYNCW6
W7COM_SPI_XSYNC
BT_PCM_DINW13W14
BT_PCM_DOUT
BT_PCM_SYNCV13
L19CAM_D_0CAM_D_1
K14K15
CAM_D_2CAM_D_3
K19K18
CAM_D_4J14
CAM_D_5CAM_D_6
J19
CAM_D_7J18H19
CAM_EXCLKCAM_HS
L15J15
CAM_LCLKCAM_RSTZ
M19
CAM_VSL18
ARMIO_1U19
N15
AR
MIO
_2
ARMIO_3V8
T19
AR
MIO
_4
ARMIO_5T20
AA
17A
RM
_BO
OT
Y13
BT
_MC
LK
_OU
T
R13
BT
_MC
LK
_RE
Q
BT_PCM_BCLKAA13
U603
OMAP1510
R670 270270R669
R679 270270R678270R677
GND2GND3
22
GND423
HS7
NC1121
NC2
SCL58
SDA
VDD_H3
VDD_L2
VS136
XRST
HEL_IO_MEM_2.8V
CKIN20
17D0
14D1
D21518
D3D4
1112
D5D6
910
D7
16DCK
4GND1
19
CONN_21FXL_RSM_TB CN601
TP
605
R62
2
33
R60
910
K
HEL_PLL_1.5V
C6040.1u
HEL_IO_MEM_2.8V
1
2
3
4
HEL_IO_MEM_2.8V
SW603
150
R62
6
SP
40
SP
31
SP
41
SP
39
SP
37
2
56
31
4
SP
36
EMX1Q604
18p
C67
622
0p
C61
3
10K
R60
6
1KR
644
100K
R63
6
C60
5
R675 270
31
4
1u
EMX18Q601
2
56
0.1uC618C617
HEL_IO_MEM_2.8V
0.1u0.1uC615
C671
0.1uC608
R64
31K
51K
R602
KEY_COL3
KEY_COL1
KEY_LED-
KEY_COL2
KEY_ROW0
_HEL_SYS_RST
MAIN_LCD_BACKLIGHT
MAIN_LCD_LED+
PWL_MAIN_LCD_BL
KEY_ROW2
HEL_UART_PC_RTS
USB_DETECT
HEL_IND_LED_O
HEL_TMS
SUB_LCD_CS
MAIN_LCD_CLK
EL_ONOFF
USB_VDD
USB_DM
ONNOFF
HEL_IND_LED_O
HEL_IND_LED_B
USB_DP
USB_VBUS
CAL_TMSCAL_TCKCAL_TDOCAL_TDICAL_NTRST
HEL_EMU0HEL_EMU1HEL_NTRSTHEL_TDIHEL_TDOHEL_TCK
HEL_EMU0HEL_EMU1
HEL_UART_DATA_RTSHEL_UART_DATA_CTS
HE
L_F
OL
DE
R_D
ET
CHARGER
HE
L_T
X_M
BO
X
CAL_TX_MBOX
HF_DET
PC
_IR
DA
_SE
L
STEREOJACK_DET
LOUD_SPKM
_YMU762_RST
SU
B_L
CD
_RE
S
HEL_UART_CNTL_RX
HEL_UART_IRDA_RXHEL_UART_IRDA_TX
HF_CALL_OFF_ON
KEY_ROW0_END_ONOFF
_YMU762_IRQ
HEL_NFWE
HE
L_N
FW
E
HEL_MCSI_DO
KEY_COL1KEY_COL2KEY_COL3KEY_COL4KEY_COL5KEY_LED-
KEY_ROW4KEY_ROW3
KEY_COL5
HEL_IND_LED_G
HEL_FADD(1)
HE
L_F
AD
D(1
)
MOTOR_BATT
CC
K32
K_C
UT
PC_UART_CTS
PC_UART_TXPC_UART_RX
HEL_FOLDER_DET
PC_UART_RTS
HE
L_I
ND
_LE
D_B
SU
B_L
CD
_CS
HEL_UART_PC_CTS
HEL_TDIHEL_TDOHEL_TMSHEL_TCK
HEL_NTRST
EL_ONOFF
HEL_MCSI_DIHEL_MCSI_CLK
HEL_FCLK
HEL_NFBE_1HEL_NFBE_0HEL_NFCS_3HEL_NFCS_2HEL_NFCS_1HEL_NFCS_0
HEL_MCSI_FS
UW
IRE
_SD
OU
WIR
E_S
CL
K
_END_ONOFFKEY_ROW0KEY_ROW1KEY_ROW2KEY_ROW3KEY_ROW4MAIN_LCD_RESMAIN_LCD_CD_SELMAIN_LCD_DATASUB_LCD_RESSUB_LCD_CD_SELUWIRE_SDO
LOUD_SPKPEAR_PIECEP
EAR_PIECEM
MAIN_LCD_LED+
UWIRE_SCLK
MAIN_LCD_CS
KEY_COL0
HEL_FADD(2)
HEL_FADD(19)
HEL_FADD(18)
HEL_FADD(17)
HEL_FADD(16)
HEL_FADD(15)
HEL_FADD(14)
HEL_FADD(13)
HEL_FADD(12)
HEL_FADD(11)
HEL_FADD(10)
HEL_NFADVHEL_NFRPHEL_NFWPHEL_NFRDY
HE
L_N
FO
E
HEL_NFOE
MA
IN_L
CD
_BA
CK
LIG
HT
SP
EA
KE
R_E
N
HEL_IND_LED_G
HEL_DATA(0:15)HEL_DATA(0:15)
HE
L_C
LK
_12M
_OU
T
KEY_COL0
KEY_COL4
MAIN_LCD_CLKMAIN_LCD_DATA
MAIN_LCD_CSMAIN_LCD_RES
MAIN_LCD_CD_SEL
SUB_LCD_CD_SEL
KEY_ROW1
HEL_DATA(9)
HEL_DATA(8)
HEL_DATA(7)
HEL_DATA(6)
HEL_DATA(5)
HEL_DATA(4)
HEL_DATA(3)
HEL_DATA(2)
HEL_DATA(15)
HEL_DATA(14)
HEL_DATA(13)
HEL_DATA(12)
HEL_DATA(11)
HEL_DATA(10)
HEL_DATA(1)
HEL_DATA(0)
HEL_UART_DATA_TX
HEL_UART_CNTL_TX
HEL_UART_DATA_RX
HEL_FADD(1:23)HEL_FADD(1:23)
HEL_FADD(9)
HEL_FADD(8)
HEL_FADD(7)
HEL_FADD(6)
HEL_FADD(5)
HEL_FADD(4)
HEL_FADD(3)
HEL_FADD(23)
HEL_FADD(22)
HEL_FADD(21)
HEL_FADD(20)
- 133 -
9. CIRCUIT DIAGRAM
5
City
Date Changed:
5 8
Time Changed:
Engineer:
10
E
Changed by:
11
6
QA CHK:
1
9
COMPANY NAMEH
F
2
2
4
A
MFG ENGR CHK:
12
10
3
Drawn by:
12
D
C
7 8
G
3
6
Size:
7
B
A
11
G
Drawing Number:
TITLE:
4
1
B
H
R&D CHK:
DOC CTRL CHK:
REV:
C
F
9
D
Page:
E
mentor
JS Lee
5:53:17 pmTuesday, December 11, 2001mentor 3
Memory12 1 8 A
A2
Address
NC9
E5RY_BY
J5VCCF
J6VCCS
VSS0J9
VSS1G3
_BYTEH9
J2_CE1S
H2_CEF
_LBC4
H3_OE
D5_RESET
_UBD4
_WEC6
C5_WP_ACC
H4
K6DU1DU2
G8
NC0A1
NC1A10
L1NC10NC11
L10
NC12M1
M10NC13
NC2B1
NC3B10
NC4C1
NC5F1F9
NC6NC7
F10
NC8G1
G10
CE2S
DQ0J3
DQ1G4
DQ10J4
DQ11K5J7
DQ12H7
DQ13DQ14
K8
DQ15H8
DQ2K4H5
DQ3H6
DQ4K7
DQ5G7
DQ6J8
DQ7K3
DQ8DQ9
F8D9
A15G9
A16F4
A17E4
A18D7
A19
A2E2
E6A20
A21E9
D2A3
F3A4
E3A5A6
D3
A7C3
A8C7
A9E7
D6
TH50VPF5683DASB U702
G2A0
F2A1
A10F7
A11C8D8
A12A13
E8
A14
10K
R79
8
DQ7G6H3
DQ8DQ9
J3
RY_BYC4
J5VDD
VSS1K2
VSS2K7
H7_BYTE
_CEH2
J2_OE
D5_RESET
_WEC5
_WP_ACCD4
A7C3
A8D6C6
A9
DQ0G3K3
DQ1
DQ10H4J4
DQ11H5
DQ12J6
DQ13H6
DQ14J7
DQ15
G4DQ2
K4DQ3DQ4
K5
DQ5G5
DQ6K6
F6A11
D7A12A13
C7E7
A14A15
F7G7
A16D3
A17E4
A18A19
F5
E2A2
F4A20A21
E5
A3C2D2
A4A5
F3E3
A6
TC58FVB641XB-70U703
G7000 EUASV
A0G2F2
A1
A10E6
HEL_IO_MEM_2.8V
HEL_IO_MEM_2.8V
10K
R79
7
10K
R78
9
C7040.1u
R70
510
K
R71
810
K
R70
8
10K
R712
0
R711
0R710
C7010.1u
J2
_CEF1H2F5
_CEF2
C4_LB
_OEH3
_RESETD5
D4_UB
C6_WE
_WP_ACCC5
M10
B1NC2
B10NC3
C1NC4
F1NC5NC6
F6
NC7F9F10
NC8NC9
G1
RY_BYE5
VCCF1J5G5
VCCF2VCCS
J6
J9VSS0
G3VSS1
H9_BYTE
_CE1S
H5
DQ4H6
DQ5K7
DQ6G7
DQ7J8
DQ8K3H4
DQ9
DU1K6G8
DU2
A1NC0
A10NC1
G6NC10NC11
G10
NC12L1L10
NC13M1
NC14NC15
F3
A5E3D3
A6C3
A7C7
A8E7
A9
CE2SD6
J3DQ0
G4DQ1
J4DQ10
K5DQ11DQ12
J7
DQ13H7K8
DQ14H8
DQ15
K4DQ2DQ3
G2
A1F2
F7A10
C8A11A12
D8E8
A13F8
A14A15
D9
A16G9
A17F4
A18E4
A19D7
E2A2
A20E6E9
A21
A3D2
A4
HEL_IO_MEM_2.8V
U701TH50VPF5781AASB
A0
0.1uC702
HEL_IO_MEM_2.8V
HEL_FADD(4)
HEL_FADD(21)
HEL_FADD(3)
HEL_FADD(19)
HEL_FADD(17)
HEL_FADD(15)
HEL_FADD(13)
HEL_FADD(11)
HEL_FADD(1)
HEL_NFBE_1HEL_NFBE_0
HEL_NFRDY
VRMEM
HEL_NFCS_0
HEL_NFCS_1
_CAL_CS0
_CAL_CS1
HEL_DATA(12)
HEL_DATA(13)
HEL_DATA(14)
HEL_DATA(15)
HEL_DATA(3)
HEL_DATA(5)
HEL_DATA(7)
HEL_DATA(9)
HEL_FADD(1:23)
HEL_FADD(22)
HEL_FADD(20)
HEL_FADD(18)
HEL_FADD(16)
HEL_FADD(14)
HEL_FADD(12)
HEL_FADD(10)
HEL_FADD(8)
HEL_FADD(6)
HEL_FADD(2)
HEL_NFWE
HEL_NFOE
HEL_NFCS_2
HEL_DATA(8)
HEL_DATA(6)
HEL_DATA(4)
HEL_DATA(2)
HEL_DATA(10)
HEL_DATA(0)
HEL_FADD(9)
HEL_FADD(7)
HEL_FADD(5)
_CAL_RD_CAL_WR
_CAL_BHE_CAL_BLE
CAL_ADD(1:22)
HEL_FADD(22)
HEL_FADD(1)
HEL_FADD(2)
HEL_FADD(3)
HEL_FADD(4)
HEL_FADD(5)
HEL_FADD(6)
HEL_FADD(7)
HEL_FADD(8)
HEL_FADD(9)
HEL_FADD(10)
HEL_FADD(11)
HEL_FADD(12)
HEL_FADD(13)
HEL_FADD(14)
HEL_FADD(15)
HEL_FADD(16)
HEL_FADD(17)
HEL_FADD(18)
HEL_FADD(19)
HEL_FADD(20)
HEL_FADD(21)
HEL_DATA(1)
HEL_DATA(11)
CAL_DATA(6)
CAL_DATA(7)
CAL_DATA(8)
CAL_DATA(9)
CAL_DATA(15)
_CAL_FDP
HEL_DATA(0)
HEL_DATA(1)
HEL_DATA(10)
HEL_DATA(11)
HEL_DATA(12)
HEL_DATA(13)
HEL_DATA(14)
HEL_DATA(15)
HEL_DATA(2)
HEL_DATA(3)
HEL_DATA(4)
HEL_DATA(5)
HEL_DATA(6)
HEL_DATA(7)
HEL_DATA(8)
HEL_DATA(9)
CAL_DATA(0:15)
CAL_ADD(22)
HE
L_D
AT
A(0
:15)
HEL_DATA(0:15)
_HEL_SYS_RST
HEL_NFRP
HEL_NFWP
CAL_ADD(1)
CAL_ADD(2)
CAL_ADD(11)
CAL_ADD(12)
CAL_ADD(13)
CAL_ADD(14)
CAL_ADD(15)
CAL_ADD(16)
CAL_ADD(17)
CAL_ADD(18)
CAL_ADD(19)
CAL_ADD(20)
CAL_ADD(3)
CAL_ADD(21)
CAL_ADD(4)
CAL_ADD(5)
CAL_ADD(6)
CAL_ADD(7)
CAL_ADD(8)
CAL_ADD(9)
CAL_ADD(10)
CAL_DATA(0)
CAL_DATA(1)
CAL_DATA(10)
CAL_DATA(11)
CAL_DATA(12)
CAL_DATA(13)
CAL_DATA(14)
CAL_DATA(2)
CAL_DATA(3)
CAL_DATA(4)
CAL_DATA(5)
Main PCB Circuit (3/5)
- 134 -
9. CIRCUIT DIAGRAMΩ
G
7
4 7
Date Changed:
E
Size:
12
DOC CTRL CHK:
CityAddress
D
F
C
D
Drawn by:
119
TITLE:
Page:
5
4
6
Time Changed:
10
QA CHK:
5
R&D CHK:
B
H
9 1 0
C
A
2
H
4
AUDIO12 1 8 A
A2
MFG ENGR CHK:
3
COMPANY NAME
6
G
Engineer:
8 12
F
8
2
B
REV:Changed by:
1
Drawing Number:
11
3
E
A
1
R847 10K
mentor
DJ Jung
3:09:32 pmFriday, December 14, 2001mentor
C831
10u
ADJ43
EN
2GNDIN
1OUT
5
R82
6
0
MIC5219BM5
U809
SP
30
R84
9
1K
27pC812
C80710p
C86110u
R894 0
C81
50.
1u
R803 0
0
R846
C888
SP
21
0F
R82
2
1K
HEL_IO_MEM_2.8V
0.1uC849
470
R871
COM1C3
A3COM2
B2
G1
G2
B3
GN
DB
1
C2IN1
A2IN2
C1NC1
A1NC2
C4NO1
NO2A4
B4
V+
SP
26
MAX4684EBC
U803
100K
R84
4
BYPASS4
2GND
VEN3
VIN1
VOUT5
LP3985IM5X-3.3U810
R82
3
1K
R80
7
200K
SP
2
C86
010
00p
U813
TC7SZ08AFE
A1
2B
GND3
VCC5
4Y
10uC846
0R833
330pC853
2
45
31
UM
C4N
Q80
8
0
R840
C847
SP
15
390p
620
R88
9
Q802DTC144EE
B
C
E
SP
19
100K
R80
2
33uC899
UMT2907AQ805
GN
D
1000
pC
859
1D
1
D2
3
D3
45D
4
D5
6
2
SM
F05
C
D80
3
2
45
31
R850
UMC4NQ809
10u
P11
P22
P3
3 4
P4
C866
L801
4.7uH
C9040.1u
C8010.47u
C817
HEL_IO_MEM_2.8V
27p
VSS
_CS29
_IRQ3
31_RD
4_RST
28_WR
R873
EQ1
EQ213
14 EQ3
HPOUT_L10
HPOUT_R11
IOVDD 32
2 LEDMTR19
NC5
6PLLC
SPOUT117
SPOUT218
SPVDD15
16SPVSS
VDD 7
VREF 9
8
30A0
1CLK1
D027
D126
D225
D3 24
D42322
D521D620
D7
12
SP
4
YMU762U807
B
C
E
DTC144EEQ804
SP
5
47uF
10uC854
0R883
C852
5
U812NCP500SN18T1
EN3
GND2
NC4
VIN1
VOUT
Q80
6U
MC
4N
2
45
31
R834 3.3K
R884 0
10uFC889
D11
D22
3D3D4 6
7D5
D6 8
G
4
5S
Q801NTHS5441T1
C84
868
n
R888 0
10pC808
R80
8
150K
10K
R85
1
R85
7
270K
R87
6
R87
70
SP
1
SP
11
1D+D+IC
6
D-3
D-IC4
2GND
5VBUS
U811 STF203-22
8.2K
R835
R90
6
R90
5
R854
C85133u
C863
C80247p
12
0.01u
220n
C82
1
OB
G-1
5S44
-C2
MIC
801
VBAT
C855
10u
R853 470
300K
R81
0
SP
3
SP
29
SP
14
C80
90.
1u
NO2A4
V+
B4
SP
25
COM1C3
A3COM2
B2
G1
G2
B3
GN
DB
1
C2IN1
A2IN2
C1NC1
A1NC2
C4NO1
D804
U805
MAX4684EBC
CRS08
1KR80
4
C85610u
R870 470
HEL_IO_MEM_2.8V
R83
7
82K
3GND
24
NC
1VDD
5VOUT
R85
5
180K
SP
13
U890
R1111N151B-TR
CE
47012
PWR_GND_21920
RFR_RTS
18RI_TMS
13RXD
TXD14
USB_PWR16
USB_RX10
15USB_TX
VBAT_GND_12526
VBAT_GND_2
27V_BAT_1
28V_BAT_2V_BAT_3
29
R863
CTS
DCD17
3DSR
DTR24
GND13031
GND2
HF_MODE2
ON_SW16
PCM_CLK87
PCM_RXA_IN
9PCM_SYNC
11PCM_TXA_OUT
PWR_+4_2V_12122
PWR_+4_2V_2
PWR_+5V_145
PWR_+5V_2
PWR_GND_1
CN802
1BATT_ID
23
D80
2
MB
RM
120L
T3
R856
15
R82
8
R86
50
B
C
E
R812
0
DTC144EEQ807
R82
4
10K
SP
27
1000pC844
SP
20
C850
R896
1K
47p
27pC814
10
R82
9R836
8.2K
SP
1722
0n
SP
10
C81
0
R86
210
K
R821
10K
1KR84
8
3
5VIN
U808 LTC1701BES5
2G
ND
RUN4
1SW
VFB
10K
R86
8
0R818
0R881
2 54
13
6
Q803 UMD2N
R81
3
R815
1K
R841
0
470R861
R811
0
HEL_IO_MEM_2.8V
0.1uC843
47pC813
10u
470
C867
123456
R860
J801
100K
R869
1B1
1B23
2A7
2B15
2B26
93A
3B111
103B2
124A
144B1
4B213
GND8
1S
16VCC
15_OE
U802SN74CBTLV3257DGVR
1A4
2
620
R89
2
FB
111
R859 100
470pC858
C830
6D
5
GN
D2
SP
22
470p
SM
F05
C
D80
1D
11 3
D2
4D
3
D4
5
SPK_VDD
AVDD
VBAT
C86
210
00p
AVDD
R82
7
47K
HEL_IO_MEM_2.8V
100
R819
R87
5
1M
Q810DTC144EE
B
C
E
470R858
83
TXD
6VCC
C8320.1u
U801CIM-80S7B-T
GND7
1LEDA
LEDK2
RXD4
5SD
SHIELD
R817
VRIO
0.1uC828
0R864
47pC819
R80
1
100K
R882 0
R87
8
12K
C82910u
10uC806
0R814
C85727p
R84
2
20K
SP
18
R89
062
0
470R872
10uC900
HEL_IO_MEM_2.8V
R825
2K
620C845
R88
7
0.022u
10pC804
R84
3
2.2K
4ADJEN
3GND
21
IN5
OUT
SP
28
VBAT
U804
MIC5219BM5
R81
6
R867 0
ONNOFF_BUF
HEL_CORE_1.5V
HEL_CLK_12M_OUT
MICBIAS
EAR_SPEAKER_SW
CHARGER
USB_DETECT
SPK_VDD
USB_PWR
AVDD
KEY_ROW1
DTC_SENSE
HF_MIC
LCD_1.8V
HEL_PLL_1.5V
HEL_IO_MEM_2.8V
USB_VDD
USB_VDD
ONNOFF_TO_BUF
DAI_SYNCDAI_CLK
CAL_UART_DCD
HEL_UART_PC_RX
PC_IRDA_SEL
LOUD_SPKP
LOUD_SPKM
AUXON
HF_SPK_P
HF_SPK_N
BAT_SENSE
HS_HF_SW
AUXI
HF_MIC
VBAT
CAL_UART_DSR
USB_PWR
DAI_RX
STEREOJACK_DET
_YMU762_IRQ
_YMU762_RST
USB_DP
USB_DM
SPEAKER_EN
HEL_NFOEHEL_NFCS_3
HEL_NFWE
HEL_FADD(1)
HF_SPK_N
AUXOP
HEL_UART_PC_TX
HEL_UART_PC_CTS
HEL_UART_IRDA_TX
HEL_UART_PC_TX
HEL_UART_IRDA_RX
_RPWON
DAI_TX
HF_CALL_OFF_ON
HEL_DATA(3)
HEL_DATA(2)
HEL_DATA(1)
HEL_DATA(7)
HEL_DATA(6)
HEL_DATA(5)
HEL_DATA(4)
HEL_DATA[0]HEL_DATA(0:15)
HE
L_D
AT
A(0
:15)
MICN
MICP
MOTOR_EN
HF_SPK_P
HEL_UART_PC_RTS
HEL_UART_PC_RX
MOTOR_BATT
Main PCB Circuit (4/5)
- 135 -
9. CIRCUIT DIAGRAM
Drawing Number:
2
10
TITLE:
8
QA CHK:
CityAddress
72
Page:
7
REV:
Size:
126
9
8
LDC15D190A007A
GPRS12 1 8 A
A2
4
12
COMPANY NAME
DOC CTRL CHK:
11
11
Drawn by:
3 10
R&D CHK:
9
Time Changed:
MFG ENGR CHK:
Engineer:
Changed by:
3 6
5
4 5
Date Changed:
0
3:07:35 pmMonday, December 10, 2001mentor 3
L151
2.2KR140
47pC160
R1410
R12
2
1.5nHL106
4.7u
1.2n_1608C167
C128
0.1uC114
12pC176
U103TC7SZ04AFE
2A
GND3
NC1
VCC5
4 Y
C171
4.7nH
3.9nH
L108
18pC186
10pC191
10n_2012C174
G1
1
G2
3
G3
5
IN
2O1
4O2
6
1KR145
FL105SAFSD942MCL0T00
C153470u
220R120
1KR128
C106
C168
0F
47p
0F
C192
C10547p
27pC121
C1511000p
R138
C180
OUT101
0F
TP101
1uC142
C1124.7u
3G
L1913.3nH
2.2uC147
C159
TP110
47p
R134180
0
R182
0.1u
C146
C182
1000p
L10312nH
C1114.7u
3G
ANTG1
G2RF
1000pC152
SW101KMS-502
C1294.7u
8200pC118
10nH
L150
3VCC10
VCC238
VCC342
VC
C4
5263V
CC
5
55V
CC
6
VC
C7
22
VCC833
VCC915
10VR4IN
49V
RE
G1
7VREG2
62V
RE
G3
60R
3
17R
ES
ET
Z
RX
_LO
N5354
RX
_LO
P28
RX
_MIX
INR
X_M
IXIP
27R
X_M
IXQ
N2625
RX
_MIX
QP
TE
ST
_VC
O29
TX
RX
CP
59
TXRXSW2
VAPC48
VB
AT
150
VBAT26
VB
AT
361
34VCC1
37GSM_INANGSM_INAP
36
1HBSW
IN20
IP21
LB
SW
64
35MAINVCO
5MAIN_CPMAIN_SPUP1
4
MA
IN_S
PU
P2
57 51O
MIX
RF
41PCS_INAN
40PCS_INAP
18Q
N19
QP
R2
5823
AU
X_V
CO
P
32B
AN
DG
AP
BIA
S_R
EF
31
CLK11
16CRF
DAT12
44DCS_INANDCS_INAP
43
30D
EC
RX
_MIN
46DETDDETR
45
EN13
47FILT
65G
ND
GND_INA39
56G
ND
_TX
CP
U105
TRF6150PAP8
APCAPCEN
9
14AUX_CP
24A
UX
_VC
ON
0FC161
TP102
1KR123
L10215nH
L10115nH
220pC116
1.2n_1608
C137
C183
470p
27p
C125
HVC369BD102
0.1uC157
G1
1 3
G2
5
G3
IN
2O1
4O2
6
TP119
SAFSD1G84CB0T00
FL104
1.5n_1608C175
470
R113
C181
1.8KR111
0F
C13347p
C1482.2u
C10
70F
R133
30
1.5nHC136
C1240F
C12227p
0FC189
300KR116
TP109
C1401000p
18n_3216C184
47pC166
C155
C162
0F
7
Y23
0F
U102NC7WZ02K8X
A11
A2 5
B12
B2 6
GND4
VCC 8
Y1
180R135
0F
470
R114
C169
C1090F
2.2pC164
C1301000p
0
R136
C135
A1 1
2A
2
CA
T3
7p
D103SMV1233-074
0.1uC127
C15047p
ENFVF382S18
2GND1
GND25
8GND3G
ND
413
GN
D5
14
RF_11
3RF_2
RF_34
6RF_4
SW_11011
SW_212
TX_RX_SW
VCC9
7VT
0F
FL101
C163
C1130.1u
82R117
0.1uC158
10pC123
47pC119
15K
R183
R126 0
U104LP3985IBPX-2.8
5BYPASS
GND2
1VEN
4VIN
3VOUT
150K
R121
FB
112
22pC134
C1390.1u
51R103
2.2pC156
3.9nH_1608L105
1G1
3
G2
4N
C1
NC26 UB1
2
UB
28
LDB25D500A0004AFL102
5 B1
7B2
R13
1
0
R1432.2K
100nHR105
GND13
GND25
GND39
GND411
GND512
GND613
VC
1
1
VC
2
7
SHS-M090B
FL1034
AN
T
DCS_RX6
DCS_TX8
EGSM_RX2
EGSM_TX10
68R119
3.3KR109
2.2nHC170
27pC138
1.2p
R180
C19
9
R913
1K
22pC185
L153100nH
C16547p
D101BAT15-05W
PT101
U8000
27pC120
TP120
L10412nH
GN
D3
1112G
ND
4
GN
D5
1314
GN
D6
15
GN
D7
GN
D8
16
GN
D9
17
4GSM_0GSM_1
1
VA
PC
2
VC
TL
7
3
VD
D1
VD
D2
6U101PF08107B
DCS_0 5DCS_18
9G
ND
1
18
GN
D10
GN
D2
10
6.8nH_1608L109
1000pC154
33pC131
C1720F
0FC102
C17712p
L152
C117
47p
220p
0.01uC149
C1327p
4.7u
3G
C115
0
R132
2.2KR142
C1440.1u
0FC178
1.5KR139
10uC110
X101
2GND
OUT3
VCC4
1VCONT
0FC173
13MHz
L1106.8nH_1608
0R127
120
R110
TP111
47pC103
27pC145
47
R107
1K
R129
R112
0
R106
100nH
1KR124
R115
100nH
0FC188
3G
R137680
L1071.5nH
0
R130
4.7uC141 3G
1K
C179
R125
0.1u
R1449.76K_1%
C14312p
C126
5.1K
R181
1IN1
3IN2
4TERM
0.1u
N101
B_OUT17
B_OUT25
COU_OUT8
GND12
6GND2
C19
80F
0FC104
RADIO_TEMP
RADIO_TEMP
VBAT_RF
VBAT_RF
VREG3
VBAT
RESETCL
QPQM
IPIM
TRXSWLBSW
VREG3VC2
HBSW
VC1TRXSW
VC1VC2
DETR
DETR
VR4I
PA_LEVEL
DETR
DETD
DETD
VTUNE
TRXSWHBSWLBSW
CRF
CLK13M
AFC
CRF
TSPENTSPDATA
TSPCLKVRIO
PA_ON
VBAT_RF
HB
SW
VA
PC
TCXO_EN
VREG3
VR4I
VAPC
VTUNE
HBSWLBSW
TRXSW
Main PCB Circuit (5/5)
3
Engineer:
F
Time Changed:
6
C
1
9
F
Drawn by:
DOC CTRL CHK:
C
4
City
MFG ENGR CHK:
R&D CHK:
2
D
11
Address
Page:Date Changed: REV:
B
E
Size:
Changed by:
5
COMPANY NAME
107
G
1
B
4 7
Drawing Number:
3
2
H
QA CHK:
9
mentor Thursday, December 13, 2001 7:30:44 pm
Y. J . SEOK
Y. J . SEOK
10
KEYPADS
A2
12 1 8 A
12
A
12
E
G
TITLE:
11
10
A
65
H
8
D
8
LD
6
456789
V2.8
171819
2
20212223242526272829
3
30
CN21
10111213141516
KB12
R19 270270R18
R16 270
LD
3
270R14
C110p
10K
R9
39R3
47p
C15
LD
2
V2.8
KB23
LD
11
R2
39
6
6061626364
789
4546474849
5
50515253545556575859
30313233343536373839
4
4041424344
16171819
2
20212223242526272829
3
CN11
101112131415
KB9
V2.8
KB22
R6
10K
V1.8
LD
1
KB1
KB7
KB15
KB8
LD
9
C4
KB13
47p
R15 270
LD
5
KB10
KB5
KB21
C20.1u
51K
R11
LD
14
LD
12
V2.8
KB2
LD
8
LD
16
LD
7
270R23
R22 270270R21
KB26
KB14
C6
VBAT
47p
C5
47pR
4
39
V1.8
KB3
LD
4KB6
10K
R20C9
47p
C8
47p
KB17
LD
10
10K
R17 C14
47p
39R1
C13
47p
47p
C12
KB25
2KR7
10K
R8
KB16
LD
13
KB19
10K
R5
VBAT
KB20
KB18
KB11
C11
47p
LD
15
3G
ND
2O
UT
VD
D1
KB24
A32
12E
LHU1
0.1u
R24 270
C3
KB4
MAIN_LCD_CS
UWIRE_SCLK
EAR_PIECEM
EAR_PIECEPLOUD_SPKP
LOUD_SPKMEAR_PIECEM
MOTOR_BATT
EL_ONOFF
UWIRE_SDOSUB_LCD_CD_SEL
MAIN_LCD_DATAMAIN_LCD_CD_SEL
MAIN_LCD_CSMAIN_LCD_CLK
SUB_LCD_CSUWIRE_SCLK
KEY_LED-
MAIN_LCD_RES
SUB_LCD_RES
MAIN_LCD_LED+
CAL_TMS
PC_UART_TX
HEL_FOLDER_DET
_END_ONOFF
KEY_COL0
EL_ONOFF
PC_UART_CTS
HEL_TMS
HEL_TDO
HEL_NTRST
HEL_EMU0
KEY_COL5
KEY_COL3
KEY_COL1
MAIN_LCD_CLK
SUB_LCD_CS
MAIN_LCD_LED+
LOUD_SPKM
MOTOR_BATT
PC_UART_RTS
HEL_TCK
HEL_TDI
HEL_EMU1
KEY_LED-
KEY_COL4
KEY_COL2
KEY_COL0
KE
Y_R
OW
4
KE
Y_R
OW
3
KE
Y_R
OW
2
KE
Y_R
OW
1
KE
Y_R
OW
0
KEY_COL1
KEY_COL2
KEY_COL3
KEY_COL4
KEY_COL5
EAR_PIECEP
UWIRE_SDO
SUB_LCD_RES
MAIN_LCD_CD_SEL
KEY_ROW4
KEY_ROW2
KEY_ROW0
HEL_FOLDER_DET
CAL_TDI
CAL_TCK
PC_UART_RX
LOUD_SPKP
SUB_LCD_CD_SEL
MAIN_LCD_DATA
MAIN_LCD_RES
KEY_ROW3
KEY_ROW1
_END_ONOFF
CAL_NTRST
CAL_TDO
- 136 -
9. CIRCUIT DIAGRAM
Keypad PCB Circuit (1/1)
- 137 -
9. CIRCUIT DIAGRAM
SIM PCB Circuit (1/1)
3CLK
6GND
I_O4
2RSTVCC
1
VPP5
456789
J1CN11
10
23
- 138 -
10. PCB LAYOUT
10. PCB LAYOUT
Main PCB Layout (1/2)
- 139 -
10. PCB LAYOUT
Main PCB Layout (2/2)
- 140 -
10. PCB LAYOUT
Keypad PCB Layout (1/2)
- 141 -
10. PCB LAYOUT
Keypad PCB Layout (2/2)
SIM PCB Layout (1/2)
- 142 -
10. PCB LAYOUT
- 143 -
10. PCB LAYOUT
SIM PCB Layout (2/2)