Lessons and Challenges for Future Signal, and Memory Circuits · 2014. 6. 17. · Reality of...
10
Lessons and Challenges for Future Mixed‐Signal, RF, and Memory Circuits Akira Matsuzawa Tokyo Institute of Technology VLSI panel, A. Matsuzawa 2014.06.12
Transcript of Lessons and Challenges for Future Signal, and Memory Circuits · 2014. 6. 17. · Reality of...
Lessons and Challenges for Future Mixed‐Signal, RF, and Memory Circuits
Akira Matsuzawa
Tokyo Institute of Technology
VLSI panel, A. Matsuzawa2014.06.12
1
Can we verify the analog circuits perfectly by circuit simulator?
VLSI panel, A. Matsuzawa2014.06.12
2Pitfalls of Analog IC Design
• Bugs of system level design• Lack of well device models• Wrong circuit simulation• Effects of parasitic components
– Not only in IC but also external components (package, PCB, etc.)
• Influences of EM fields
VLSI panel, A. Matsuzawa2014.06.12
3Ex.1 Hung-up: wrong system level design50MS/s SAR ADC suddenly stopped after 1 hour from power-on .Error rate: 10-11 ← Can we simulate?
Asynchronous operation VREF
VDAC
Vin
Q
R=1 ⇒ ReadyR=0 ⇒ Under Conversion‘START’ signal is ignored under conversion.
If asynchronous operation is stopped,‘R’ cannot be '1' .→Conversion is stopped.
i=i-1
2014.06.12
4Ex.2 Wrong circuit simulation
VP
VN
VDD=1.0V
CMOS oscillator with DC-cut LC tank
Sometimes circuits have two steady-states.Designers have to set a initial condition carefully.
VP
VN
VDD
VDD=0V
VDD= 1.0VActual power onRamped VDD
Conventional simulation
Doesn't Oscillate
2014.06.12
5V(
V(1)@2V(1)@3
0
0.2
0.4
0.6
0.8
1.0
V(2V(2)@2V(2)@3
0
0.4
0.8
1.2
1.6
0 1n 2n 3n 4n 5n
TIME (s)
8Ω16Ω
32Ω
8Ω
16Ω
32Ω
RC only
L is also considered
Ex.3 Different result: Effect of inductance
C110p
C210p
L1
5n
R1
8
R2
8
V10 PULSE 0 1 0 0.1n 0.1n 10n 20n 5
3 24
1
If inductance is neglected,The smaller resistance is the betterfor fast settling.However, actual circuit containsInductive component; wires.If it is considered,Smaller resistance makes largeRinging. The optimum resistanceexists.
VLSI panel, A. Matsuzawa2014.06.12
6Ex.4 Parasitic components
-20
-15
-10
-5
0
5
100 1000
Nor
mal
ized
Gai
n [d
B]
Frequency [MHz]
40dB30dB20dB10dB0dBIdeal LPF
ADC
0-40dBFc=1GHz
5bit 2.304GS/s
DigitalBaseband
ADC VDD
ADC VSS
IC Chip
Package
Wire
Baseband Input
ADC VDD-VSS
Input-dependent supply-noise
Revised versionWire coupling effect
Mutual inductance of package wire often forms feedback loop resulting in oscillation.
-40-35-30-25-20-15-10-505
10
0 200 400 600 800 1000 1200
Nor
mal
ized
Gai
n [d
B]
Frequency [MHz]
37.6dB31.5dB
19.8dB
0.4dB
Mutual inductance between wires
2014.06.12
7
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
-40 0 40 80 120
Vth
[V]
Temp []
SlowTypFast
0.3
0.35
0.4
0.45
0.5
0.55
0.6
-40 0 40 80 120
Vth
[V]
Temp []
SlowTypFast
Small design margin: VT of transistor
240mV 220mVPMOS NMOS
40nmCMOS
VT of 40nm CMOS transistor is quite high of 0.6V. (VGS=0.8V)PVT variation is 220-240mW. Therefore it is quite difficult to realize 1V operation with 40nm CMOS.
VLSI panel, A. Matsuzawa2014.06.12
8Reality of analog& mixed signal LSI• Circuit design
– Almost no margin for low voltage design.– Can’t simulate every performance with every condition.– Calibration technique is needed, however it can’t guarantee
the optimum performance.
• Layout design– Analog performance is strongly affected by layout design.– Package and board design affects the performance.– Not acceptable time for LPE simulation.
• Testing and embedding– No testing method for perfect verification.– Strongly affected by package or probe.– Affected by embedding to Mixed signal LSI.
VLSI panel, A. Matsuzawa2014.06.12
9Development procedure of M/S SoC
D-FF 5bit x 8
Circuit design TEG Test& Rework
Layout design
5b, 2.3GSps ADCBB SoC for 60GHzCMOS Transceiver
Embeding to the SoC
TEG test and rework are necessary before embedding to the M/S SoC.
Simulation with package
VLSI panel, A. Matsuzawa2014.06.12
