Lecture4Timer2019 - ele.uri.edu

10/1/19

1

1

Timing control and PWM

Sec 4. General Purpose TimerTimer

2

} Free-run counter (independent of processor)

} Functions} Input capture} Output compare} Pulse-width modulation (PWM) generation} One-pulse mode output

Timer: Clock

3

Reload Value

Timer Counter

fCL_PSCISR

Interrupt

Reload

PSC

ARR

!"#_"%& =!"(_)*"+,- +1

Prescaler

fCL_CNT

clock

Timer: Output

4

Reload Value

Timer Counter

fCL_PSCISR

Interrupt

Reload

PSC

ARR

Prescaler

fCL_CNT

clock

Compare & Capture

Register (CCR)

= Timer Output(OCREF)

Timer: Input Capture

5

Reload Value

Timer Counter

fCL_PSCISR

Interrupt

Reload

PSC

ARR

Prescaler

fCL_CNT

clock

Compare & Capture

Register (CCR)

Multi-Channel Outputs

6

10/1/19

2

Output Compare

7

Output Compare Mode (OCM) Timer Output (OCREF)000 Frozen001 High if CNT == CCR010 Low if CNT == CCR011 Toggle if CNT == CCR100 Forced low (always low)101 Forced high (always high)

PWM Mode

8

Mode Counter < Reference Counter ≥ ReferencePWM mode 1

(Low True) Active Inactive

PWM mode 2(High True) Inactive Active

Edge-aligned Mode (Up-counting)

9

ARR = 6, RCR = 0

clock

counter

Counter overflowUpdate event (UEV)

Period = (1 + ARR) * Clock Period= 7 * Clock Period

01

23

45

6

01

23

45

6

01

23

45

6

01

23

45

6Counter overflow

Counter overflow

Counter overflow

Edge-aligned Mode (down-counting)

10

ARR = 6, RCR = 0

Clock

Counter


01

23

45

6

01

23

45

6

01

23

45

6

01

23

45

6

Counter underflow

Counter underflow

Counter underflow

Counter underflowUpdate event (UEV)

Center-aligned Mode

11

ARR = 6, RCR = 0

Clock

Counter

Update event (UEV)

01

23

45

6

01

23

45

12

34

56

01

23

45

Counter overflow

Counter overflow

Counter underflow

Counter underflow

Period = 2 * ARR * Clock Period= 12 * Clock Period

PWM Mode 1 (Low-True)

12

01

23

45

6

01

23

45

6

01

23

45

6

01

23

45

6

Upcounting mode, ARR = 6, CCR = 3, RCR = 0

Clock

CounterCCR = 3


Duty Cycle = CCR

ARR + 1

=3

7

OCREF

Timer Output =High if counter < CCR

Low if counter ≥ CCR

Mode 1

10/1/19

3

PWM Mode 2 (High-True)

13

01

23

45

6

01

23

45

6

01

23

45

6

01

23

45

6


Clock

CounterCCR = 3


Duty Cycle = 1 -CCR

ARR + 1

=4

7

OCREF

Timer Output =Low if counter < CCR

High if counter ≥ CCR

Mode 2

14

01

23

45

6

01

23

45

6

01

23

45

6

01

23

45

6


Clock

Counter

CCR = 5

Duty Cycle = 1 -CCR

ARR + 1

=2

7


OCREF




Mode 2

15

01

23

45

6

01

23

45

12

34

56

01

23

45

Center-aligned mode, ARR = 6, CCR = 3, RCR = 0

Clock

CounterCCR = 3

Duty Cycle = 1 -CCR

ARR Period = 2 * ARR * Clock Period= 12 * Clock Period

=1

2

OCREF




Mode 2

16

01

23

45

6

01

23

45

12

34

56

01

23

45


Clock

CounterCCR = 1

Duty Cycle = 1 -CCR

ARR

=5

6

Period = 2 * ARR * Clock Period= 12 * Clock Period

OCREF




Mode 2

Auto-Reload Register (ARR)

17

} Auto-Reload Preload Enable (ARPE) bit in TIMx_CR1

Preload Register

Auto-reload Register (ARR)

Write to ARR

Read from ARR

Triggered by Update Event (UEV)

ARPE = 1 (Syn Update)

ARPE = 0 (Asyn Update)

Auto-reload Register (ARR)

Write to ARR

Read from ARR

If UDIS bit in TIMx_CR1 is 1, UEV event is disabled.

PWM Output Polarity

18

Mode Counter < CCRCounter ≥

CCRPWM mode 1

(Low True) Active Inactive

PWM mode 2(High True)

Inactive Active

Active Inactive

Active High High Voltage Low Voltage

Active Low Low Voltage High Voltage

Output Polarity: • Software can program the CCxP bit in the TIMx_CCER register

10/1/19

4

Counting up, down, center

19

Up-Counting: Left Edge-aligned

20

01

23

45

6

01

23

45

6

01

23

45

6

01

23

45

6


Clock

CounterCCR = 3

OC1REF

CCR = 6

OC2REF

CCR = 3

CCR = 6

All rising edges occur at the same time! PWM Period

Left-aligned

PWM Mode 2: Right Edge-aligned

21

01

23

45

6

01

23

45

6

01

23

45

6

01

23

45

6


CCR = 3

Clock

Counter

OC1REF

OC2REF

All falling edges occur at the same time!

CCR = 5

CCR = 5

CCR = 3

PWM Period

Right-aligned

PWM Mode 2: Center Aligned

22


01

23

45

6

01

23

45

12

34

56

01

23

45

CCR = 3

Clock

Counter

OC1REF

CCR = 1

OC2REF

PWM signals are center aligned!

CCR = 1

CCR = 3

PWM Period

Center-aligned



The devil is in the detail

23

} Timer output control} Enable Timer Output

} MOE: Main output enable} OSSI: Off-state selection for

Idle mode

} OSSR: Off-state selection for Run mode

} CCxE: Enable of capture/compare output for channel x

} CCxNE: Enable of capture/compare complementary output for channel x

Input Capture

24

} Monitor both rising and falling edge

10/1/19

5

Input Capture

25

} Monitor only rising edges or only falling edge

Input Capture

26

Input Filtering

27

Input Capture Diagram

28

Ultrasonic Distance Sensor

29

!"#$%&'( = *+,&- ./"0 ."1(×30((- +4 3+,&-2

= *+,&- ./"0 ."1( µ#58


30

The echo pulse width corresponds to round-trip time.

!"#$%&'( ('*) = -./#(0"1$ℎ (3#)58or

!"#$%&'( ("&'ℎ) = -./#(0"1$ℎ (3#)148

If pulse width is 38ms, no obstacle is detected.

10/1/19

6


31

Real-Time Clock (RTC)

32

} RTC is a digital clock that provides calendar time and date.

} Typical requirements:} Low power consumption

} Separately powered by a battery} Accurate

} Run independently from the processor core

UNIX Epoch Time

33

} Definition: number of seconds that have elapsed since 00:00:00 UTC, Thursday, 1 January 1970

} Example:} Converting 2:07:39am, April 21, 2014 (UTC) to Unix Epoch number

= 16181 days×secondsday +2 hours×secondshour +7minutes×secondsminutes +39UNIX EpochNumber

= 16181×86400+2×3600+7×60+39= 1398046059= 0x53547D6B

Note a day has 86400 seconds (24×60×60 = 86400)

UNIX Epoch Time

34

} Use a signed 32-bit integer to hold the UNIX Epoch Time } Covers a time span of 136 years.} Minimum representable time is 1901-12-13} Maximum representable time is 2038-01-19

} Year 2038 Problem (also called Unix Millennium Bug)} The second after 03:14:07 UTC 2038-01-19 is an overflow

(which became 1901-12-13).

} Use a signed 64-bit integer to fix the problem} A challenge in embedded systems

Crystal Inaccuracy: PPM

35

} Parts Per Million (PPM) = 10-6

} Crystal Inaccuracy} 1 PPM ⟶±1.1secondsperyear} Atypicalwatchcrystalhas20PPM

} Errorperday:86400seconds× 20× 10-6 =1.728seconds/day

} Errorpermonth:30days× 1.728seconds/day=51seconds/month

} STM32 RTC} At 25°C, HSI and MSI have an accuracy of 100 ppm (not

accurate enough for RTC)

} Need to use external LSE crystal, typically 32.768 kHz (215

Hz)

Frequency Setting

36

!"#$ =!&'(

)*+,-ℎ_012*-3421 +1 × 8+,-ℎ_012*-3421 +1

10/1/19

7

Frequency Setting

37

If !"#$ is 32.768 kHz, i.e. 215 Hz, then %&'()ℎ_,-.&)/0.- is 27-1, i.e.127, and 1'()ℎ_,-.&)/0.- is set as 28-1, i.e. 255, in many applications, as shown below.

! = !"#$%&'()ℎ_,-.&)/0.- +1 × 1'()ℎ_,-.&)/0.- +1

= 278127+1 × 255+1

= 2782;×2<

= 1=>

Initial Setup of Raspberry

} Connect SD card directly to Pi that is connected to a monitor through HDMI (Don’t use SD card reader to format SD card, OS is already preloaded)

} Change PassWD to all up case letters} RASPBERRY

} WiFi Connection} UID = Embedded_sytem; Passwd: lab440-picar

} Enable SSH: SSH (secure shell)} PreferenceàRaspberry Pi ConfigàInterface

} Shut Down the Raspberry Pi} Take SD card out

38

Download Programs to Pi} Insert the SD card to your Pi Car} Acquire IP address} Use Putty to connect and operate PiCar} Download the Pi car program} Follow the instructions in Section 3.2 to download

all the programs of the Pi car (~30 mins)

- Add the RPi Car program to auto-start. Make sure Exec path is correct.

} Auto-start Pi Car } Client Server

39

Lecture4Timer2019 - ele.uri.edu

Documents

Transcript of Lecture4Timer2019 - ele.uri.edu