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George Mason UniversityECE 545 Introduction to VHDL

Data FlowModeling of

Combinational Logic

ECE 545Lecture 2 Part 2

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2ECE 545 Introduction to VHDL

Resources

Volnei A. Pedroni, Circuit Design with VHDLChapter 5, Concurrent CodeChapter 4.1, Operators

Sundar Rajan, Essential VHDL: RTL SynthesisDone Right

Chapter 3, Gates, Decoders and Encoders(see errata at http://www.vahana.com/bugs.htm)

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3ECE 545 Introduction to VHDL

Register Transfer Level (RTL) Design Description

CombinationalLogic

CombinationalLogic

Registers

Todays Topic

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4ECE 545 Introduction to VHDL

D escribing

Combinational LogicUsing

D ataflow D esign Style

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5ECE 545 Introduction to VHDL

VHDL Design Styles

Components and interconnects

structural

VHD L D esignStyles

dataflow

Concurrent statements

behavioral

Registers

State machinesTest benches

Sequential statements

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6ECE 545 Introduction to VHDL

Data-flow VHDL

c on cu rrent signal assignment ( ) c onditional c on cu rrent signal assignment

(when-else )sele c ted c on cu rrent signal assignment

(with-sele c t-when )generate s c heme for eq u ations

(for-generate )

Major instructionsC oncurrent statements

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7ECE 545 Introduction to VHDL

Data-flow VHDL

concurrent signal assignment ( ) c onditional c on cu rrent signal assignment

(when-else )sele c ted c on cu rrent signal assignment

(with-sele c t-when )generate s c heme for eq u ations

(for-generate )

Major instructionsC oncurrent statements

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8ECE 545 Introduction to VHDL

Data-flow VHDL: Example

0 0 0 10 11

1

c i 1

0 0 0 0 111

1

0 0 110 0 1

1

0 10 10 10

1

c i x i y i

00 01 11 1 0

0

1

x i y ic i

1

1

1

1

s i x i y i c i =

00 01 11 1 0

0

1

x i y ic i

1

1 1 1

c i 1+ x i y i x i c i y i c i+ +=

c i

x i

y i s i

c i 1+

(a) Truth table

(b) Karnaugh maps

(c) Circuit

0 110 10 0

1

s i

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9ECE 545 Introduction to VHDL

Data-flow VHDL: Example (1 )

LIBRARY ieee ;USE ieee.std_logi c _1164.all ;

ENT ITY f u lladd ISPOR T ( x : I N STD_ LOG IC ;

y : I N STD_ LOG IC ;c in : I N STD_ LOG IC ;s : OUT STD_ LOG IC ;c ou t : OUT STD_ LOG IC ) ;

END f u lladd ;

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10ECE 545 Introduction to VHDL

Data-flow VHDL: Example (2 )

ARCHI TECTU R E f u lladd_dataflow OF f u lladd IS

BEG I Ns

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11ECE 545 Introduction to VHDL

Logic Operators

Logic operators

Logic operators precedence

and or nand nor xor not xnor

not

and or nand nor xor xnor

Highest

Lowest

only in VHDL- 93

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1 2ECE 545 Introduction to VHDL

Wanted: y = ab + cdIncorrecty

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13ECE 545 Introduction to VHDL

Concatenation

SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c, d , e , f: STD_LOGIC_VECTOR(7 DOWNTO 0);

a

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1 4ECE 545 Introduction to VHDL

Rotations in VHDL

a( 3 ) a(2) a( 1 ) a( 0 )

a(2) a( 1 ) a( 0 ) a( 3 )

a

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1 5ECE 545 Introduction to VHDL

Arithmetic Operators in VHDL ( 1 )

T o use basic arithmetic operations involvingstd_logic_vectors you need to include thefollowing library packages:

LIBRARY i eee ;USE i eee.std _l og i c_ 1164.a ll;

USE ieee.std_logic_unsigned.all;or

USE ieee.std_logic_signed.all;

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16ECE 545 Introduction to VHDL

Arithmetic Operators in VHDL (2)

You can use standard +, - operatorsto perform addition and subtraction:

signal A : STD_ LOGIC _VE CTOR(3 downto 0);signal B : STD_ LOGIC _VE CTOR(3 downto 0);signal C : STD_ LOGIC _VE CTOR(3 downto 0);

C

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17ECE 545 Introduction to VHDL

Data-flow VHDL

c on cu rrent signal assignment ( )

conditional concurrent signal assignment(when-else )

sele c ted c on cu rrent signal assignment(with-sele c t-when )

generate s c heme for eq u ations(for-generate )

Major instructionsC oncurrent statements

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18ECE 545 Introduction to VHDL

Conditional concurrent signal assignment

target_signal

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19ECE 545 Introduction to VHDL

Operators

Relational operators

Logic and relational operators precedence

= /= < >=

not= /= < >=and or nand nor xor xnor

Highest

Lowest

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20ECE 545 Introduction to VHDL

compare a = bcIncorrect

when a = b and c else

equivalent to when (a = b) and c else

Correct when a = (b and c) else

Priority of logic and relational operators

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21ECE 545 Introduction to VHDL

Tri-state Buffer example ( 1 )

LIBRARY ieee;USE ieee.std_logic_ 116 4.all;

ENTITY tri_state ISPORT ( ena: IN STD_LOGIC;

input: IN STD_LOGIC_VECTOR( 7 downto 0 );output: OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 )

);END tri_state;

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22ECE 545 Introduction to VHDL

Tri-state Buffer example (2)

ARCHITECTURE tri_state_dataflow OF tri_state ISBEGIN

output Z );

END tri_state_dataflow;

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23ECE 545 Introduction to VHDL

Data-flow VHDL

c on cu rrent signal assignment ( ) c onditional c on cu rrent signal assignment

(when-else )selected concurrent signal assignment

(with-select-when )

generate s c heme for eq u ations(for-generate )

Major instructionsC oncurrent statements

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24ECE 545 Introduction to VHDL

Selected concurrent signal assignment

with cho i c e_expressi o n selecttarget_signal

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25ECE 545 Introduction to VHDL

Allowed formats of choices_k

WHEN value

WHEN value_ 1 to value_2

WHEN value_ 1 | value_2 | .... | value N

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26ECE 545 Introduction to VHDL

Allowed formats of choice_k - example

WITH se l SELECTy