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EE 105 Spring 1997

Lecture 27

MOSFET Current Source Equivalent Circuit

s Small-signal model: source resistance is r

o

2

by inspection

s

Combine output resistance with DC output current for approximate equivalent

circuit ... actual i

OUT

vs. v

OUT

characteristics are those ofM

2

with V

GS2

= V

REF

gm1vgs1gm2vgs2ro1 ro2

+

vgs2= 0 V

1/ro2ro2

iOUT iOUT

vOUT

vOUT(W/L)2(W/L)1

IREF

(W/L)2(W/L)1

IREF

(a) (b)

VDSSAT2

+

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Lecture 27

The Cascode Current Source

s

In order to boost the source resistance, we can study our single-stage building

blocks and recognize that a common-gate is attractive, due to it high output

resistance

s

Adapting the output resistance for a common gate amplier, the cascode current

source has a source resistance of

s

Penalty for cascode:

needs larger V

OUT

to function

VDD

IREF

M3 M4

M2M1

iOUT

RS

1 g+m4

ro2

( )ro4

gm4

ro4

ro2

=

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EE 105 Spring 1997

Lecture 27

MOSFET Current Sources and Sinks

s

n-channel current source sinks

current to ground ... how do we source

current

from the positive supply? Answer: p-channel current sources...?

s

By mixing n-channel and p-channel diode-connected devices, we can produce

current sinks and sources from a reference current connected to V

DD

or ground.

VDD

IREF

MR

M1 M2M3

iOUT1 iOUT2 iOUT3

IREF

MR

VDD

M1M2

M4M3

iOUT1 iOUT2

iOUT4

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EE 105 Spring 1997

Lecture 27

Two-Stage BiCMOS Transconductance Amplier

s

Concept: cascade two common-emitter stages to get more transconductance --

not

an ideal solution but illustrates DC biasing and interstage coupling

s

DC Issues:

First stage: npn common-emitter amplier (DC level shifts up)

Second stage: pnp common-emitter amplier (DC level shifts down)

+

_

vs

RS

Gm2vin2

Rin2

+

_

vin2

Gm1vin1

Rin1

+

_

vin1Rout2Rout1 RL

iout

CE (npn) CE (pnp)

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Lecture 27

Amplier Topology

s

Basic structure -- connect output of CE (npn) to input of CE (pnp),

attach small-signal voltage input (withR

S

) and load (

R

L

)

s

Current source design:

assume that the reference current is generated by a resistor (to ground)

+

_+

_

vs

VBIAS

RS

V+ = + 2.5 V

Q2

Q1

iout

RL

V- = - 2.5 V

iSUP2

iSUP1

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Lecture 27

DC Currents from Reference

s p-channel diode-connectedM3 is used to generate source-gate voltages forM4(which generates iSUP1) and forM5. The second current supply is generated by

rst using -ID5 to generate a DC gate-source voltage via diode-connectedM7.

V+ = + 2.5 V

M4M3

M7

RREF

M5

M6

V- = - 2.5 V

IREF

iSUP1 - ID5

iSUP2

ID7

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Lecture 27

Two-Stage BiCMOS Transconductance Amplier

s Combine current source circuit with basic amplier topology

+

_+

_

vs

VBIAS

RS

V+ = + 2.5 V

Q2

M4

Q1

M3

M7

RREF

M5

M6

iout

RL

V-= - 2.5 V

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EE 105 Spring 1997

Lecture 27

DC Bias of Transconductance Amplier

s Given: VOUT= 0 V (DC); V+ = 2.5 V, V- = -2.5 V;RS=RL = 50 k

s Standard simplications: assumeIB = 0 for bipolar transistors, neglect Early

effect (BJT) and channel-length modulation (MOSFETs) for hand calculations

s Device Properties: (for simplicity, make all n-channel and all p-channel

MOSFETs the same dimensions)

MOSFETs: nCox = 50 AV-2, (W/L)n = (50/2), VTn = 1 V, n = 0.05 V

-1

pCox = 25 AV-2, (W/L)p = (80/2), VTp = - 1 V, p = 0.05 V

-1

BJTs: on

= 100, VAn

= 50 V, op

= 50, VAp

= 25 V

+

_+

_

vs

VBIAS

RS

V+ = + 2.5 V

Q2

M4

Q1

M3

M7

RREF

M5

M6

iout

RL

V-= - 2.5 V

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Lecture 27

Reference Resistor

s FindRREFsuch thatIREF= 50 A and then find all node voltages and DC biascurrents ...

s SubstitutingIREF= -ID3 = 50 A, the source-gate voltage drop is

s Solve for the reference resistor:

M3

RREF

+2.5 V

- 2.5 V

IREF0

- ID3

VSG3 VDD IREFRREF VSS=

+_

VSG3 VTp

I

D3

W 2L( )( )p

pC

ox---------------------------------------------+=

VSG3

VSG3 1 V( ) 50 A80

2 2( )( )---------------- 50 A/V2( )----------------------------------------------------+ 1.22 V= =

RREF

VDD

VSS

( ) VSG3

IREF

----------------------------------------------------2.5 V 2. 5 V( ) 1.22 V

50 A----------------------------------------------------------------- 75.6 k= = =

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Lecture 27

DC Operating Point

s Since width-to-length ratios are identical for n-channel and p-channel devices

(separately), the DC supply currents are equal to the reference current

s Neglecting base currents,IC1 = 50 andIC2 = 50

Q1: gm1 = 2 mS, r1= 50 k, ro1 = 1

Q2: gm2 = 2 mS, r2= 25 k, ro2 = 500 k

Source resistances of the current supplies for rst and second stages:

roc1 = ro4 = (4(-ID4))-1 = (0.05(0.05))-1 = 400 k

roc2 = ro6 = (6(ID6))-1 = (0.05(0.05))-1 = 400 k

+

_+

_

vs

VBIAS

RS

V+ = + 2.5 V

Q2

Q1

iout

RL

V- = - 2.5 V

ISUP2 =

ISUP1 =50 A

50 A

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Lecture 27

Overall Two-Port Model

s Rin =Rin1 = 50 kandRout=Rout2 = ro2 || roc2 = 500 k || 400 k = 220 k

s Overall short-circuit transconductance Gm -- must apply procedure

Find input voltage to the second stage:

vin2 = - Gm1(Rout1 ||Rin2 ) vin = - gm1 ( ro1 || roc1 || r 2 ) vin

Output current

iout= Gm2 vin2 = gm2 [- gm1 (ro1 || roc1 || r2)] vin

s Overall transconductance:

Gm = iout/ vin = - gm2gm1 (ro1 || roc1 || r2)

Gm = - (2 mS)(2 mS)(1 M || 400 k || 25 k) = - (2 mS)(2 mS)(23 k)

Gm = - 92 mS

+

_vin

Gm2vin2

Rin2

+

_

vin2

Gm1vin1

Rin1

+

_

vin1Rout2Rout1

iout

CE (npn) CE (pnp)

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Lecture 27

Output Voltage Swing

s Find the maximum and minimum values ofvOUT

s

Determine how high the output node can rise before a device leaves its constant-current region

Q2 saturates when vOUT= VOUT(max) = 2.4 V ... VEC(sat) = 0.1 V

Note thatM4 is still saturated since VSD4 = VEB4 = 0.7 V >vSG4 + VTp = 0.22 V

s Determine how low the output node can drop ...

M6goes triode when vOUT= VDS7(sat) = VGS7 - VTn = 1.22 V - 1 V = 0.22 V

VOUT(min) = - 2.5 V + 0.22 V = 2.23 V

+

_VBIAS

Q2

M4

Q1

M3

M7

RREF

M5

M6

vOUT

V-= - 2.5 V

V+= 2.5 V