lecture digital integrated circuits chapter12 [호환...

Digital Integrated Digital Integrated g gg gCircuitsCircuits

SemiconductorSemiconductorSemiconductorSemiconductorMemoriesMemoriesMemoriesMemories

© Digital Integrated Circuits2nd Memories

Chapter OverviewChapter OverviewChapter OverviewChapter Overview

M Cl ifi tiMemory ClassificationMemory ArchitecturesMemory ArchitecturesThe Memory CoreyPeripheryReliabilityCase StudiesCase Studies


Semiconductor Memory ClassificationSemiconductor Memory ClassificationSemiconductor Memory ClassificationSemiconductor Memory Classification

Read-Write MemoryNon-VolatileRead-Write Read-Only Memory

Memory

EPROMRandom Non-RandomMask ProgrammedEPROM

E2PROM

FLASH

Access Access Mask-Programmed

Programmable (PROM)

FIFO FLASHSRAM

DRAM

FIFO

Shift Register

LIFO

Shift Register

CAM


Memory Timing: DefinitionsMemory Timing: DefinitionsMemory Timing: DefinitionsMemory Timing: Definitions


Memory Architecture: DecodersMemory Architecture: DecodersMemory Architecture: DecodersMemory Architecture: DecodersM bits M bits

Word 0

Word 1S

S0

S1

SA 0

Word 0

Word 1S

S0

Word 2 Storagecell

words

S2 A 1

A

Word 2 Storagecell

Word N 2 2

Word N 2 1

NwordsSN 2 2A K 2 1

SN 2 1

Word N 2 2

Word N 2 1

Decoder

K 5 log2N

Input-Output(M bit )

Input-Output(M bit )(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N d N l t i l K = log2NDecoder reduces the number of select signals

(M bits)


N words == N select signals K log2N

ArrayArray--Structured Memory ArchitectureStructured Memory Architecture


Hierarchical Memory ArchitectureHierarchical Memory ArchitectureHierarchical Memory ArchitectureHierarchical Memory Architecture


Block Diagram of 4 Mbit SRAMBlock Diagram of 4 Mbit SRAMggClock

generatorZ-address

bufferX-address

buffergenerator buffer buffer

Predecoder and block selectorBit line load

Subglobal row decoderGlobal row decoderSubglobal row decoderBl k 30Bl k 31

128 K Array Block

Block 30Block 31 Block 1

Transfer gateColumn decoder

Sense amplifier and write driver Local row decCS, WEbuffer

I/Obuffer

Y-addressbuffer

X-addressbuffer

x1/x4controller

© Digital Integrated Circuits2nd Memories[Hirose90]

ContentsContents--Addressable MemoryAddressable MemoryContentsContents Addressable MemoryAddressable Memory

I/O BuffersI/O Buffers

CommandsCommands

Address Decoder29Validity BitsPriority Enc29Validity BitsAddress DecoderPriority Enc

Address Decoder29Validity Bits

Priority Enc


Memory Timing: ApproachesMemory Timing: ApproachesMemory Timing: ApproachesMemory Timing: Approaches


ReadRead--Only Memory CellsOnly Memory CellsReadRead--Only Memory CellsOnly Memory CellsBL BLBL

WL

BL

WL

BL

1WL

BLVDD

1

WL

BL

WL

BL

WL

BL

0WL

GND

Diode ROM MOS ROM 1 MOS ROM 2


MOS OR ROMMOS OR ROMMOS OR ROMMOS OR ROMBL[0] BL[1] BL[2] BL[3]

WL[0]

VDDVDD

WL[1]

WL[2]

VDD

WL[3]

DD

Vbias

Pull-down loads


Pull down loads

MOS NOR ROMMOS NOR ROMMOS NOR ROMMOS NOR ROMVDD

Pull-up devices

WL[0]

GND

WL [1]

WL [2]WL [2]

WL [3]

GND

BL [0]

WL [3]

BL [1] BL [2] BL [3]


[ ] [ ] [ ] [ ]

MOS NOR ROM LayoutMOS NOR ROM LayoutyyCell (9.5λ x 7λ)

Programmming using theg g gActive Layer Only

PolysiliconPolysilicon

Metal1

DiffusionDiffusion

Metal1 on Diffusion


MOS NOR ROM LayoutMOS NOR ROM LayoutyyCell (11λ x 7λ)

Programmming usingg g gthe Contact Layer Only

PolysiliconPolysilicon

Metal1

DiffusionDiffusion

Metal1 on Diffusion


MOS NAND ROMMOS NAND ROMMOS NAND ROMMOS NAND ROMVDD

Pull-up devices

BL[3]BL[2]BL[1]BL [0]

WL [0]

WL [1]

WL [2]WL [2]

WL [3]

All d li hi h b d f lt ith ti f l t d


All word lines high by default with exception of selected row

MOS NAND ROM LayoutMOS NAND ROM LayoutyyCell (8λ x 7λ)

Programmming usingthe Metal-1 Layer Only

No contact to VDD or GND necessary;d ti ll d d ll i

y y

Loss in performance compared to NOR ROMdrastically reduced cell size

Polysilicon

DiffusionDiffusion

Metal1 on Diffusion


NAND ROM LayoutNAND ROM LayoutCell (5λ x 6λ)

Programmming usingImplants Onlyp y

Polysilicon

Threshold alteringThreshold-alteringimplant

Metal1 on Diffusion


Equivalent Transient Model for MOS NOR ROMEquivalent Transient Model for MOS NOR ROMqu a e t a s e t ode o OS O Oqu a e t a s e t ode o OS O O

Model for NOR ROM VDD

BL

Cbit

rword

cword

WL

Word line parasiticsWord line parasiticsWire capacitance and gate capacitanceWire resistance (polysilicon)

Bi li i iBit line parasiticsResistance not dominant (metal)Drain and Gate-Drain capacitance


p

Equivalent Transient Model for MOS NAND ROMEquivalent Transient Model for MOS NAND ROMqq

VDD

Model for NAND ROM

C

BL

CL

rwordcbit

rbit

WL

Word line parasitics

cword

Word line parasiticsSimilar to NOR ROM

Bit line parasiticsResistance of cascaded transistors dominatesDrain/Source and complete gate capacitance


Decreasing Word Line DelayDecreasing Word Line DelayDecreasing Word Line DelayDecreasing Word Line DelayPolysilicon word lineWL

DriverPolysilicon word lineWL

l d li

(a) Driving the word line from both sides

Metal word line

Metal bypass

Polysilicon word lineK cells

(b) Using a metal bypass

WL

(b) Using a metal bypass

(c) Use silicides


Precharged MOS NOR ROMPrecharged MOS NOR ROMPrecharged MOS NOR ROMPrecharged MOS NOR ROMVDDpref

WL [0]

Precharge devices

GNDWL [1]

WL [2]

GND

BL [0]

WL [3]

BL [1] BL [2] BL [3]

PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.

[0] [ ] [ ] [3]


g

NonNon--Volatile MemoriesVolatile MemoriesTh Fl iTh Fl i i (FAMOS) i (FAMOS)The FloatingThe Floating--gate transistor (FAMOS)gate transistor (FAMOS)

Floating gate GateFloating gate

Source

Gate

Drain

t G

D

n+ n+_p

tox

tox

G

S

Substratep

Device cross section Schematic symbolDevice cross-section Schematic symbol


FloatingFloating--Gate Transistor ProgrammingGate Transistor ProgrammingFloatingFloating Gate Transistor ProgrammingGate Transistor Programming

0 V 5 V20 V

2 5 V 0 V

DS

2 2.5 V 5 V

DS

10 V 5 V 20 V

DS DS

Removing programming lt l h t d

DS

Programming results inhi h V

DS

Avalanche injectionvoltage leaves charge trapped higher VT.


A “ProgrammableA “Programmable--Threshold” TransistorThreshold” TransistorA ProgrammableA Programmable Threshold TransistorThreshold Transistor


FLOTOX EEPROMFLOTOX EEPROMFLOTOX EEPROMFLOTOX EEPROMFloating gate

Source

Gate

Drain

I

Source

20–30 nm -10 V10 V

VGD

Substratep

n1 n1

10

FLOTOX transistor Fowler-Nordheim I V characteristic

10 nm

I-V characteristic


EEPROM CellEEPROM CellEEPROM CellEEPROM CellBL

WLWLAbsolute threshold controlis hard

VDD

is hardUnprogrammed transistor might be depletionmight be depletion

2 transistor cell


Fl h EEPROMFl h EEPROMFlash EEPROMFlash EEPROM

Control gate

erasure

Floating gate

Thin tunneling oxideerasure Thin tunneling oxide

n 1 source n1 drainprogrammingp-substrate

p g g

Many other options …


CrossCross--sections of NVM cellssections of NVM cellsCrossCross sections of NVM cellssections of NVM cells

Ol h© Digital Integrated Circuits2nd Memories

EPROMFlashCourtesy Intel

Basic Operations in a NOR Flash Memory―Basic Operations in a NOR Flash Memory―Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash MemoryEraseErase


Basic Operations in a NOR Flash Memory―Basic Operations in a NOR Flash Memory―Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash MemoryWriteWrite


Basic Operations in a NOR Flash Memory―Basic Operations in a NOR Flash Memory―Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash MemoryReadRead


NAND Flash MemoryNAND Flash Memoryyy

Word line(poly)

Unit Cell

Source line(Diff Layer)


(Diff. Layer)

Courtesy Toshiba

NAND Flash MemoryNAND Flash MemoryNAND Flash MemoryNAND Flash Memory

Word linesSelect transistor

Active area

STI

Bit line contact Source line contact

© Digital Integrated Circuits2nd MemoriesCourtesy Toshiba

Characteristics of StateCharacteristics of State--ofof--thethe--art NVMart NVM


ReadRead--Write Memories (RAM)Write Memories (RAM)ReadRead Write Memories (RAM)Write Memories (RAM)STATIC (SRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

DYNAMIC (DRAM)

Periodic refresh requiredSmall (1-3 transistors/cell)( )SlowerSingle Ended


66--transistor CMOS SRAM Cell transistor CMOS SRAM Cell

WL

VDDDD

M

M4M2

QQM5

M6

M M

Q

BL

M1 M3

BL BLBL


CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)WL

BL

VDD

M

M 4BL

Q 1Q = 0

M 5M 6

M1 VDDVDD VDD

Q = 1

Cbit Cbit


CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)

1

1.2

0.6

0.8

Ris

e (V

)

0 2

0.4

l i [ ]Volta

ge R

00

0.2

0 5

Voltage rise [V]

1 1 2 1 5 2 2 5 3

V

0 0.5 1 1.2 1.5 2Cell Ratio (CR)

2.5 3


CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) V

WL

Q = 0

M4

M6

VDD

Q 0Q = 1

M1

M56

VBL = 1 BL = 0

VDD


CMOS SRAM Analysis (Write)CMOS SRAM Analysis (Write)CMOS SRAM Analysis (Write)CMOS SRAM Analysis (Write)


6T6T--SRAM SRAM —— Layout Layout 6T6T SRAM SRAM Layout Layout VVDD

M4M2

QQQ

M1 M3

GND

WLM5 M6

BLBL


ResistanceResistance--load SRAM Cellload SRAM CellResistanceResistance load SRAM Cellload SRAM CellWL

RL RL

VDD

M3Q Q

M4

BL BLM1 M2BL BL

Static power dissipation -- Want R L largeBit lines precharged to VDD to address tp problem


SRAM CharacteristicsSRAM CharacteristicsSRAM CharacteristicsSRAM Characteristics


33--Transistor DRAM CellTransistor DRAM CellBL1 BL2

WWL

RWL WWL

M1 X

M3

M2VDD 2 VTX

RWL

M2

CSV DD

DVV DD 2 VTBL 2

BL 1

V DD 2 VTBL 2

No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn


g WWL Tn

3T3T--DRAM DRAM —— LayoutLayout3T3T DRAM DRAM LayoutLayout

BL2 BL1 GND

RWLM3

WWL

M2

WWLM1


11--Transistor DRAM CellTransistor DRAM Cell11 Transistor DRAM CellTransistor DRAM Cell


DRAM Cell ObservationsDRAM Cell ObservationsDRAM Cell ObservationsDRAM Cell Observations1T DRAM requires a sense amplifier for each bit line, due

t h di t ib ti d tto charge redistribution read-out.DRAM memory cells are single ended in contrast to

SRAM cellsSRAM cells.The read-out of the 1T DRAM cell is destructive; read

and refresh operations are necessary for correctand refresh operations are necessary for correct operation.

Unlike 3T cell, 1T cell requires presence of an extraUnlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.

When writing a “1” into a DRAM cell, a threshold voltage g , gis lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD


Sense Amp OperationSense Amp OperationSense Amp OperationSense Amp Operation

V(1)VBL

DV(1)VPRE

DV(1)

V(0)tSense amp activatedp

Word line activated


11--T DRAM CellT DRAM CellCapacitor

M1 wordlineMetal word line

Diff d

Metal word lineSiO2

Field Oxide+ +

Poly

Diffusedbit line

Polysilicon Polysiliconplate

Poly

Field Oxiden+ n+

Inversion layerinduced byplate bias gate plate

Cross-section Layout

plate bias

Uses Polysilicon-Diffusion CapacitanceExpensive in Area


Expensive in Area

SEM of polySEM of poly--diffusion capacitor 1Tdiffusion capacitor 1T--DRAMDRAMp yp y pp


Advanced 1T DRAM CellsAdvanced 1T DRAM CellsAdvanced 1T DRAM CellsAdvanced 1T DRAM CellsCapacitor dielectric layerCell plate

Word lineInsulating Layer

Cell Plate Si

Insulating Layer

Cell Plate Si

Capacitor Insulator Refilling PolyIsolationTransfer gate

Storage electrodeCapacitor Insulator

Storage Node Poly

g y

Si Substrate

Storage electrode

2nd Field Oxide

Si Substrate

T h C ll Stacked capacitor Cell


Trench Cell Stacked-capacitor Cell

Static CAM Memory CellStatic CAM Memory CellStatic CAM Memory CellStatic CAM Memory Cell

BitWord

Bit Bit Bit

M8 M9Bit Bit

CAM ••• CAMM7M6

M4 M5

••• •••CAM

Word

M2M3int

SWord

••• CAM

S

Match M1

M2M3

Wired-NOR Match Line


CAM in Cache MemoryCAM in Cache Memoryyy

CAM SRAM

Hit LogicARRAY

SRAM

ARRAY

Address Decoder

g

Input Drivers Sense Amps / Input Drivers

Tag HitAddress DataR/W


PeripheryPeripheryPeripheryPeriphery

DecodersSense AmplifiersInput/Output BuffersInput/Output BuffersControl / Timing Circuitryg y


Row DecodersRow DecodersRow DecodersRow DecodersCollection of 2M complex logic gatesg gOrganized in regular and dense fashion

(N)AND Decoder(N)AND Decoder

NOR Decoder


Hierarchical DecodersHierarchical DecodersMulti-stage implementation improves performance

• • •

WL 1

WL 0

1

A2A3

WL 0

A2A3A2A3A2A3A0A1A0A1A0A1A0A1

• • •

NAND decoder usingNAND decoder using

A2A2A3 A3A0A0A1 A1

gg22--input preinput pre--decodersdecoders


Dynamic DecodersDynamic Decodersyy

P h d iPrecharge devices GND

WL3

GND

WL3

VDD

VDDWL3

WL2

WL

WL 2VDD

WL1

WL0

WL 1

WL 0

VDD

VDD φ A0A0 A1A1φA0A0 A1A1

0

2-input NOR decoder 2-input NAND decoder


44--input passinput pass--transistor based column transistor based column decoderdecoder

BL 0 BL 1 BL 2 BL 3

A0S0

S1

A1

S2

S

2-input NOR decoder

A1 S3

Advantages: speed (t does not add to overall memory access time)

D

Advantages: speed (tpd does not add to overall memory access time)Only one extra transistor in signal path

Disadvantage: Large transistor count


44--toto--1 tree based column decoder1 tree based column decoderBL 0 BL 1 BL 2 BL 3

A 0A 0

A 0

A1

AA 1

Number of devices drastically reducedD

Number of devices drastically reducedDelay increases quadratically with # of sections; prohibitive for large decoders

buffersprogressive sizingcombination of tree and pass transistor approaches

Solutions:


combination of tree and pass transistor approaches

D d f i l hiftD d f i l hift i ti tDecoder for circular shiftDecoder for circular shift--registerregister

V V V V V VV DD

WL 0

V DD

f

V DD

WL 1

V DD

f

V DD

WL 2

V DD

f

V DD

R f

ff

f R f

ff

f R f

ff

f• • •

V DD


Sense AmplifiersSense AmplifiersSense AmplifiersSense Amplifiersmake ΔV as small

tpC ΔV×

Iav----------------=

make V as smallas possible

smalllarge

Idea: Use Sense AmpliferIdea: Use Sense Amplifer

smalls.a.

smalltransition

outputinput


Differential Sense AmplifierDifferential Sense AmplifierDifferential Sense AmplifierDifferential Sense AmplifierVDD

M 4M 3

M M bibi

Outy

M 1 M 2 bitbit

M 5SE

Directly applicable toSRAMs


Differential Sensing ― SRAMDifferential Sensing ― SRAM


LatchLatch--Based Sense Amplifier (DRAM)Based Sense Amplifier (DRAM)EQ

VDD

BL BL

VDD

SE

SE

Initialized in its meta-stable point with EQOnce adequate voltage gap created, sense amp enabled with SEP iti f db k i kl f t t t t bl ti i t


Positive feedback quickly forces output to a stable operating point.

ChargeCharge--Redistribution AmplifierRedistribution Amplifiergg


ChargeCharge--Redistribution Amplifier―Redistribution Amplifier―EPROMEPROMEPROMEPROM VDD

SE LoadOut

M4

CascodedeviceVcasc

CoutM3

WLCColumndecoder

Ccol

MWLC decoder

BL

M2

EPROMarray

BL

WLCBLM1


Si lSi l tt Diff ti l C iDiff ti l C iSingleSingle--toto--Differential ConversionDifferential Conversion


Open bitline architecture with Open bitline architecture with d lld lldummy cellsdummy cells

L L L V

EQ

L L 1 L 0 R0 R1 LV DD

SE

BLL BLR

CS CS CS CS CS CS

… …SE

Dummy cell Dummy cellDummy cell Dummy cell


DRAM Read Process with Dummy CellDRAM Read Process with Dummy Cell3

2

3

22

1 VBL

BL

2

1VBL

BL

00 1 2 3

t (ns)

00 1 2 3

t (ns)

reading 03

EQ WL

reading 1

2

1V SE

00 1 2 3

t (ns)


t (ns)

control signals

Voltage RegulatorVoltage RegulatorVoltage RegulatorVoltage Regulator

VDD

VREF

Mdrive

VDL

Vbias

Equivalent Model

-

+Mdrive

VREF

VDL


Charge PumpCharge PumpCharge PumpCharge Pump


DRAM TimingDRAM TimingDRAM TimingDRAM Timing


RDRAM ArchitectureRDRAM ArchitectureRDRAM ArchitectureRDRAM ArchitectureBus

ClocksBus

memoryarray

Databus

k k 3 larray

mux/demuxnetwork

Columnpacket dec.demux

Rowdemux packet dec.


Address Transition DetectionAddress Transition DetectionAddress Transition DetectionAddress Transition Detection

DELAY

VDD

DELAYtdA0

DELAY

ATD ATD

DELAYtdA1

DELAYtdAN2 1

…


Reliability and YieldReliability and YieldReliability and YieldReliability and Yield


Sensing Parameters in DRAMSensing Parameters in DRAMSensing Parameters in DRAMSensing Parameters in DRAM1000 CD(1F)CD(1F)

Q

V smax (mv)

100

DD,Vsmax CS(1F)

Q S(1C)

10S,CS,VDD

CD,QS

VDD (V)Q S 5 CS V DD /2V smax 5 Q S / (CS 1 CD)

4K 64K 1M 16M 256M 4G 64GMemory Capacity (bits /chip)

smax S S

© Digital Integrated Circuits2nd MemoriesFrom [Itoh01]

Memory Capacity (bits /chip)

Noise Sources in 1T DRamNoise Sources in 1T DRamNoise Sources in 1T DRamNoise Sources in 1T DRamb t t

a particles

BL substrate Adjacent BLCWBL

a -particles

WL

leakage CS

electrode

Ccross


Open BitOpen Bit--line Architecture line Architecture ——Cross CouplingCross CouplingOpen BitOpen Bit line Architecture line Architecture Cross CouplingCross Coupling

EQ

WL 1

BLCWBL CWBL

WL 0 WL D WL D WL 0 WL 1

BL

SenseAmplifierC

BL

CBLCC C

CBLC C

BL


F ld dF ld d Bitli A hit tBitli A hit tFoldedFolded--Bitline ArchitectureBitline Architecture


TransposedTransposed--Bitline ArchitectureBitline Architecturepp


AlphaAlpha--particles (or Neutrons)particles (or Neutrons)AlphaAlpha--particles (or Neutrons)particles (or Neutrons)i l

WL V DD

a -particle

BL

V DD

SiO 2n 1SiO 21

1 22

2

1111

22

2

1 Particle ~ 1 Million Carriers


YieldYieldYieldYield

Yi ld t diff t t f t itYield curves at different stages of process maturity(from [Veendrick92])


RedundancyRedundancyRedundancyRedundancyRow

Redundantrows

RowAddress

Redundantcolumns

FuseBank:

MemoryArray

columns

Row DecoderColumnColumn Decoder ColumnAddress


ErrorError--Correcting CodesCorrecting CodesggExample: Hamming Codes

with

e.g. B3 Wrong

with

1

31

0

= 3

0


Redundancy and Error CorrectionRedundancy and Error CorrectionRedundancy and Error CorrectionRedundancy and Error Correction


Sources of Power Dissipation in Sources of Power Dissipation in M iM iMemoriesMemories

VDD

CHIP

nC DE VINT f m

IDD 5 SCiDVif1S IDCP

selectedCPTVINT f miact

IDCP n

ROWDEC

non-selected

C V f

ARRAYm(n 2 1)ihld

PERIPHERY COLUMN DECmC DE VINT f

V


VSS

From [Itoh00]

Data Retention in SRAMData Retention in SRAM1.30u

1.10u

900n0.13 m CMOSm

700n

500n Factor 7leak

age

(A)

500n

300n

Factor 7

0.18 m CMOSm

I

100n

0.00 .600 1.20 1.80

VDD

SRAM leakage increases with technology scaling


g gy g

Suppressing Leakage in SRAMSuppressing Leakage in SRAMSuppressing Leakage in SRAMSuppressing Leakage in SRAMVVDD

VDD VDDL

sleeplow-threshold transistor

SRAM SRAM SRAM

VDD,intVDD,int

sleep

SRAMcell

SRAMcell

SRAMcell

V

SRAMcell

SRAMcell

SRAMcell

VSS,intsleep

Reducing the supply voltageReducing the supply voltageInserting Extra ResistanceInserting Extra Resistance


Data Retention in DRAMData Retention in DRAM


From [Itoh00]

C St diC St diCase StudiesCase Studies

Programmable Logic ArraySRAMSRAM Flash Memoryy


PLA versus ROMPLA versus ROMPLA versus ROMPLA versus ROMProgrammable Logic Arraystructured approach to random logicstructured approach to random logic“two level logic implementation”

NOR-NOR (product of sums)NAND NAND (sum of products)NAND-NAND (sum of products)

IDENTICAL TO ROM!

Main differenceROM: fully populatedPLA l iPLA: one element per minterm

Note: Importance of PLA’s has drastically reduced1. slow2. better software techniques (mutli-level logic

synthesis)


y )But …

Programmable Logic ArrayProgrammable Logic Array

GND GND GND GNDV DD

Pseudo-NMOS PLA

GND GND GND GND GND

GND

GND

V DD X 0X 0 X 1 f0 f1X 1 X 2X 2

AND plane OR plane


AND-plane OR-plane

Dynamic PLADynamic PLAyyGND VDD

ANDf

ORf

fORf

GNDVDD X 0X 0 X 1 f0 f1X 1 X 2X 2

ANDf

AND-plane OR-plane


Clock Signal Generation Clock Signal Generation for selffor self--timed dynamic PLAtimed dynamic PLA

f ff

f

t tf AND

ff ANDDummy AND row

tpre teval f AND

f OR

f ORDummy AND row

(a) Clock signals (b) Timing generation circuitry


PLA LayoutPLA LayoutPLA LayoutPLA LayoutVDD GNDφ

And-Plane Or-Plane

f0 f1x0 x0 x1 x1 x2 x2Pull-up devices Pull-up devices


Pull up devices Pull up devices

4 Mbit SRAM4 Mbit SRAMHi hi l W dHi hi l W d li A hili A hiHierarchical WordHierarchical Word--line Architectureline Architecture


BitBit--line Circuitryline CircuitryBitBit line Circuitryline CircuitryBlock

Bit-lineload

select ATD

BEQ

Local WL

Memory cell

B /T B /T

I/O liI/O

B /T

CDCD CD

B /T

I/O line

Sense amplifierI/O


Sense Amplifier (and Waveforms)Sense Amplifier (and Waveforms)

I /O I /O

Address

I /O I /O

Blockselect ATD

SEQATD

BS

BSSA SA I/O Lines

BEQ

Vdd

SEQ

SEQSEQ

GND

DATA

SEQ SEQ

Dei

SA, SAVdd

GND

BS

Data cut

DATA


Data-cut

1 Gbit Flash Memory1 Gbit Flash Memory1 Gbit Flash Memory1 Gbit Flash Memory

© Digital Integrated Circuits2nd MemoriesFrom [Nakamura02]

Writing Flash MemoryWriting Flash MemoryWriting Flash MemoryWriting Flash Memory

Read

Number of cells

From [Nakamura02]


125125mmmm22 1Gbit NAND Flash Memory1Gbit NAND Flash Memoryyy

ache

32 word lines m

m

uffe

r & c

e pu

mp x 1024 blocks

10.7

m

Pag

e bu

Cha

rge

2kB

P

16896 bit lines

11 7mm


11.7mm

From [Nakamura02]

125125 22 1Gbit NAND Fl h M1Gbit NAND Fl h M125125mmmm22 1Gbit NAND Flash Memory1Gbit NAND Flash MemoryTechnology 0.13μm p-sub CMOS triple-well

1poly, 1polycide, 1W, 2AlC ll i 0 077 2Cell size 0.077μm2Chip size 125.2mm2Organization 2112 x 8b x 64 page x 1k blockOrganization 2112 x 8b x 64 page x 1k blockPower supply 2.7V-3.6VCycle time 50nsRead time 25μsProgram time 200μs / pageE ti 2 / bl kErase time 2ms / block

© Digital Integrated Circuits2nd MemoriesFrom [Nakamura02]

Semiconductor Memory TrendsSemiconductor Memory Trends( t th 90’ )( t th 90’ )(up to the 90’s)(up to the 90’s)

Memory Size as a function of time: x 4 every three years


Semiconductor Memory TrendsSemiconductor Memory Trends( d t d)( d t d)(updated)(updated)


Trends in Memory Cell AreaTrends in Memory Cell AreaTrends in Memory Cell AreaTrends in Memory Cell Area


Semiconductor Memory TrendsSemiconductor Memory TrendsSemiconductor Memory TrendsSemiconductor Memory Trends

Technology feature size for different SRAM generations


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