Elmore Delay, Logical Effort. Modern Interconnect © Rabaey, ch4Wire.ppt, slide 22.
Lecture 8: Circuit Simulations · 4 Logical Effort: Extract τ • Recall τ is the coefficient of...
Transcript of Lecture 8: Circuit Simulations · 4 Logical Effort: Extract τ • Recall τ is the coefficient of...
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Lecture 8: Circuit Simulations
• Circuit Characterization (Brief)
• Reading: Ch. 5
IV curves: Basic Shapes • IDS vs VDS (two regions)
– Linear (Low VDS) • Effective Resistance
– Saturated (High VDS) • Current, gm, gds
• IDS vs VGS – Linear IDS (above threshold) – Log (IDS) (below threshold)
2
SPICE Level 1 Model • Shichman-Hodges Model (Schichman68)
– Similar to Shockley model, but with channel length modulation and body effect
( )
( )( )⎪⎪⎪
⎩
⎪⎪⎪
⎨
⎧
−>−⋅+
−<⎟⎠
⎞⎜⎝
⎛−−⋅+
<
=
saturationVVVVVVLAMBDALWKP
linearVVVVVVVVLAMBDALWKP
cutoffVV
I
tgsdstgsdseff
eff
tgsdsdsds
tgsdseff
eff
tgs
ds
212
21
0
SPICE Level 1 Model • SPICE Level 1 Model
• SPICE Level 2 and 3 – Includes velocity saturation, mobility degradation, subthreshold
conduction, drain induced barrier lowering • BSIM Models
– Berkeley Short-Channel IGFET Model (BSIM) – IGFET – Insulated Gate Field Effect Transistor (i.e. MOSFET) – BSIM 3.v3 = SPICE level 49
• More then 100 parameters and device equations!
( )PHIVPHIGAMMAVTOV sbt ++⋅+=MJSW
sbMJ
sbsb PHP
VCJSWPSPBVCJASC
−−
⎟⎠
⎞⎜⎝
⎛+⋅⋅+⎟
⎠
⎞⎜⎝
⎛+⋅⋅= 11
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Fanout-of-4 inverter delay
• P/N ratio 2:1 – 1 means 1xWmin, 2
means 2xWmin,… – L=2lamda (always)
• X2 is upsized by 4x – 8 means 8xWmin…
• Device under test placed in the middle – Realistic input and
output slopes • Find tpdr and tpdf
Copyright © 2005 Pearson Addison-Wesley. All rights reserved. 5-10
a b c d eX1 X2 X3 X41
2
4
8
16
32
64
128 fX5256
512
Shape input
DeviceUnderTest Load
Load onLoad
Optimization
• Example: Best P/N ratio – We’ve assumed 2:1 gives equal rise/fall delays – But we see rise is actually slower than fall – What P/N ratio gives equal delays?
• P/N ratio for equal delay is 3.6:1 – tpd = tpdr = tpdf = 84 ps (slower than 2:1 ratio) – Big pMOS transistors waste power too – Seldom design for exactly equal delays
• What ratio gives lowest average delay? – P/N ratio of 1.4:1 – tpdr = 87 ps, tpdf = 59 ps, tpd = 73 ps
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Logical Effort: Extract τ • Recall τ is the coefficient of h
(i.e. slope) in a delay vs. fanout plot for an inverter
• Logical effort for INV g=1 a b c d e X1 X2 X3 X4
M=1
f X5
Shape input
Device Under Test Load
Load on Load
M=h M=h2 M=h3 M=h4
0 15 30 45 60
75 90
105 120
0 2 4 6 8 10 h
d abs
dabs=(gh+p) τ dabs=(h+p)τ
τ = 15 ps
Logical Effort Plots • Logical effort can be measured
from simulation • Plot tpd vs. h
– Normalize by τ – y-intercept is parasitic delay – Slope is logical effort
• Delay fits straight line very well in any process as long as input slope is consistent
0
20
40
60
80100
120
140
160
180
0 2 4 6 8 10
h
dabs
τ = 15 ps
dabs=16.7h + 28.9ps
gNAND=16.7/15=1.11 pNAND=28.9/15=1.93
X1 X2 X3 X4 X5
a b c d efM=1 M=h M=h2
M=h3M=h4
Shape input
DeviceUnderTest Load
Load onLoad
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Gate Capacitance (delay)
• Gate capacitance extraction (delay) – Effective gate capacitance for delay estimation – Example: Estimate fanout of 4 input capacitance
• Adjust capacitance Cdelay until c-to-d delay equals c-to-g delay
Gate Capacitance (power) • Gate capacitance extraction (power)
– Effective gate capacitance for power estimation is higher than effective gate capacitance for delay estimation
• CGD is effectively doubled when wait long enough for drain to completely switch (Miller effect)
– Example: circuit for determining the effective gate capacitance of X1 for power estimation
• Apply voltage step and integrate the current into X1
Vdd
dttipowerC in
g∫=
)()(
Integrated over entire transition (delay is 50% point only)
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Parasitic Capacitance
• Parasitic Capacitance Extraction – Parasitic capacitance associated with drain or source includes
gate-to-diffusion overlap cap (Cgol) and area and perimeter cap Cjb and Cjbsw
Effective Resistance
• According to RC delay model, Unit transistor has gate cap C, parasitic cap Cd, resistance Rn (for nMOS) and resistance Rp (for pMOS)
• Find rising falling delays of fanout-of-h with 2:1 P/N ratio using Figure below
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Effective Resistance w/o Cd • Remove dependence on parasitic capacitance Cd • Calculate delay for h=3 and h=4, and subtract
( ) ( )
( ) ( ) CRCCRCCRt
CRCCR
CCR
t
ndndnpdf
pdp
dp
pdr
23333343
23333
2343
2
=+⋅⋅−+⋅⋅=Δ
=+⋅⋅−+⋅⋅=Δ
Summary
• Simple simulations to extract R, Cg, Cd
• More in Ch5