Lecture 7 AM - University of...

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Addressing Modes

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What is an Addressing Mode?

• An addressing mode is a way in which an operand is specified in an instruction.

• There are different ways in which an operand may be specified in an instruction.

• An operand may be specified using the immediate, direct, extended, indexed, and inherent modes.

• Different addressing modes are required in programs for processing implied numbers, constants, variables, and arrays.

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IMMEDIATE ADDRESSING MODEExample: ADDA IMM

ADDA #$33

# Signifies IMMediateaddressing mode (IMM)

$ Signifies Hexadecimal number

• Example instruction: ADDA #$33

• The addressing mode IMM is identified and distinguished from the other addressing modes by the # symbol.

• This instruction adds the 8-bit number $33 to ACCA. In RTL: A ← A + $33

• The previous value of ACCA is overwritten by the accumulated result of the addition, on purpose.• For example, if ACCA = $12 initially, then, after the instruction ADDA $33

executes, ACCA will have $45.

ADDA #51

No Symbol Signifies Decimal number

Can also be written as:

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• Preconditions: instruction (8B33) stored in memory and PC initialized to $0100• The first mop fetches the opcode.• The opcode 8B conveys the following information to the CCU, that:

1. It must do an ADD operation2. The 1st operand is ACCA3. The 2nd operand is specified using the IMM addressing mode.

• The 2nd mop performs the addition• It gets the 2nd operand by reading the 2nd byte of the instruction• It adds this byte to the present contents of ACCA• It stores the result in ACCA, thus overwriting the previous contents of ACCA.

PC MAR MEMORY OCR

33

0100 8BADD

0101

01001 1 1 ACCAIMM

8B

0102

01012 2 2 A + 33 → A

6

PC MAR MEMORY OCR

φ1

φ2

0102

0101 332 2 2 A + 33 → A

0100 01001

0101

1 8B 1ADDACCAIMM

8B

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GENERAL FORMAT (TEMPLATE) ADDA IMMEDIATE

Location Machine Code

0100 8B

0101

0102 Opcode of Next Instruction

PC MAR MEMORY OCR

0102

01012 2 2 A + → A

0100 01001

0101

1 8B 1ADDACCAIMM

8B

• Note that for the general format, the actual number to be loaded into ACCA is not specified; instead, a symbol ( ) is specified.

: 8-bit Immediate 2nd Operand.Represents 2 Hex Symbols.Represents any 8-bit Data.‘ ’ represents one Hex symbol, i.e., 4-bits.‘ ’: immediate, immediate

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ADDA IMM68HC11 Data Sheet Information (From course web site)

• “ADDA IMM” means “Add memory (M) to ACCA”, and store the result in ACCA: A + M → A

• The “memory” term in “Add memory to ACCA” refers to the 2nd byte (ii) of the instruction: 8B ii

• The 1st operand is implied to be ACCA.

• The 2nd operand is actually stored in the instruction, so when the μP fetches the specification of the 2nd operand, the 2nd operand is available immediately, hence the name IMM.

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ADDA IMM68HC11 Data Sheet Information (From course web site)

• The template of the complete instruction is encoded as: 8B ii

• Note that when you provide the machine code of an instruction, you will replace the with the actual value you want to load into ACCA.• E.g: ADDA #$33 8B 33

• It takes 2 clock cycles to execute, and two bytes to store.

• The NZVC bits in the CCR are updated, as indicated by the “delta” symbol, which means that these bit will either be set or clear, depending on the result of the instruction.

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IMM ADDRESSING MODE2nd OPERAND IS A CONSTANT


0100 8B

0101 ii

0102 Next Opcode

• A program (list of instructions) is stored in non-volatile memory (e.g., ROM, FLASH, or a hard disk).

• In the IMM addressing mode, the actual value of the 2nd

operand is stored in the instruction itself.

• This means that the 2nd operand cannot be changed once the program is written into ROM.• This is very clear in the case when the program is stored and run from a ROM.

• FLASH memories are considered ROM from the point of view of non-volatililty.

• Typically programs are copied from non-volatile memory (e.g., ROM, FLASH, and hard disk) to RAM because RAM has faster access times and programs run faster when they run from RAM.

• But, programs are never copied back to non-volatile storage.

• Thus, the 2nd operand must be treated as a constant, that cannot be changed in the program stored in ROM.

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IMM Mode SummaryIMM General Form: ADDA #$ii

ADDA #$33

# Signifies IMMediateaddressing mode (IMM), and # distinguishes IMMmode from other modes.

$ Signifies Hexadecimal

number

Address Data

00FF

0100 8B

0101 33

0102

…

From: Instruction set Manual

Memory

ii

A ← A + $33 = A + $33

General MachineCode

General Assembly Language

Form:For any

addressing Mode

8B 33

Example MachineCode

Example AssemblyLanguage

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• The IMM addressing mode is used when we know the value of the number we want to operate on and the value will not change, i.e., the number is a constant.

• The IMM addressing mode cannot be used when we require to add, subtract, or generally process variables.

• If we need to process variables, then we can use the Direct, Extended, or Indexed addressing modes.

– These addressing mode permit processing of variables.

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EXTENDED ADDRESSING MODEExample: ADDA EXT

ADDA $0133

The absence of the # symbol, together with a 16-bit address, signifies EXTended addressing mode (EXT)

• Example instruction: ADDA $0133

• The addressing mode EXT is identified and distinguished from the other addressing modes by the presence of a 16-bit address of the 2nd operand, and the absence of the # symbol to distinguish it from the IMM mode.

• This adds the contents of memory location $0133 to ACCA. In RTL: A ← A + ($0133)

• The previous value of ACCA is overwritten by the accumulated result of the addition, on purpose.• For example, if ACCA = $12 initially, and ($0133) = $10, then, after the

instruction ADDA $0133 executes, ACCA will have $22.

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ADDA EXTENDEDADDA EXT (Ex: ADDA $0133)

Location MachineCode

0100 BB

0101 01

0102 33

0103 Next Opcode

0100

0101

0102

0103

1 0100

0101

0102

0133

MARPC

1 BB

01

33

MEMORY

.

.

.

1 BB

OCR

2 2 2

0133

3 3 3

Temporary holding register

4

4

vv 4

ADDACCA

ACC AA + vv→ Α

EXT

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TIMING: EXTENDED ADDRESSING MODEEXAMPLE: ADDA $0133

φ1

φ2

0100

0101

0102

0103

1 0100

0101

0102

0133

MARPC

1 BB

01

33

MEMORY

.

.

.

1 BB

OCR

2 2 2

0133

3 3 3


4

4

vv 4

ADDACCA

ACC AA + vv→ Α

EXT

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ADDA EXT68HC11 Data Sheet Information (From course web site)

• “ADDA EXT” is a general description. It means add “memory” to ACCA, and store the result in ACCA: A + M → A

• “memory” refers to the contents of the address of the 2nd operand.

• The address of the 2nd operand is part of the instruction: BB hh ll

• The address of the 2nd operand is specified by 16-bits.

• The complete instruction is encoded as: BB hh ll

• It takes 4 clock cycles to execute.

• The NZVC bits in the CCR are updated, as indicated by the “delta” symbol.

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TIMING: TemplateEXAMPLE: ADDA $hhll

φ1

φ2

0100

0101

0102

0103

1 0100

0101

0102

0133

MARPC

1 BB

01

33

MEMORY

.

.

.

1 BB

OCR

2 2 2

0133

3 3 3


4

4

vv 4

ADDACCA

ACC AA + vv→ Α

EXThh

ll

hhll

hhll

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ADDA EXTMemory Access

• Since, the address of the 2nd

operand is specified by 16-bits, the EXT mode of addressing can access any single location in the entire memory space:

00000001…

00FE00FF01000101…

01FE01FF02000201…

FEFFFF00FF01…

FFFEFFFF

EntireMemorySpaceCentral

Processing Unit (CPU, i.e., μP)

Memory: RAM, ROM, FLASH,

etc,

Input/Output(I/O)

Controllers

ABUS

CBUS

DBUS

16 1616 8 8 8

64K x 8 Memory Space216 = 64K

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ADDA $0133

Absence of # and presence of 16-bit address signifies

EXTended addressing mode (EXT)


number

Address Data

00FF

0100 BB

0101 01

0102 33

…

0133 vv


Memory

hh

ll

A ← A + ($0133) = A + vv

General Form: ADDA $hhll

Assembly language Machine code

BB 01 33Example

Example

Template

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DIRECT ADDRESSING MODE• The EXT mode permits processing of variables in

any location of the memory space, since the 2nd

operand is specified by a 16-bit address.

• Sometimes, variables are stored in the 1st page of memory, which requires only an 8-bit address, since the high byte is always zero.

• The DIRect addressing mode is conceptually the same as the EXT mode, except that the address of the 2nd operand is specified using only 8-bits.

• The DIRect addressing mode can be used to access variables in the 1st page of memory, only.

• The DIR addressing is more efficient than the EXT mode because it requires less space to store, and it runs faster.

00000001…

00FE00FF01000101…

01FE01FF02000201…

FEFFFF00FF01…

FFFEFFFF

1st Page

2nd Page

256th Page

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DIRECT ADDRESSING MODEExample: ADDA DIR

ADDA $33

The absence of the # symbol, together with an 8-bit address, signifies DIRect addressing mode (DIR)

• Example instruction: ADDA $33

• The addressing mode DIR is identified and distinguished from the other addressing modes by the presence of an 8-bit address of the 2nd operand, and the absence of the # symbol to distinguish it from the IMM mode.

• This adds the contents of memory location $0033 to ACCA. In RTL: A ← A + ($0033)

• The previous value of ACCA is overwritten by the accumulated result of the addition.• For example, if ACCA = $12 and ($0033) = $10 initially, then, after the

instruction ADDA $33 executes, ACCA will have $22.

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ADDA DIRECT CYCLESExample: ADDA $33

• The 1st mop fetches the opcode.• The opcode 9B conveys the following information to the CCU,

that:1. It must do an ADD operation2. The 1st operand is ACCA3. The 2nd operand is specified by the DIR addressing mode.

0100

0101

1 0100

0101

MARPC1 9B

33

MEMORY1 9B

OCR

2 2

ADDACCA

01023

ACC A3 0033 3 vv A + vv→ Α

DIR

0033 Temporary holding register

2

3

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ADDA DIRECT CYCLESExample: ADDA $33

• The 2nd mop reads the 8-bit address (of the 2nd operand).• The 8-bit address is placed into the low byte of the THR• The high byte of the THR is set to zero.• Thus, the THR has generated the address of the 2nd operand.

• The 3rd mop reads the 2nd operand (vv) from memory using the THR as the address.• The 2nd operand is added to the current contents of ACCA.

0100

0101

1 0100

0101

MARPC1 9B

33

MEMORY1 9B

OCR

2 2

ADDACCA

01023

ACC A3 0033 3 vv A + vv→ Α

DIR


2

3

24

0100

0101

1 0100

0101

MARPC1 9B

33

MEMORY1 9B

OCR

2 2

ADDACCA

01023

ACC A3 0033 3 vv A + vv→ Α

DIR


2

3

ADDA DIRECT TemplateADDA DIR


0100 9B

0101 dd

0102 Opcode of Next Instruction

dd

dd: 8-bit Address of 2nd Operanddd: Represents 2 Hex Symbolsdd: “direct” “direct”dd: Any 8-bit direct address

vv

dd

dd

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TIMING: DIRECT ADDRESSING MODEEXAMPLE: ADDA $33

φ1

φ2

Fetch and execute steps for ADDA direct. Note that vv is an 8-bit variable. Note also that the address of vv is constant since it ($33) is stored in the instruction.

0100

0101

1 0100

0101

MARPC1 9B

33

MEMORY1 9B

OCR

2 2

ADDACCA

01023

ACC A3 0033 3 vv A + vv→ Α

DIR


2

3

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ADDA DIR68HC11 Data Sheet Information (From course web site)

• “ADDA DIR” is a general description. It means add “memory” to ACCA, and store the result in ACCA: A + M → A

• “memory” refers to the contents of the address of the 2nd operand.

• The address of the 2nd operand is stored in the instruction, as dd: 9B dd

• Unlike the default address size of 16-bits, the address of the 2nd operand is specified by 8-bits. The CCU automatically converts the 8-bit address to 16-bits by prepending zeroes: 00dd.

• The complete instruction is encoded as: 9B dd


• The NZVC bits in the CCR are updated, as indicated by the “delta” symbol.

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DIRect Addressing ModeLimitation

Limitation

• Since, the address of the 2nd

operand is specified by 8-bits (dd);

• And, since the CCU automatically converts the 8-bit address to 16-bits by prepending zeroes, 00dd;

• Then, the DIR addressing mode can access only the 1st

page of memory.

00000001…

00FE00FF01000101…

01FE01FF02000201…

FEFFFF00FF01…

FFFEFFFF

1st Page

2nd Page

256th Page

Memory Space

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ADDA $33

Absence of # and 8-bit address signifies DIRect addressing

mode (DIR).


number.

Address Data

0033 vv

…

0100 9B

0101 33

0102


Memory

dd

A ← A + ($0033) = A + vv

General Form: ADDA $dd


Example 9B 33Example

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ADDA DIR & EXTADDRESS OF 2nd OPERAND IS A CONSTANT

• A program is stored in non-volatile memory (e.g., FLASH).

• In the DIR and EXT addressing modes, the address of the 2nd operand is stored in the instruction itself.

• This means that the address of the 2nd operand cannot be changed once the program is written into ROM (Read Only Memory).

• Thus, the address of the 2nd operand is a constant.

• Note: programs are rarely executed in ROM. Typically, a program is copied from a ROM to RAM, and then run in RAM, because RAM memories are much faster than ROM memories. However, our assertion that instructions cannot be changed (and so the 2nd operand address cannot be changed) still holds.


0100 9B

0101 dd

0102 Next Opcode


0100 BB

0101 hh

0102 ll

0103 Next Opcode

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COMPARISON: ADDA DIR & EXTNUMBER OF STORAGE BYTES AND CLOCK CYCLES

• Accumulator DIR instructions require• 2 bytes to store• 3 cycles to execute• Can access only the 1st page of the memory space.

• Accumulator EXT instructions require• 3 bytes to store• 4 cycles to execute• Can access the entire memory space.


0100 9B

0101 dd

0102 Next Opcode


0100 BB

0101 hh

0102 ll

0103 Next Opcode

ADDA DIR

ADDA EXT

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PROCESSING LISTS OR ARRAYS

• The DIR and EXT addressing modes cannot be used when we require to change the address of variables.– This is because the address of the variable is stored inside the

instruction, and the instruction cannot be changed.

• For example, to process a list of numbers, stored in memory in sequential order, the address of the numbers needs to be incremented.

• In this case, we can use the INDexed addressing mode.

• This addressing mode permits changing the effective address of the 2nd operand.

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Indexed Addressing ModeGeneral Form, Accumulator A Indexed X Addressing Mode: ADDA $ff,X

• The address of the 2nd operand is also called the “effective address.”

• The effective address is computed (generated) by:– Value of the index register X + the unsigned 16-bit extension of the offset.

• For example, if X=1000, (1080) = , then, the ADDA $80,X instruction:

$ff,X signifies INDexed addressing

mode (IND).

$ Signifies that the offset is

specified by a Hexadecimal

number

X Signifies using the Indexed X

addressing mode (other is Y).

ADDA $ff,XEA is formed by: X + 00ff

Effective Address

ff is the 8-bit unsigned offset

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Indexed Addressing ModeEffective Address is a Variable

• The address of the 2nd operand is a variable, since the value of index register X can be changed, through several different instructions.

• Examples of instructions that change the value of index register X:

LDX #$BEEF //Load the number $BEEF into X.INX //Increment X by one.DEX //Decrement X by one.

• Assumin the ADDA $80,X instruction follows this above sequence:

• Note that the offset cannot be changed, since it is part of the instruction.

Effective Address

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CYCLES of ADDA IND,XExample: ADDA $80,X

• For the above assume X=$0100, currently.

• The animation software shows how the effective address may be computed in the hardware.

• When explaining the timing, instead of using a specific example offset (i.e., $80) as in the above, we typically replace the number with a symbol, which in this case we use the symbol to denote the offset.


0100 AB

0101 80

0102 Next Opcode

0100

0101

0102

1 0100

0101

0180

MARPC

1 AB

80

MEMORY

.

.

.

1 AB

OCR

2 2 2

0100

4

Index Register X

vv 4ACC A

A + vv→ Α

ADDACCA

+

Offset

Effective Address (EA)

3

0080THR

INDEXED

0180 THR

0180 4

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“ADDA IND,X” TemplateADDA $ff,X


0100 AB

0101 ff

0102 Next Opcode

ff: Symbol for 8-bit unsigned offsetff: Represents 2 Hex symbolsff: offset offset

0100

0101

0102

1 0100

0101

0180

MARPC

1 AB

80

MEMORY

.

.

.

1 AB

OCR

2 2 2

0100

4

Index Register X

vv 4ACC A

A + vv→ Α

ADDACCA

+

Offset


3

0080THR

INDEXED

0180 THR

ff

ff

EFAD

00ff: 16-bit Unsigned Extension of ffEFAD: 16-bit Sum of THR + IXEFAD: Effective Address

Note: EFAD means EFfective ADdress

I am not specifying the contents of X,

nor I am specifying the actual offset.

EFAD

EFAD 4

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TIMING: INDEXED ADDRESSING MODEEXAMPLE: ADDA $ff,X

φ1

φ2

0100

0101

0102

1 0100

0101

0180

MARPC

1 AB

80

MEMORY

.

.

.

1 AB

OCR

2 2 2

0100

4

Index Register X

vv 4ACC A

A + vv→ Α

ADDACCA

+

Offset


3

0080THR

INDEXED

0180 THR

ff

ff

EFAD

EFAD

EFAD

EFAD 4

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ADDA IND68HC11 Data Sheet Information (From course web site)

• “ADDA IND” is a general description. It means add “memory” to ACCA, and store result in ACCA: A+M→A

• “memory” refers to the contents of the effective address of the 2nd operand.

• The effective address of the 2nd operand is formed by adding the unsigned extension of the offset to the current value of the index register. AB ff

• The offset is specified by 8-bits: it is assumed to be unsigned, by default.

• The complete instruction is encoded as: AB ff


• The NZVC bits in the CCR are updated accordingly, as indicated by the “delta” symbol.

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ADDA $01,X

$ff,X signifies INDex X

addressing mode (IND X).

$ Signifies offset represented as Hexadecimal

number.

Address Data

00FF

0100 AB

0101 01

0102

…

1001 vv


Memory

ff

A ← A + ($1001) = A + vv

General Form: ADDA $ff,X


AB 01Example

Example

Offset Indexregister X.

Assume X = 1000 currently.

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NON-MEMORY ACCESS INSTRUCTIONS• Sometimes, it is required to make a register zero, increment a

register, decrement a register, complement a register, negate a register, or transfer one register to another.

• In these cases, there are special instructions to do just that.

• For example: to make ACCA=0, we can use: CLRA

• These types of instructions use the Inherent (or Implied) addressing mode.

• The name Inherent or Implied was chosen because the 2nd

operand is implied by the opcode, and the 2nd operand does not need to be specified in the instruction.

40

INHERENT ADDRESSING MODEExample: CLRA INH (CLRA)


0100 4F

0101 Next Opcode

0100

0101

1 0100MARPC

1 4FMEMORY

1 4FOCR CLEAR

2ACC A

$00 → Α

ACCA00

CLRA

No Specification of operand means this instruction uses the

INHerent addressing mode (INH) A ← 0

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INH Mode Example: CLRAManual Assembly

CLRA

No Specification of operand implies

INHerent addressing mode (INH)

Address Data

00FF

0100 4F

0101

Memory

A ← 0

42

TIMING: INHERENT ADDRESSING MODEEXAMPLE: CLRA

PC MAR MEMORY OCR

0100 01001

0101

1 4F 1

φ1

φ2

2 00 → A

LOADACCA

04F

ACCA

43

CLRA INH68HC11 μP Peculiarities

• Clearly, setting N=0 and Z=1 makes a lot of sense.

• But, why is the V set to zero?

• Moreover, why is the C set to zero?

• The CLRA instruction does not seem to be an arithmetic instruction. It is more like a load instruction: LDAA #$00.

• Sometimes, the reason for doing this is a “Manufacturer’s design choice”.

• Another possible reason could be that when you clear A, you are clearing an accumulator, and so, it is like resetting the accumulation of arithmetic results; so, maybe we should reset the C and V bits as well.

44

EXAMPLES USES OF ADDRESSING MODES

• Now, let’s look at some examples.

45

ACCUMULATOR LOAD INSTRUCTIONS

ADDRESS CONTENTS… …

0400 010401 020402 FE

… …

ADDRESS CONTENTS… …

0093 AB0094 130095 EF

… …

INSTRUCTION COMMENT RTL

LDAA #$94 This loads the number $94 into ACCA. ACCA ← $94

LDAA $94 This loads the data located at $0094 into ACCA. ACCA ← ($0094) = $13

LDAA $0094 This loads ACCA with the data located at $0094. ACCA ← ($0094) = $13

LDAA $01,XThis loads ACCA with the data located at ($0001 + X). Since X = 03FF, then, this loads the data located at 0400 into ACCA.

ACCA ← (0001+X)ACCA ← (03FF+0001)ACCA ← 01

LDX #$03FF This loads the number $03FF into X. X ← $03FF

46

LOAD INSTRUCTIONS QUESTIONS

1. Write down two different instructions that load accumulator B with the contents of memory location $1234. You may assume a value for X.

2. Write down three different instructions that load accumulator B with the data located at $0034. You may assume a value for X.

3. Write down four different instructions that load the number 34 into Accumulator B. You may assume a value for X and make assumptions regarding contents of memory.

4. Describe the main purpose of each one of the micro-instructions for each instruction listed above.

5. Examine each micro-instruction for each instruction above. Are there any duplicate micro-instructions? If so, what are they?

47

DUPLICATE MOPS OF LDAA IMM, DIR, EXT, IND

MOP LDAA IMM LDAA DIR LDAA EXT LDAA IND

1 (PC) OCR (PC) OCR (PC) OCR (PC) OCR

2 (PC) A (PC) THRLB, 00 THRHB (PC) THRHB (PC) THRLB, 00 THRHB

3 (THR) A (PC) THRLB X + THR THR

4 (THR) A (THR) A

48

STORE INSTRUCTION QUESTIONS

6. Write down two instructions, each of which stores the data in accumulator A to location $1234. You may assume a value for X.

7. Write down three different instructions, each of which stores the data in accumulator A to location $0012. You may assume a value for X.

8. Describe the main purpose of each one of the micro-instructions for each instruction listed above.

9. Examine each micro-instruction for each instruction above. Are there any duplicate micro-instructions? If so, what are they?

49

ARITHMETIC AND LOGIC INSTRUCTION QUESTIONS

10.Write down an instruction that ADDs the data located at $0101 to Accumulator A.

11.Write down an instruction that ANDs the data located at $0101 to Accumulator A.

12.Describe the main purpose of each one of the micro-instructions for each instruction listed above.

13.Examine each micro-instruction for each instruction above. Are there any duplicate micro-instructions? If so, what are they? How many micro-instructions are different? Which micro-instruction(s) is(are) different?

50

ADDRESSING MODE QUESTIONS

15.Identify all information in the following:XXXX #12XXXX $12XXXX $1234XXXX $01,XXXX #1234XXX #$1234XXX $1234XXX $00,X

51

Example: Writing a Simple Assembly Language Program

• Problem: count the number of occurrences of $42 in data memory from address $1000 to $2000, inclusive.

• Solution:– Use ACCB to count the number.– Use X as an memory address pointer

7F013442…

00

…42

10001001

…

1FFF20002001

DataAddressMemory

clrbldx #$1000

loop ldaa $0,Xcmpa #$42bne skipincb

skip inxcpx #$2001bne loop

done bra done

ACCA

ACCB

52

Explanation• CLRB

– Accumulator B is used to count the number of occurrences of the number $42 in a block of memory, starting from $1000, and ending at $2000, inclusive.• Therefore, we need to initialize the counter B to zero.

• LDX #$1000– Index register X is used as a pointer, aka address, to point to the next Byte in the block to check.– Therefore, X needs to be initialized to the starting address of the block, which is $1000.

• LDAA $0,X– To determine if the data located at any element of the block is equal to $42, we need to copy the Byte (element) into Accumulator A first, because it is

not possible to check the memory location directly.– This instruction uses the Index X addressing mode ($00,X ) to specify the address of the 2nd operand. The effective address of the 2nd operand is

computed by the CPU as EA = X + 00ff, where ff is the offset of the instruction, which, in this case is $00; therefore the EA = $1000.• CMPA #$42

– Once the data has been loaded in Accumulator A, we can then check if it is equal to $42. We use the compare Accumulator A instruction to compare the contents of Accumulator A with the number $42.

• BNE skip– If Accumulator A is not equal to $42, then this instruction will cause the CPU to jump (aka branch) over the next instruction and continue with the one

that is located at line “skip”. If Accumulator A is equal to $42, then the CPU will not take the branch and execute the next instruction, which is to increment the counter.

• INCB– If Accumulator A is equal to $42, then the CPU will increment the counter, Accumulator B.

• INX– After checking and processing the current location in the block, the program needs to check the next location, and therefore, X is incremented by one.

• CPX #$2001– Index register X is incremented each time through the loop, on order to check each element of the block. The program needs to know if it has checked

all of the elements in the block. When X reach $2001, the program knows that all elements have been checked, and so the loop should be terminated.• BNE loop

– Each time through the loop, X is compared with $2001; if X is not equal to $2001, then the program will branch (jump) to address (line) “loop”, which will begin testing the next element of the block. When X reach $2001, the program knows that all elements have been checked, and so the branch will not be taken, and the loop is terminated.

• BRA done– This instruction executes it self forever, which is one way to stop a program from running.

53

14. Write down a sequence of instructions that store the multiple byte word $0123456789ABCDEF starting at location $0A00.– Using the BIG ENDIAN format

• Big end of the word stored at the lowest memory location– Using the LITTLE ENDIAN format

• Little end of the word stored at lowest memory location.

0123456789ABCDEF

0A000A01

…

DataAddressMemory

0A07

Big Endian

EFCDAB8967452301

0A000A01

…

DataAddressMemory

0A07Little Endian

Lecture 7 AM - University of...

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