Lecture 6 CES 522 Latches and Flip-Flops Jack Ou, Ph.D.

Lecture 6

CES 522Latches and Flip-Flops

Jack Ou, Ph.D.

Sequential Circuits

• New output are dependent on the inputs and the preceding values of outputs.

• Characteristic: output nodes are intentionally connected back to inputs.

• Basic sequential circuits:– Level Sensitive Circuits– Edge Sensitive Circuits

Small Perturbation to a Basic Inverter

Large Perturbation to a Basic Inverter

Application: SRAM

is pulled below VS to force the cell to switch via regenerative action.

Metastable Point

Small Perturbation from the Metastable Point

Intel’s Random Bit Generator

Latches

• Latches are level sensitive.• Latches propagate values from input to output

continuously.• S sets Q =1; R sets Q=1– Active low inputs are enabled by 0s.– Active high inputs are enabled by 1s.

SR Latch with NOR Gates

tPDSQ=2 NOR gate delays.tPDRQ_=1 NOR gate delay

Forbidden State

SR are trigger pulses which can return to zero once Q is set.

Active High inputs

SR Latch with NAND Gates

Active lowinputs

D Latch

D-latch Operation

D-Latch (CK=0)

0

D

DB

0

0

D-Latch (CK=1)

1

D

DB

D

DB D

DB

Analyze D Latch Using Boolean Algebra

𝐷 ∙𝐶𝐾

𝐷 ∙𝐶𝐾

𝐷 ∙𝐶𝐾 +𝑄

𝑄=𝐷 ∙𝐶𝐾 +𝑄

Transistor Level Implementation of D-Latch

𝐷 ∙𝐶𝐾 +𝑄𝐷 ∙𝐶𝐾 +𝑄

D-Latch (CLK=1,D=1)

VDD

VDD

0

Standard Library D LatchCLK=VDD (Q=D)

𝐷

𝐷 𝐷𝑄=𝐷

Standard Library D LatchCLK=0V (Hold State)

𝐷

𝑄 𝑄𝑄

JK Flip-Flop

JK Flip Flop (CK=0)

0

1

1𝑄

𝑄

JK Flip Flop (CK=1,J=K=0)

1

1

1𝑄

𝑄0

0

JK Flip Flop (CK=1,J=K=1)

1

1

1

If CK is on for a long time, the output of this JK flip flip will toggle!The pulse width of CK must be less than the propagationdelay time through the loop.

JK Flip Flop (CK=1,J=0→1,K=0)

1

1

𝑄=1

𝑄=00

1

𝑄=0

1

𝑄=1

Current: Next:

0

JK Flip Flop (CK=1,J=0 → 1,K=0)

1

1

𝑄=0→1

𝑄=1→00

𝑄=1→0

1

𝑄=0→1

Current: Next:

1

0

CK=1, J=0 → 1, K=0

• Regardless of initial value of Q, – CK=1, J= → 1, K=0 will set the updated value of Q

to a 1.

JK Flip Flop (CK=1,J=0,K= 0→ 1)

1

1

𝑄=0

𝑄=1

0

1

𝑄=1

1

𝑄=0

Current: 0Next:

0

JK Flip Flop (CK=1,J=0,K= 0→ 1)

11→0 →1

𝑄=1→0

1

0

1

𝑄=0→1

1

𝑄=1→0

Current: Next: 0

0

CK=1, J=0, K=0 → 1

• Regardless of initial value of Q, – CK=1, J= 0, K=0 → 1 will set the updated value of

Q to a 0.

JK Flip-Flop

J=1, K=1 can lead tooscillation if the width of CK is longer than propagation delay.

JK Master-Slave Flip-Flop

1

0

1

1

The slave latch is insulated from changes of J and K when CK=1 Q holds its current value.

The Q of the master latch is updated when CK=1.

JK Master-Slave Flip-Flop (CK=1)

1

0

1

1

𝑋

𝑋

J K

0 0


1

0

1

1

𝑋

𝑋

J K

1 1

1

1

𝑄

𝑄 𝑄

𝑄


1

0

1

1

J K

0 1 (Q=0)0(Q=1)

(Q=0)1(Q=1)

0

1

𝑄

𝑄 𝑄

1


1

0

1

1

J K

1 0 (Q=1) (Q=0)

(Q=1) (Q=0)

1

0

𝑄

𝑄

𝑄

1


J K

0 0

1 1

0 1 (Q=0)0(Q=1)

(Q=0)1(Q=1)

1 0 (Q=1) (Q=0)

(Q=1) (Q=0)


J K

0 0

1 0 (Q=1) (Q=0)

(Q=1) (Q=0)

0 0 (1 in this example)

(0 in this example)

If J catches a glitch, it is stuck the master latch!

1

0

Edge Sensitive Circuits

JK Negative Edge-Triggered Flip-Flop

1

𝐽𝑄

Active-Low Devices

1

1

Disabled

𝐾𝑄

“hold” mode


0

1

1

Active-Low Devices

1

1

“hold” modeenabled


1

1

“hold” mode

enabled →disabled

1 𝑡𝑃𝐷→

𝐽 𝑄


1

1→ 1

disabled→enabled disabled

1hold→update hold

CK

CK

The NAND latch is only updated for a short interval immediately after the negative edge, before being set to the hold.

1→1

Update

Jn Kn S= R= Qn+1

0 0 1 1

0 1 1

1 1

1 0 1

J=0; K=1Jn Kn S= R= Qn+1

0 1 1 0

0 1 1 0

0 1 1

J=1; K=0Jn Kn S= R= Qn+1

1 0 Q 1 1

0 1 Qn=0S=0

1 1

0 1 Qn=1S=1

1 Qn=1Qn+1=1

Negative Edge Triggered Flip-FLop

Jn Kn S= R= Qn+1

0 0 1 1

0 1 1 0

1 1

1 0 Q 1 1

D Flip-Flop

D-Flop

1 2

CK of latch 2

CK of latch 1

X

OUT=X

X=IN

1: Hold

2: Track

2:hold

1:track

OUT samples IN at the positive edge of the clock

Timing Diagram

Definition

• Setup time: the time that the incoming data must be stable before the clock arrives

• Hold time: the length of time that the data remains stable after the clock arrives for proper operation

• If the data is stable before the setup time and continues to be stable after the hold time, the flop will work properly.

• If the data arrives within the period designated by the setup and hold times, the flop may or may not capture the correct value.

CLK-Q

• The delay from the time that the clock arrives to the point that the output stabilizes.

• In reality the data must arrive at the setup time before the clock hits and the output is valid after the CLK-Q delay.

Lecture 6 CES 522 Latches and Flip-Flops Jack Ou, Ph.D.

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Transcript of Lecture 6 CES 522 Latches and Flip-Flops Jack Ou, Ph.D.