Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky...
Transcript of Lecture 6- Analog Layout layout and to minimize the resistance of the connection Dr. Mohamed Refky...
Lecture 6- Analog Layout
Dr. Mohamed Refky Amin
Electronics and Electrical Communications Engineering Department (EECE)
Cairo University
http://scholar.cu.edu.eg/refky/
Outline of this Lecture
• Previously on ELCN321
• Layout of a Single Transistor
• Matching of Transistors
• Layout of Resistors
• Layout of Capacitors
Dr. Mohamed Refky
Previously on ELCN321
Interconnect Parasitic Parameters
Capacitance
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Previously on ELCN321
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Interconnect Parasitic Parameters
Resistance
Previously on ELCN321
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Electrical Wire Models
Previously on ELCN321
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Elmore delay formula
Analog Layout
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Layout of a Single Transistor
Analog Layout
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Layout of a Single Transistor
Source and Drain Connections
Analog Layout
Single contact must be avoided to improve the reliability of the
layout and to minimize the resistance of the connection
Dr. Mohamed Refky
Layout of a Single Transistor
Source and Drain Connections
Analog Layout
Large contracts must be avoided because it may cause micro-
fractures and electromigration. This this causes reliability
problems
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Layout of a Single Transistor
Source and Drain Connections
Analog Layout
A single tie can be used every 2 transistors or more.
Double ties on both sides of a MOSFET can also be used.
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Layout of a Single Transistor
Substrate and Well Ties
Analog Layout
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Layout of a Single Transistor
Analog Layout
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Layout of a Single Transistor
Multiple Fingers Single Transistor
2
fingers
3
fingers
Analog Layout
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Example (1)
one finger 5 finger 8 finger
Analog Layout
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Example (1)
one finger 5 finger 8 finger
Analog Layout
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Example (1)
one finger 5 finger 8 finger
Analog Layout
Many analog circuits require high matching between the building
transistors
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Matching of Transistors
Process variations result in
mismatch between transistors
Mismatch Errors
Systematic
Errors
Random
Errors
Analog Layout
Small nearby devices are
dominated by random errors
Large nearby devices are
dominated by systematic
errors (process gradient)
Random errors are difficult to
mitigate.
Systematic errors can be
mitigated by layout techniques
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Matching of Transistors
Introduction
To match two transistors, parallel elements must be used becausesilicon is un-isotropic
The current should flow in the same direction in the twotransistors
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Matching of Transistors
Matching of One Finger Transistors
Introduction
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Matching of Transistors
Matching of One Finger Transistors
Introduction
Interdigitation is 1-dimension technique to overcome the
systematic mismatch due to process gradient
Common axis provide higher degree of matching
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Matching of Transistors
Matching of Multi-Fingers Transistors
Analog Layout
In interdigitation technique, the two transistors are spilt in an
equal part of fingers and then the fingers are interdigitated in a
balanced fashion
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Matching of Transistors
Matching of Multi-Fingers Transistors
AABBAABB ABBAABBA
Analog Layout
Common centroid is another technique to overcome the
systematic mismatch due to process gradient
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Matching of Transistors
Matching of Multi-Fingers Transistors
Cross coupling Tiling pattern
Analog Layout
Common-centroid is considered as a 2-dimension technique to
overcome the systematic mismatch
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Matching of Transistors
Matching of Multi-Fingers Transistors
Analog Layout
Sketch the layout of three interdigitated transistors having the
same width. The three transistors have the source in common.
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Assignment
Analog Layout
Ending elements have different boundary conditions than the
inner elements. This affect the matching of the transistors
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Matching of Transistors
Dummy Devices
Analog Layout
To overcome this problem, dummy transistors (one at each end)
are used
Dummies transistors are shorted transistors
Dummies transistors add parasitics to the circuit
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Matching of Transistors
Dummy Devices
Analog Layout
Stacked Layout is a systematic use of stack of transistors
In the same stack, fingers of same width are used to represent the
transistors, possibly different length
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Stacked Layout
Analog Layout
The design steps of the stacked layout are:
1) Examine the size of transistors in the cell
2) Split transistors size in a number of layout oriented fingers
3) Identify the transistors that can be placed on the same stack
4) Possibly change the size of non-critical transistors
5) Use (almost) the same number of finger per stack
6) Place stacks and interconnect
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Stacked Layout
Design procedure
Analog Layout
Use the stacked layout technique to layout the two stages OTA
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Example (3)
Analog Layout
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Example (3)
The width of the second and
third stack is 10
Analog Layout
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Example (3)
Analog Layout
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AssignmentUse the stacked layout technique to layout the two stages OTA
Analog Layout
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Layout of Resistors
Analog Layout
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Layout of Resistors
Diffused resistances have large
resistance
Diffused resistances have a
large voltage and temperature
coefficient
Diffused resistances are weakly
insulated from the surrounding
Diffused Resistances
Analog Layout
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Layout of Resistors
Poly is the most widely used material to implement resistance
Features of Resistors
Type of layerAccuracy
%
30 - 50 20 - 40 200 – 1k 50 - 300
50 - 150 20 - 40 200 – 1k 50 - 300
2k – 4k 15 - 30 5k 10k
3k – 6k 15 - 30 5k 10k
6k – 10k 25 - 40 10k 20k
9k – 13k 25 - 40 10k 20k
First poly 20 - 40 25 - 40 500 - 1500 20 - 200
Second poly 15 - 40 25 - 40 500 - 1500 20 - 200
Analog Layout
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Layout of Resistors
Resistance Calculations
Analog Layout
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Layout of Resistors
Resistance Calculations
Analog Layout
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Layout of Resistors
Absolute accuracy of the resistor is
controlled by the poly line edge-shift
during processing (PR dimensional
change, lateral etching, UV diffraction,
... etc)
As inaccuracy is almost the same in
the two resistors, matching accuracy is
very high
Accuracy of Resistors
Analog Layout
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Layout of Resistors
Accuracy of Resistors
Analog Layout
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Layout of Resistors
Accuracy of Resistors
Etching
Boundary
Side diffusivity
Implant dose
Side diffusivity
Deposition rate
Doping dose
Stress
Temperature
Analog Layout
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Layout of Resistors
Accuracy of Resistors
Analog Layout
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Layout of Resistors
Accuracy of Resistors
Accurate VLSI designs should depend on
resistance ratio rather than on absolute
resistance
Analog Layout
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Layout of Resistors
Temperature gradient on the
chip may produce thermal
induced mismatch.
Thus, nearby heat sources, the
orientation of the resistor can
affect the matching
Accuracy of Resistors
Analog Layout
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Layout of Resistors
Matching between resistances can be improved by using
interdigitation, common centroid, and dummy cell techniques
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Matching of Resistors
Analog Layout
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Layout of Capacitors
For integrated capacitors, the electrodes are usually made of
metal, polysilicon, or diffusion
The insulator are usually made of silicon oxide, polysilicon
oxide, or CVD oxide
Analog Layout
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Layout of Capacitors
Oxide damage
Impurities
Temperature
Bias condition
Stress
Analog Layout
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Layout of Capacitors
Accuracy of Capacitors
Analog Layout
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Layout of Capacitors
Accuracy of Capacitors
Capacitors with large perimeter
features (like zigzags) suffers from
low accuracy
Analog Layout
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Layout of Capacitors
Accuracy of Capacitors
Type of layerAccuracy
%
poly - diff 15 - 20 7 - 14 20 – 50 60 - 300
poly I - diff II 15 - 25 6 - 12 20 – 50 40 - 200
metal - poly 500 - 700 6 - 12 50 – 100 40 - 200
metal - diff 1200 - 1400 6 - 12 50 – 100 60 - 300
metal I- metal II 800 - 1200 6 - 12 50 – 100 40 - 200
Analog Layout
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Layout of Resistors
To achieve good matching between
capacitors, copies of unit capacitor
are used and are connected in parallel.
The unit capacitor are usually made
of a fairly large square
Matching accuracy of the capacitors
is better than that of the resistors
Matching of Capacitors
Analog Layout
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Layout of Resistors
Matching between capacitors can be
improved by using common centroid,
and dummy cell techniques
Matching of Capacitors