Lecture 5 Example Design 1 - University of Toronto
Transcript of Lecture 5 Example Design 1 - University of Toronto
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Lecture PlanDate Lecture (Wednesday 2-4pm) Reference Homework
2020-01-07 1 MOD1 & MOD2 PST 2, 3, A 1: Matlab MOD1&22020-01-14 2 MODN + Toolbox PST 4, B
2: Toolbox2020-01-21 3 SC Circuits R 12, CCJM 142020-01-28 4 Comparator & Flash ADC CCJM 10
3: Comparator2020-02-04 5 Example Design 1 PST 7, CCJM 142020-02-11 6 Example Design 2 CCJM 18
4: SC MOD22020-02-18 Reading Week / ISSCC2020-02-25 7 Amplifier Design 1
Project
2020-03-03 8 Amplifier Design 22020-03-10 9 Noise in SC Circuits2020-03-17 10 Nyquist-Rate ADCs CCJM 15, 172020-03-24 11 Mismatch & MM-Shaping PST 62020-03-31 12 Continuous-Time PST 82020-04-07 Exam2020-04-21 Project Presentation (Project Report Due at start of class)
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What you will learnโฆโข MOD2 implementationโข Switched-capacitor circuits
Switched-cap summer + DACโข Dynamic-range scalingโข kT/C noiseโข Verification strategy
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Review: A ADC System
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Review: MOD2
โข Doubling OSR improves SQNR by 15 dBPeak SQNR ~ ๐๐๐ฅ๐จ๐ ๐๐ ๐ ยท ๐ถ๐บ๐น๐ ๐ ๐โ
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Review: Simulated MOD2 PSDโข Input at 50% of FullScale
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Review: Advantages of โข ADC: Simplified Anti-Alias Filter
Since the input is oversampled, only very high frequencies alias to the passbandA simple RC filter often sufficesIf a continuous-time loop filter is used, the anti-alias filter can be often eliminated altogether
โข Inherent LinearitySingle-bit DAC structures can yield very high SNR
โข Robust Implementation tolerates sizable component errors
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Letโs Try Making Oneโข Clock at fS = 1 MHz, assume BW = 1 kHz
OSR = fS / 2๊BW = 500 ~ 29
โข MOD1: SQNR ~ 9 dB/octave x 9 octaves = 81 dBโข MOD2: SQNR ~ 15 dB/octave x 9 octaves = 135 dB
Actually more like 120 dBโข SQNR of MOD1 is not bad, but SQNR of MOD2 is
very goodIn addition to MOD2โs SQNR advantage, MOD2 is usually preferred over MOD1 because MOD2โs quantization noise is more well-behaved
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What Do We Need?
1. Summation blocks2. Delaying and non-delaying discrete-time
integrators3. Quantizer (1-bit)4. Feedback DACs (1-bit)5. Decimation filter (not shown)
Digital and therefore assumed to be easy
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Switched-Capacitor Integrator
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Switched-Capacitor Integrator
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Switched-Capacitor Integrator
โข Since ๐ธ๐ ๐ช๐๐ฝ๐๐ and ๐ธ๐ ๐ช๐๐ฝ๐๐๐
โข Voltage gain is controlled by a ratio of capacitors
With careful layout, 0.1% accuracy is possible
๐๐ ๐ ๐ ๐๐ ๐ ๐๐ ๐
๐๐ธ๐ ๐ ๐ธ๐ ๐ ๐ธ๐ ๐
๐ธ๐ ๐๐ธ๐ ๐๐ ๐
๐ฝ๐๐๐ ๐๐ฝ๐๐ ๐
๐ช๐/๐ช๐๐ ๐
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Summation + Integration
โข Adding an extra input branch accomplishes addition, with weighting
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1b DAC + Summation + Integration
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Differential Integrator
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Non-Delaying Integrator
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Non-Delaying Integrator
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Non-Delaying Integrator
โข Delay-free integrator (inverting)
๐๐ ๐ ๐ ๐๐ ๐ ๐๐ ๐ ๐
๐๐ธ๐ ๐ ๐ธ๐ ๐ ๐๐ธ๐ ๐
๐ธ๐ ๐๐๐ธ๐ ๐๐ ๐
๐ฝ๐๐๐ ๐๐ฝ๐๐ ๐
๐ช๐๐ช๐
๐๐ ๐
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Half-Delay Integrator
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Half-Delay Integratorโข Output is sampled on a different phase than the
input
โข Some use the notation ๐ฏ ๐ ๐๐/๐
๐ ๐to denote the
shift in sampling timeโข An alternative method is to declare that the
border between time n and n+1 occurs at the end of a specific phase, say 2
โข A circuit which samples on 1 and updates on 2is non-delaying (ie, ๐ฏ ๐ ๐/ ๐ ๐ ) whereas a circuit which samples on 2 and updates on 1 is delaying (ie, ๐ฏ ๐ ๐/ ๐ ๐ )
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Timing in a ADCโข The safest way to deal with timing is to construct
a timing diagram and verify that the circuit implements the desired difference equations
โข E.g. MOD2:
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Switched-Capacitor Realization
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Signal Swingโข So far, we have not paid any attention to how
much swing the op amps can support, or to the magnitudes of u, Vref, x1 and x2
โข For simplicity, assume:The full-scale range of u is +/- 1 VThe op-amp swing is also +/- 1 VVref = 1 V
โข We still need to know the ranges of x1 and x2 in order to accomplish dynamic-range scaling
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Dynamic-Range Scalingโข In a linear system with known state bounds, the
states can be scaled to occupy any desired range
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State Swings in MOD2โข Linear Theory
โข If ๐ is constant and ๐ is white with power ๐๐๐ ๐/๐, then ๐๐ ๐, ๐๐๐
๐ ๐๐๐๐ ๐/๐, ๐๐ ๐and ๐๐๐
๐ ๐๐๐๐ ๐/๐
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Simulated Histograms
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Observationsโข The match between simulations and our linear
theory is fair for x1, but poor for x2x1โs mean and standard deviation match theory, although x1โs distribution does not have the triangular form that would result if e were white and uniformly distributed in [-1, 1]x2โs mean is 50-100% high, its standard deviation is ~25% low, and the distribution is weird
โข Our linear theory is not adequate for determining signal swings in MOD2
No real surprise since linear theory does not handle overload (ie, where x1 or x2 go to infinity when u > 1)
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MOD2 Simulated State Bounds
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Scaled MOD2โข Take ๐๐ ๐ and ๐๐ ๐
The first integrator should not saturateThe second integrator will not saturate for dc inputs up to -3 dBFS and possibly as high as -1 dBFS
โข Our scaled version of MOD2 is
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First Integrator (INT1)โข Shared Input/Reference Caps
โข How do we determine C?
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kT/C Noise
โข Regardless of the value of R, the mean-square value of the voltage on C is
where k = 1.38 x 10-23 J/K is Boltzmannโs constant and T is the temperature in Kelvin
The mean square noise charge is ๐๐๐ ๐ช๐๐๐๐ ๐๐ป๐ช
๐๐๐๐๐ป๐ช
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Derivation of kT/C Noiseโข Noise in RC switch network
Noise PSD from R: ๐บ๐น ๐ ๐๐๐ป๐นTime constant of R-C filter: ๐ ๐น๐ชNoise voltage across C:
๐ฝ๐ช๐ ๐บ๐น ๐๐
๐ ๐๐
๐๐ ๐
๐
๐๐๐ป๐น๐
๐ ๐๐
๐๐ ๐
๐
๐๐๐ป๐น๐๐
๐๐ป๐ช
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Implications for a SC Integratorโข Each charge/discharge operation has a random
componentThe amplifier plays a role during phase 2, but weโll assume the noise in both phases is kT/C (we will revisit this in โNoise in SC Circuitsโ Lecture)
โข For a given cap these random components are essentially uncorrelated so the noise is white
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Implications for a SC Integratorโข The noise charge is equivalent to a noise voltage
with mean square value ๐๐๐ ๐๐๐ป/๐ช๐ added to the input of the integrator
โข This noise power is spread uniformly over all frequencies from 0 to fS/2
โข The power in the band from 0 to fB is ๐๐๐/๐ถ๐บ๐น
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Differential Noise
โข Twice as many switched caps twice as much noise power
โข The input-referred noise power in our differential integrator is
๐๐๐ ๐๐๐ป/๐ช๐
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INT1 Absolute Capacitor Sizesโข For SNR = 100 dB @ -3 dBFS input
The signal power is
Therefore we want ๐๐,๐ข๐ง๐๐๐ง๐๐ ๐.๐๐ ๐๐ ๐๐ ๐ฝ๐
Since ๐๐,๐ข๐ง๐๐๐ง๐๐ ๐๐๐/๐ถ๐บ๐น
โข If we want 10 dB more SNR, we need 10x caps
๐ช๐๐๐๐ป๐๐๐
๐.๐๐ ๐ฉ๐
๐๐๐๐๐ ยท
๐ ๐ฝ ๐
๐ ๐.๐๐ ๐ฝ๐
๐จ๐/๐๐ ๐๐๐ ๐
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Second Integrator (INT2)โข Separate Input and Feedback Caps
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INT2 Absolute Capacitor Sizesโข In-band noise of second integrator is greatly
attenuated
Capacitor sizes not dictated by thermal noise
โข Charge injection errors and desired ratio accuracy set absolute size
A reasonable size for a small cap is ~10 fF
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Behavioral Schematic
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Verificationโข Open-loop verification
1) Loop filter2) Comparator
Since MOD2 is a 1-bit system, all that can go wrong is the polarity and the timingUsually the timing is checked by (1) so this verification check is not needed
โข Closed-loop verification3) Swing of internal states4) Spectrum: SQNR, STF gain5) Sensitivity, start-up, overload recovery, โฆ
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Loop-Filter Checkโข Open the feedback loop, set u = 0 and drive an
impulse through the feedback path
โข If x2 is as predicted then the loop filter is correctAt least for the feedback signal, which implies that the NTF will be as designed
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Loop-Filter Check
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Impulse Responseโข An impulse is {1,0,0,โฆ}, but a binary DAC can
only output +/- 1 and cannot produce a 0
Q. How can we determine the impulse response of the loop filter through simulation?
A. Do two simulations: one with v = {-1,-1,-1,โฆ} and one with v = {+1,-1,-1,โฆ}, take the difference, divide by 2
With superposition the difference is v = {2,0,0,โฆ} and the result is divided by 2To keep the integrator states from growing too quickly, you could also use v = {-1,-1,+1,-1,โฆ} and then v = {+1,-1,+1,-1,โฆ}
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Simulated State Swingsโข -3 dBFS, ~300 Hz sine wave
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Unclear Spectrum
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Better Spectrum
โข SQNR dominated by -108 dBFS 3rd harmonic
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Implementation Summary1) Choose a viable SC topology and manually
verify timing2) Dynamic Range scaling
You now have a set of capacitor ratiosVerify operation: loop filter, timing, swing, spectrum
3) Determine absolute capacitor sizesVerify noise
4) Determine op-amp specs and construct a transistor-level schematicVerify everything
5) Layout, fab, debug, documentโฆ
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Differential vs Single-Endedโข Differential is more complicated and has more
caps and more noise single-ended is better?
โข Same capacitor area same SNRDifferential is generally preferred due to rejection of even-order distortion and common-mode noise/interference.
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Shared vs Separate Input Capsโข Separate caps more noise
โข Using separate caps allows input CM and ref CM to be different and is often preferred
Also improves linearity as reference feeds into separate node and wonโt introduce signal dependent error
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Single-Ended Inputโข Shared Caps
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What You Learned Todayโข MOD2 implementationโข Switched-capacitor integrator
Switched-cap summer & DAC tooโข Dynamic-range scalingโข kT/C noiseโข Verification strategy