Lecture 4: CMOS Transistor Theorykmram/1192-2192/lectures/... · 2017. 8. 31. · q MOS structure...
Transcript of Lecture 4: CMOS Transistor Theorykmram/1192-2192/lectures/... · 2017. 8. 31. · q MOS structure...
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Introduction to CMOS VLSI
Design
Lecture 4: CMOS Transistor Theory
David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan
University of Pittsburgh
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 2
Outline q Introduction q MOS Capacitor q nMOS I-V Characteristics q pMOS I-V Characteristics q Gate and Diffusion Capacitance q Pass Transistors q RC Delay Models
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 3
Introduction q So far, we have treated transistors as ideal switches q An ON transistor passes a finite amount of current
– Depends on terminal voltages – Derive current-voltage (I-V) relationships
q Transistor gate, source, drain all have capacitance – I = C (ΔV/Δt) -> Δt = (C/I) ΔV – Capacitance and current determine speed
q Also explore what a “degraded level” really means
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© Digital Integrated Circuits2nd Devices
MOS Transistors - Types and Symbols
D
S G
D
S G
G S
D D
S G
NMOS Enhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS with Bulk Contact
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The MOS Transistor
Polysilicon Aluminum
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Controlling current flow in an nFET.
Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.
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© Digital Integrated Circuits2nd Devices Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.
Controlling current flow in a pFET.
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© Digital Integrated Circuits2nd Devices
What is a Transistor?
VGS ≥ VTR o n
S D
A Switch!
|V GS |
A MOS Transistor
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I-V Curves
Resistor I = V/R
Diode I = Is*exp(k*V-Vt)
Current (I) vs. Voltage (V) I = f(V)
0 0.5 1 1.5 2 2.5 0
1
2
3
4
5
6 x 10 -4
V DS
I D (A)
MOS I = f(Vgs, Vds)
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 10
Terminal Voltages q Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs – Vgd = Vg – Vd – Vds = Vd – Vs = Vgs - Vgd
q Source and drain are symmetric diffusion terminals – By convention, source is terminal at lower voltage – Hence Vds ≥ 0
q nMOS body is grounded. First assume source is 0 too. q Three regions of operation
– Cutoff – Linear – Saturation
Vg
Vs Vd
VgdVgs
Vds+-
+
-
+
-
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 11
MOS Capacitor q Gate and body form MOS capacitor q Operating modes
– Accumulation – Depletion – Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg < 0
(b)
+-
0 < Vg < Vtdepletion region
(c)
+-
Vg > Vt
depletion regioninversion region
In general, MOS gate capacitance is not constant
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© Digital Integrated Circuits2nd Devices Copyright © 2005 Pearson Addison-Wesley. All rights reserved.
MOS Transistors – Operating regions
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 13
nMOS Cutoff q No channel q Ids = 0
+-
Vgs = 0
n+ n+
+-
Vgd
p-type body
b
g
s d
d
s
g
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 14
nMOS Linear q Channel forms q Current flows from d to s
– e- from s to d q Ids increases with Vds q Similar to linear resistor
+-
Vgs > Vt
n+ n+
+-
Vgd = Vgs
+-
Vgs > Vt
n+ n+
+-
Vgs > Vgd > Vt
Vds = 0
0 < Vds < Vgs-Vtp-type body
p-type body
b
g
s d
b
g
s d Ids
d
s
g
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© Digital Integrated Circuits2nd Devices
n+n+
p-substrate
D
SG
B
VGS
xL
V(x) +–
VDS
ID
MOS transistor and its bias conditions
Linear Region Vgs>Vt & Vgd>Vt
Positive Charge on Gate: Channel exists, Current Flows
since Vds > 0 Ids = k’(W/L)((Vgs-Vt)Vds-Vds2/2)
R Vgd
Vgs
Ids
Vds
I=V/R R= 1/(k’(W/L)(Vgs-Vt))
Ids
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 16
nMOS Saturation q Channel pinches off q Ids independent of Vds q We say current saturates q Similar to current source
+-
Vgs > Vt
n+ n+
+-
Vgd < Vt
Vds > Vgs-Vtp-type body
b
g
s d Ids
d
s
g
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© Digital Integrated Circuits2nd Devices
n+n+
S
G
VGS
D
VDS > VGS - VT
VGS - VT+-
Saturation: Vgs>Vt & Vgd 0 But: channel is “pinched off”
Ids = (k’/2)(W/L)(Vgs-Vt)2
Vgd
Vgs
Ids
Ids
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 18
I-V Characteristics q In Linear region, Ids depends on
– How much charge is in the channel? – How fast is the charge moving?
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© Digital Integrated Circuits2nd Devices Copyright © 2005 Pearson Addison-Wesley. All rights reserved.
MOS Transistors – Regions Transitions
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 20
Channel Charge q MOS structure looks like parallel plate capacitor
while operating in inversion – Gate – oxide – channel
q Qchannel =
n+ n+
p-type body
+
Vgd
gate
+ +source
-
Vgs-
drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-type body
W
L
toxSiO2 gate oxide
(good insulator, εox = 3.9)
polysilicongate
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 21
Channel Charge q MOS structure looks like parallel plate capacitor
while operating in inversion – Gate – oxide – channel
q Qchannel = CV q C =
n+ n+
p-type body
+
Vgd
gate
+ +source
-
Vgs-
drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-type body
W
L
toxSiO2 gate oxide
(good insulator, εox = 3.9)
polysilicongate
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 22
Channel Charge q MOS structure looks like parallel plate capacitor
while operating in inversion – Gate – oxide – channel
q Qchannel = CV q C = Cg = εoxWL/tox = CoxWL q V =
n+ n+
p-type body
+
Vgd
gate
+ +source
-
Vgs-
drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-type body
W
L
toxSiO2 gate oxide
(good insulator, εox = 3.9)
polysilicongate
Cox = εox / tox Cox = 8.6*fF/um2
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 23
Channel Charge q MOS structure looks like parallel plate capacitor
while operating in inversion – Gate – oxide – channel
q Qchannel = CV q C = Cg = εoxWL/tox = CoxWL q V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +source
-
Vgs-
drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-type body
W
L
toxSiO2 gate oxide
(good insulator, εox = 3.9)
polysilicongate
Cox = εox / tox
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 24
Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field
between source and drain q v =
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 25
Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field
between source and drain q v = µE µ called mobility q E =
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 26
Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field
between source and drain q v = µE µ called mobility q E = Vds/L q Time for carrier to cross channel:
– t =
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 27
Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field
between source and drain q v = µE µ called mobility q E = Vds/L q Time for carrier to cross channel:
– t = L / v
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 28
nMOS Linear I-V q Now we know
– How much charge Qchannel is in the channel – How much time t each carrier takes to cross
dsI =
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 29
nMOS Linear I-V q Now we know
– How much charge Qchannel is in the channel – How much time t each carrier takes to cross
channelds
QIt
=
=
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 30
nMOS Linear I-V q Now we know
– How much charge Qchannel is in the channel – How much time t each carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QItW VC V V VL
VV V V
µ
β
=
⎛ ⎞= − −⎜ ⎟⎝ ⎠
⎛ ⎞= − −⎜ ⎟⎝ ⎠
ox = WCL
β µ
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© Digital Integrated Circuits2nd Devices
Computed Curves
Vgs = 5v
Vgs = 4.5v
Vgs = 4.0v
Linear Resistor
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 32
nMOS Saturation I-V q If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt q Now drain voltage no longer increases current
dsI =
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 33
nMOS Saturation I-V q If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt q Now drain voltage no longer increases current
2dsat
ds gs t dsatVI V V Vβ ⎛ ⎞= − −⎜ ⎟
⎝ ⎠
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 34
nMOS Saturation I-V q If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt q Now drain voltage no longer increases current
( )22
2
dsatds gs t dsat
gs t
VI V V V
V V
β
β
⎛ ⎞= − −⎜ ⎟⎝ ⎠
= −
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 35
Computed Curves
Vgs = 5v
Vgs = 4.5v
Vgs = 4.0v
Linear Resistor
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 36
nMOS I-V Summary
( )2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V VVI V V V V V
V V V V
β
β
⎧⎪ <⎪⎪ ⎛ ⎞= − − ⎪⎩
q Shockley 1st order transistor models
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 37
Example q We will be using a 0.180 µm process for your project
– From TSMC Semiconductor – tox = 40 Å – µ = 180 cm2/V*s – Vt = 0.4 V
q Plot Ids vs. Vds – Vgs = 0, 0.3,…, 1.8 – Use W/L = 4/2 λ
( )14
28
3.9 8.85 10350 120 /100 10ox
W W WC A VL L L
β µ µ−
−
⎛ ⎞• ⋅ ⎛ ⎞= = =⎜ ⎟⎜ ⎟⋅ ⎝ ⎠⎝ ⎠180
40 155
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 38
pMOS I-V q All dopings and voltages are
inverted for pMOS q Mobility µp is determined by
holes – Typically 2-3x lower than
that of electrons µn q Thus pMOS must be wider to
provide same current – Often, assume µn / µp = 2
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© Digital Integrated Circuits2nd Devices
Current-Voltage Relations Long-Channel Device
Cut-off (VGS – VT < 0) “no current” (not really)
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© Digital Integrated Circuits2nd Devices
ID versus VDS short channel device
-4
V DS (V) 0 0.5 1 1.5 2 2.5 0
0.5
1
1.5
2
2.5 x 10
I D (A
)
VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V
0 0.5 1 1.5 2 2.5 0
1
2
3
4
5
6 x 10 -4
V DS (V)
I D (A
)
VGS= 2.5 V
VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V
Resistive Saturation VDS = VGS - VT
Long Channel Short Channel
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© Digital Integrated Circuits2nd Devices
Rabaey’s unified model for manual analysis
S D
G
B
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© Digital Integrated Circuits2nd Devices
Transistor Model for Manual Analysis
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© Digital Integrated Circuits2nd Devices
Simple Model versus SPICE
0 0.5 1 1.5 2 2.5 0
0.5
1
1.5
2
2.5 x 10 -4
V DS (V)
I D (A
)
Velocity Saturated
Linear
Saturated
VDSAT=VGT
VDS=VDSAT
VDS=VGT
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© Digital Integrated Circuits2nd Devices
Even Simpler: The Transistor as a Switch
VGS ≥ VTR o n
S DID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
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© Digital Integrated Circuits2nd Devices
The Transistor as a Switch
This week’s Lab – find Req for our TSMC 180nm process
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© Digital Integrated Circuits2nd Devices
Saturation Effects
Which is the resistor?
Discharge of 1pf capacitor, with Vgs of 3,4,5 volts. Also, 12k resistor.
d
s
g
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 47
More on Capacitance q Any two conductors separated by an insulator have
capacitance q Gate to channel capacitor is very important
– Creates channel charge necessary for operation q Source and drain have capacitance to body
– Across reverse-biased diodes – Called diffusion capacitance because it is
associated with source/drain diffusion
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 48
Gate Capacitance q Approximate channel as connected to source q Cgs = εoxWL/tox = CoxWL = CpermicronW q Cpermicron is typically about 2 fF/µm
n+ n+
p-type body
W
L
toxSiO2 gate oxide
(good insulator, εox = 3.9ε0)
polysilicongate
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© Digital Integrated Circuits2nd Devices
The Gate Capacitance
t ox
n + n +
Cross section
L
Gate oxide
x d x d
L d
Polysilicon gate
Top view
Gate-bulk overlap
Source
n +
Drain
n + W
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© Digital Integrated Circuits2nd Devices
Dynamic Behavior of MOS Transistor
DS
G
B
CGDCGS
CSB CDBCGB
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© Digital Integrated Circuits2nd Devices
Physical visualization of FET capacitances
Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.
-
© Digital Integrated Circuits2nd Devices Copyright © 2005 Pearson Addison-Wesley. All rights reserved.
MOS Capacitances Behavior !
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© Digital Integrated Circuits2nd Devices
Gate Capacitance – Behavior
S D
G
CGCS D
G
CGCS D
G
CGC
Cut-off Resistive Saturation
Most important regions in digital design: saturation and cut-off
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© Digital Integrated Circuits2nd Devices
Measuring the Gate Cap
2 1.5 2 1 2 0.5 0
3
4
5
6
7
8
9
103 102 16
2
VGS (V)
VGS
GateCapacita
nce(F)
0.5 1 1.5 22 2
I
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CMOS VLSI Design 3: CMOS Transistor Theory Slide 55
Diffusion Capacitance q Csb, Cdb q Undesirable, called parasitic capacitance q Capacitance depends on area and perimeter
– Use small diffusion nodes – Comparable to Cg
for contacted diff – ½ Cg for uncontacted – Varies with process
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© Digital Integrated Circuits2nd Devices
Diffusion Capacitance
Bottom
Side wall
Side wall Channel
Source N D
Channel-stop implant N A 1
Substrate N A
W
x j
L S
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© Digital Integrated Circuits2nd Devices
Calculation of the FET junction capacitance
Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.
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© Digital Integrated Circuits2nd Devices
Capacitances in 0.25 µm CMOS process
Values for a Typical Device:
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© Digital Integrated Circuits2nd Devices
Parasitic Resistances
W
LD
Drain
Draincontact
Polysilicon gate
DS
G
RS RD
VGS,eff
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© Digital Integrated Circuits2nd Devices
Final construction of the nFET RC model
Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.
CG
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© Digital Integrated Circuits2nd Devices
Latchup
(a) Origin of latchup (b) Equivalent circuit
VDD
Rpsubs
Rnwell p-source
n-source
n+ n+p+ p+ p+ n+
p-substrateRpsubs
Rnwell
VDD
n-well
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© Digital Integrated Circuits2nd Devices
Summary of MOSFET Operating Regions
q Strong Inversion VGS > VT § Linear (Resistive) VDS < VDSAT § Saturated (Constant Current) VDS ≥ VDSAT
q Weak Inversion (Sub-Threshold) VGS ≤ VT § Exponential in VGS with linear VDS dependence
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© Digital Integrated Circuits2nd Devices
SPICE MODELS
Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes VelocitySaturation and Threshold Variations
Level 3: Semi-Emperical - Based on curve fittingto measured devices
Level 4 (BSIM): Emperical - Simple and Popular
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© Digital Integrated Circuits2nd Devices
Main MOS SPICE Parameters
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© Digital Integrated Circuits2nd Devices
SPICE Parameters for Parasitics
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© Digital Integrated Circuits2nd Devices
SPICE Transistors Parameters
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© Digital Integrated Circuits2nd Devices
Circuit Simulation Model of CMOS Inverter
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© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 68
Pass Transistors
q We have assumed source is grounded q What if source > 0?
§ e.g. pass transistor passing VDD
VDDVDD
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© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 69
Pass Transistors
q We have assumed source is grounded q What if source > 0?
§ e.g. pass transistor passing VDD q Vg = VDD
§ If Vs > VDD-Vt, Vgs < Vt § Hence transistor would turn itself off
q nMOS pass transistors pull no higher than VDD-Vtn § Called a degraded “1” § Approach degraded value slowly (low Ids)
q pMOS pass transistors pull no lower than Vtp
VDDVDD
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© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 70
Pass Transistor Ckts
VDDVDD
VSS
VDD
VDD
VDD VDD VDD
VDD
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© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 71
Pass Transistor Ckts
VDDVDD Vs = VDD-Vtn
VSS
Vs = |Vtp|
VDDVDD-Vtn VDD-Vtn
VDD-Vtn
VDD
VDD VDD VDD
VDD
VDD-Vtn
VDD-2Vtn
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© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 72
Effective Resistance
q Shockley models have limited value § Not accurate enough for modern transistors § Too complicated for much hand analysis
q Simplification: treat transistor as resistor § Replace Ids(Vds, Vgs) with effective resistance R
– Ids = Vds/R § R averaged across switching of digital gate
q Too inaccurate to predict current at any given time § But good enough to predict RC delay
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© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 73
RC Delay Model
q Use equivalent circuits for MOS transistors § Ideal switch + capacitance and ON resistance § Unit nMOS has resistance R, capacitance C § Unit pMOS has resistance 2R, capacitance C
q Capacitance proportional to width q Resistance inversely proportional to width
kgs
dg
s
d
kCkC
kCR/k
kgs
dg
s
d
kC
kC
kC
2R/k
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© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 74
RC Values
q Capacitance § C = Cg = Cs = Cd = 2 fF/µm of gate width § Values similar across many processes
q Resistance § R ≈ 6 KΩ*µm in 0.6um process § Improves with shorter channel lengths
q Unit transistors § May refer to minimum contacted device (4/2 λ) § Or maybe 1 µm wide device § Doesn’t matter as long as you are consistent
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© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 75
Inverter Delay Estimate
q Estimate the delay of a fanout-of-1 inverter
2
1A
Y 2
1
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© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 76
Inverter Delay Estimate
q Estimate the delay of a fanout-of-1 inverter
C
CR
2C
2C
R
2
1A
Y
C
2C
Y2
1
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© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 77
Inverter Delay Estimate
q Estimate the delay of a fanout-of-1 inverter
C
CR
2C
2C
R
2
1A
Y
C
2C
C
2C
C
2C
RY
2
1
-
© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 78
Inverter Delay Estimate
q Estimate the delay of a fanout-of-1 inverter
C
CR
2C
2C
R
2
1A
Y
C
2C
C
2C
C
2C
RY
2
1
d = 6RC