Lecture 4. Adder & Subtractor Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E...

Lecture 4. Adder & Subtractor

Prof. Taeweon SuhComputer Science Education

Korea University

2010 R&E Computer System Education & Research

Korea Univ

Arithmetic Circuits

• Arithmetic circuits are the central building blocks of computers (CPUs)

• Computers are able to perform many arithmetic functions such as addition, subtraction, comparison, shift, multiplication, and division

• We are going to study hardware implementations of these operations

• Let’s start with adder• Addition is one of most common operations in computer

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1-bit Half Adder

• Let’s first consider how to implement an 1-bit adder

• Half adder 2 inputs: A and B 2 outputs: S (Sum) and Cout

(Carry)

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A B S(um)

C(arry)

0 0

0 1

1 0

1 1

AB C

BABABAS

A

BSum

Carry

0 0

1 0

0

0

1

1

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1-bit Full Adder

• Half adder lacks a Cin input to accept Cout of the previous column

• Full adder 3 inputs: A, B, Cin

2 outputs: S, Cout

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Cin A B S(um)

Cout

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0

1

1

0

1

0

0

1

0

0

1

1

1

1

0

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1-bit Full Adder

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Cin A B S(um)

Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

00 01 11 10

0 0 1 0 1

1 1 0 1 0

CinAB

00 01 11 10

0 0 0 1 0

1 0 1 1 1

CinAB

00 01 11 10

0 0 0 1 0

1 0 1 1 1

CinAB

or

Slide from Prof. Sean Lee, Georgia Tech

Sum

Cout

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1-bit Full Adder Schematic

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BACinS

A

B

Cin

Cout

S

Half Adder

Half Adder

B)Cin(AABCout


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Multi-bit Adder

• It seems that an 1-bit adder is doing not much of work• Let’s move on to a multi-bit adder

N-bit adder sums two N-bit inputs (A and B), and Cin (carry-in)

• It is commonly called carry propagate adders (CPAs) because the carry-out of one bit propagates into the next bit

• Three common CPA implementations Ripple-carry adders (slow) Carry-lookahead adders (fast) Prefix adders (faster)

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A B

S

Cout Cin+N

NN

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Ripple-Carry Adder

• The simplest way to build an N-bit CPA is to chain 1-bit adders together Carry ripples through entire chain

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S31

A30 B30

S30

A1 B1

S1

A0 B0

S0

C30 C29 C1 C0

Cout ++++

A31 B31

Cin

Example: 32-bit Ripple Carry Adder

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4-bit Ripple-Carry Adder

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FullAdder

A B

CinCout

S

S0

A0 B0

FullAdder

A B

CinCout

S

S1

A1 B1

FullAdder

A B

CinCout

S

S2

A2 B2

FullAdder

A B

CinCout

S

S3

A3 B3

Carry

S0

BACinS

B)Cin(AABCout

Modified from Prof Sean Lee’s Slide, Georgia Tech

ABCin

S

Cout

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Delay of Ripple Carry Adder

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S0

A0 B0

Carry Cin

1st Stage Critical Path = 3 gate delays= DXOR+DAND+DORBACinS

B)Cin(AABCout


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1st Stage Critical Path = 3 gate delays= DXOR+DAND+DOR

2nd Stage Critical Path = 2 gate delays= DAND+DOR

(Assume that inputs are applied at the same time)

S0

A0 B0

Cin

S1

A1 B1

BACinS

B)Cin(AABCout


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• Critical path delay of a 4-bit ripple carry adder• DXOR + 4 (DAND+DOR) : 9 gates delay

• Critical path delay of an N-bit ripple carry adder•2(N-1)+3 = (2N+1) gate delays

S0

A0 B0

Cin

S1

A1 B1

S2

A2 B2

S3

A3 B3

Carry

Modified from Prof Sean Lee’s Slide, Georgia Tech

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Ripple-Carry Adder Delay

• Ripple-carry adder has disadvantage of being slow when N is large The delay of an N-bit ripple-carry adder is

roughly tripple = N • tFA (tFA is the delay of a full adder)

• A faster adder needs to address the serial propagation of the carry bit

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Carry-Lookahead Adder

• The fundamental reason that large ripple-carry adders are slow is that the carry signals must propagate through every bit in the adder

• A carry-lookahead adder (CLA) is another type of CPA that solves this problem. It divides the adder into blocks and provides circuitry to

quickly determine the carry out of a block as soon as the carry-in is known

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Carry-Lookahead Adder

• Compute the carry-out (Cout) for an N-bit block Compute generate (G) and propagate (P) signals for columns and

then an N-bit block A column (bit i) can produce a carry-out by either generating a

carry-out or propagating a carry-in to the carry-out

• Generate (Gi) and Propagate (Pi) signals for each column A column will generate a carry-out if both Ai and Bi are 1

Gi = Ai Bi

A column will propagate a carry-in to the carry-out if either Ai or Bi is 1

Pi = Ai + Bi

• Express the carry-out of a column (Ci) in terms of Pi and Gi

Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1

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Carry Generate & Propagate

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What do these equations mean? Let’s think about these equations for a moment

Modified from Prof H.H.Lee’s Slide, Georgia Tech

gi = Ai Bi

pi = Ai + Bi

Ci = AiBi + (Ai + Bi) Ci-1

Ci = gi + pi Ci-1C0 = g0 + p0 C-1

C1 = g1 + p1 C0 = g1 + p1 g0 + p1 p0 C-1

C2 = g2 + p2 C1 = g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 C-1

C3 = g3 + p3 C2 = g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0 + p3 p2 p1 p0 C-1

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Carry Generate & Propagate

• A 4-bit block will generate a carry-out if column 3 generates (g3) a carry or if column 3 propagates (p3) a carry that was generated or propagated in a previous column

G3:0 = g3 + p3 (g2 + p2 (g1 + p1 g0 )

= g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0

• A 4-bit block will propagate a carry-in to the carry-out if all of the columns propagate the carry

P3:0 = p3 p2 p1 p0

• We compute the carry out of the 4-bit block (Ci) as

Ci = Gi:j + Pi:j Cj

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4-bit CLA

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Carry Lookahead Logic

g1 p1

A1 B1S1

C0

g2 p2

A2 B2S2

C1

g3 p3

A3 B3S3

C2

g0 p0

A0 B0S0

C-1C3

)(propagate BAp

(generate) BAg

iii

iii

iiii BACS


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An Implementation of CLA

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A0 B0S0A1 B1S1A2 B2S2A3 B3S3

C0C1C2

C3

g0 p0g1 p1g2 p2g3 p3

Carry Delay is 4*DAND + 2*DOR for Carry C3

Reuse some gate output results in little Improvement

C-1


C0 = g0 + p0 C-1

C1 = g1 + p1 C0 = g1 + p1 g0 + p1 p0 C-1

C2 = g2 + p2 C1 = g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 C-1


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More Expensive and Fast CLA

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Carry Lookahead LogicC3

A0 B0S0A1 B1S1

C-1

A2 B2S2A3 B3S3

Only 3 Gate Delay for each Carry Ci = DAND + 2*DOR

C2g3 p3 g0 p0C1g2 p2 C0g1 p1


C0 = g0 + p0 C-1

C1 = g1 + p1 C0 = g1 + p1 g0 + p1 p0 C-1

C2 = g2 + p2 C1 = g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 C-1


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32-bit CLA with 4-bit blocks

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B0

++++

P3:0

G3P3G2P2G1P1G0

P3P2P1P0

G3:0

Cin

Cout

A0

S0

C0

B1 A1

S1

C1

B2 A2

S2

C2

B3 A3

S3

Cin

A3:0B3:0

S3:0

4-bit CLABlock

Cin

A7:4B7:4

S7:4

4-bit CLABlock

C3C7

A27:24B27:24

S27:24

4-bit CLABlock

C23

A31:28B31:28

S31:28

4-bit CLABlock

C27Cout

It shows a path to C3 only


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CLA Delay

• The delay of an N-bit CLA with k-bit blocks is roughly: tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA

where tpg is the delay of the column generate and propagate gates tpg_block is the delay of the block generate and propagate gates tAND_OR is the delay from Cin to Cout of the final AND/OR gate

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tpg

tpg_block

tAND_OR

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Adder Delay Comparisons

• Compare the delay of 32-bit ripple-carry adder and CLA The CLA has 4-bit blocks Assume that each two-input gate delay is 100 ps Assume that a full adder delay is 300 ps

tripple = NtFA

= 32(300 ps) = 9.6 ns

tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA

= [100 + 600 + (7)200 + 4(300)] ps= 3.3 ns

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Verilog-HDL Representation

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module adder #(parameter N = 8)

(input [N-1:0] a, b,

input cin,

output [N-1:0] s,

output cout);

assign {cout, s} = a + b + cin;

endmodule

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Then, When to Use What?

• We have discussed 3 kinds of CPA Ripple-carry adder Carry-lookahead adder Prefix adder (see backup slides)

• Faster adders require more hardware and therefore they are more expensive and power-hungry

• So, depending on your speed requirement, you can choose the right one

• If you use HDL to describe an adder, the CAD tools will generate appropriate logic considering your speed requirement

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References

• Our book covers very little about addition and subtraction

• Refer to the following books for details Logic and Computer Design Fundamentals by Morris Mano, 4th

edition (Ch 4. Arithmetic Functions and HDLs, pp 168 ~ pp 185)

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Revisiting 2’s Complement Number

• Given an n-bit number N, the 2s complement of N is defined as 2n – N for N ≠ 0 0 for N = 0

Example: 3 is 4’b0011 (in a 4-bit binary) • 2s complement of 3: 24 -3 = 4’b1101

• A fast way to get a 2s complement number is to flip all the bits and add 1

• In hardware design of computer arithmetic, the 2s complement number provides a convenient and simple way to do addition and subtraction of unsigned and signed numbers

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Subtractor

• Suppose that we use a 4-bit

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7 - 5

0111 0101

3 - 7

0011 0111

Result = 2 Result = -4

0111+ 1011

10010

0011+ 1001

01100CinCout

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An Implementation of a 4-bit Adder and Subtractor

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FullAdder

A B

CinCout

S

S0

A0

FullAdder

A B

CinCout

S

S1

A1

FullAdder

A B

CinCout

S

S2

A2

FullAdder

A B

CinCout

S

S3

A3

B0B1B2B3

C

Subtract

Hmmm.. So, it looks simple! Are we done?

Not Really!!

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Subtraction of Unsigned Numbers

• Unsigned number is either positive or zero There is no sign bit So, a n-bit can represent numbers from 0 to 2n - 1

• For example, a 4-bit can represent 0 to 15 (=24 – 1) To declare an unsigned number in C language,

• unsigned int a; x86 allocates a 32-bit for a variable of unsigned int

• Subtraction of unsigned integers M – N in binary can be done as follows:

• M + (2n – N) = M – N + 2n

• If M ≥ N, the sum does produce an end carry, which is 2n

Subtraction result is zero or a positive number• If M < N, the sum does not produce an end carry since it is equal to 2n

– (N – M)

• Unsigned Underflow If there is no carry-out from adder, the subtraction result is

negative (and unsigned number can’t represent negative numbers)

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Example

• Suppose that we use a 4-bit (0 ~ 15)

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10 - 51010 0101

#include <stdio.h>

void main(){unsigned int ua, ub, uc;

ua = 10;ub = 5;

uc = ua - ub ;

printf("hex: ua = h'%x, ub = h'%x, uc = h'%x\n", ua, ub, uc);printf("unsigned: ua = d'%u, ub = d'%u, uc = d'%u\n", ua, ub, uc);printf("signed: ua = d'%d, ub = d'%d, uc = d'%d\n", ua, ub, uc);}

1010+ 1011

10101

• Carry-out can be used in comparison of two unsigned numbers• If the sum produces an end carry, then the minuend

(10) is equal to the subtrahend (5) or larger than the subtrahend

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Another Example

• Suppose that we use a 4-bit (0 ~ 15)

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10 - 13

1010 1101

#include <stdio.h>

void main(){unsigned int ua, ub, uc;

ua = 10;ub = 13;

uc = ua - ub ;

printf("hex: ua = h'%x, ub = h'%x, uc = h'%x\n", ua, ub, uc);printf("unsigned: ua = d'%u, ub = d'%u, uc = d'%u\n", ua, ub, uc);printf("signed: ua = d'%d, ub = d'%d, uc = d'%d\n", ua, ub, uc);}

1010+ 0011

01101

• It is called unsigned underflow (borrow) when the carry out is 0 in unsigned subtraction• Carry-out can be used in comparison of two unsigned numbers• If the sum does not produces an end carry, then the former (10) is smaller the latter (13)• Be careful when you do your programming

• Understand the consequence of the execution of your program in computer!!!

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Subtraction of Signed Numbers

• Signed number represents positive or negative number There is a sign bit (MSB) A n-bit can represent numbers from -2n-1 to 2n-1-1

• For example, a 4-bit can represent -8 (-23) to 7 (=23 – 1) To declare a signed number in C language,

• int a; // signed is implicit x86 allocates a 32-bit for a variable of signed int

• Subtraction of signed integers It is simply done by addition of two binary numbers in 2s

complement form• A carry-out from the sign bit position is discarded

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Example

• Suppose that we use a 4-bit (-8 ~ 7)

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7 - 5

0111 0101

#include <stdio.h>

void main(){int sa, sb, sc;

sa = 7;sb = 5;

sc = sa - sb ;

printf("hex: sa = h'%x, sb = h'%x, sc = h'%x\n", sa, sb, sc);printf("unsigned: sa = d'%u, sb = d'%u, sc = d'%u\n", sa, sb, sc);printf("signed: sa = d'%d, sb = d'%d, sc = d'%d\n", sa, sb, sc);}

0111+ 1011

10010

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Example

• Suppose that we use a 4-bit (-8 ~ 7)

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5 - 7

0101 0111

#include <stdio.h>

void main(){int sa, sb, sc;

sa = 5;sb = 7;

sc = sa - sb ;

printf("hex: sa = h'%x, sb = h'%x, sc = h'%x\n", sa, sb, sc);printf("unsigned: sa = d'%u, sb = d'%u, sc = d'%u\n", sa, sb, sc);printf("signed: sa = d'%d, sb = d'%d, sc = d'%d\n", sa, sb, sc);}

0101+ 1001

01110

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Overflow/Underflow

• Overflow/Underflow The answer to an addition or subtraction exceeds the

magnitude that can be represented with the allocated number of bits

• Overflow/Underflow is a problem in computers because the number of bits to hold a number is fixed For this reason, computers detect and flag the occurrence

of an overflow/underflow

• Detection of an overflow/underflow after the addition of two binary numbers depends on whether the numbers are considered to be signed or unsigned

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Overflow/Underflow in Unsigned Numbers

• When two unsigned numbers are added, overflow is detected from the end carry-out of the most significant position If the end carry is 1, there is an overflow

• When two unsigned numbers are subtracted, underflow is detected when the end carry is 0

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Overflow/Underflow in Signed Numbers

• With signed numbers, an overflow/underflow can’t occur for an addition if one number is positive and the other is negative. Adding a positive number to a negative number

produces a result whose magnitude is equal to or smaller than the larger of the original numbers

• An overflow may occur in addition if two numbers are both positive When x and y both have sign bits of 0 (positive numbers)

• If the sum has sign bit of 1, there is an overflow

• An underflow may occur in addition if two numbers are both negative When x and y both have sign bits of 1 (negative

numbers)• If the sum has sign bit of 0, there is an underflow

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Examples

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01001000 (+72)00111001 (+57)--------------------10000001 (+129)

What is largest positive number represented by 8-bit?

8-bit Signed number addition

10000001 (-127)11111010 ( -6)--------------------01111011 (-133)

8-bit Signed number addition

What is smallest negative number represented by 8-bit?

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Overflow/Underflow in Signed Numbers

• We can detect overflow/underflow with the following logic Suppose that we add two k-bit numbers

xk-1xk-2… x0 + yk-1yk-2… y0 = sk-1sk-2… s0

• There is an easier formula

Let the carry out of a k-bit full adder be ck-1ck-2… c0

If a 0 (ck-2) is carried in, the only way that 1 (ck-1) can be carried out is when xk-1 = 1 and yk-1= 1 (Adding two negative numbers results in a non-negative number)

If a 1 (ck-2) is carried in, the only way that 0 (ck-1) can be carried out is when xk-1 = 0 and yk-1= 0 (Adding two positive numbers results in a negative number)

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Overflow = xk-1yk-1sk-1 + xk-1yk-1sk-1

Overflow = ck-1 + ck-2

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Overflow/Underflow Detection of Signed Numbers

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FullAdder

A B

CinCout

S

S0

A0 B0

FullAdder

A B

CinCout

S

S1

A1 B1

FullAdder

A B

CinCout

S

S2

A2 B2

FullAdder

A B

CinCout

S

S3

A3 B3

Carry

Overflow/Underflow

n-bit Adder/SubtractorOverflow/Underflow

Cn-1

Cn-2

Prof. Sean Lee’s Slide, Georgia Tech

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Recap

• Unsigned numbers Overflow could occur when 2 unsigned numbers are

added• An end carry of 1 indicates an overflow

Underflow could occur when 2 unsigned numbers are subtracted

• An end carry of 0 indicates an underflow (minuend < subtrahend)

• Signed numbers Overflow could occur when 2 signed positive numbers

are added Underflow could occur when 2 signed negative numbers

are added Overflow flag (Cn-1^ Cn-2) indicates either overflow or

underflow42

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Recap

• Binary numbers in 2s complement system are added and subtracted by the same basic addition and subtraction rules as used in unsigned numbers Therefore, computers need only one common

hardware circuit to handle both types (signed, unsigned numbers) of arithmetic

• The programmer must interpret the results of addition or subtraction differently, depending on whether it is assumed that the numbers are signed or unsigned

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Backup Slides

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Prefix Adder

• Computes generate and propagate signals for all of the columns (!) to perform addition even faster

• Computes G and P for 2-bit blocks, then 4-bit blocks, then 8-bit blocks, etc. until the generate and propagate signals are known for each column Then, the prefix adder has log2N stages

• The strategy is to compute the carry in (Ci-1) for each of the columns as fast as possible and then to compute the sum:

Si = (Ai Bi) Ci-1

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Prefix Adder

• A carry is generated by being either generated in a column or propagated from a previous column

• Define column -1 to hold Cin, so

G-1 = Cin, P-1 = 0 Then,

Ci-1 = Gi-1:-1 because there will be a carry out of column i-1 if the block spanning columns i-1 through -1 generates a carry

• Thus, we can rewrite the sum equation as: Si = (Ai Bi) Gi-1:-1

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Prefix Adder

• The generate and propagate signals for a block spanning bits i:j are

Gi:j = Gi:k Pi:k Gk-1:j

Pi:j = Pi:kPk-1:j

• These signals are called the prefixes because they must be precomputed before the final sum computation can complete

• In words, these prefixes describe that A block will generate a carry if the upper part (i:k) generates a

carry or the upper part propagates a carry generated in the lower part (k-1:j)

A block will propagate a carry if both the upper and lower parts propagate the carry.

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4-bit Prefix Adder

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B3 B2 B1 B0

A3 A2 A1 A0 Cin

G-1 = Cin, P-1 = 0P2, G2 P1, G1 P0, G0 P-1, G-1

Pi = Ai Bi , Gi = Ai + Bi

P0:-1, G0:-

1

P2:1, G2:1 P2:1 = P2 P1, G2:1 = G2 + P2 G1

P0:-1 = P0 P-1, G0:-1 = G0 + P0 G-1

S3 S2 S1 S0

S3 = A3 B3 G2:-1

S2 = A2 B2 G1:-1

S1 = A1 B1 G0:-1

S0 = A0 B0 G-1

+ +++

+

+++

P2:-1, G2:-

1

P2:-1 = P2:1 P0:-1 ,

G2:-1 = G2:1 + P2:1 G0:-1

P1:-1, G1:-

1

P1:-1 = P1 P0:-1 ,

G1:-1 = G1 + P1 G0:-1

C-1 = G -1C0 = G 0:-1C1 = G 1:-

1

C2 = G 2:-

1

Remember that P2:-1 is always “0” since P-1 = 0, but intermediate propagate signals (P1:-1 ,P0:-1 ,P2:1) are used for calculating subsequent generate signals

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16-bit Prefix Adder

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0:-1

-1

2:1

1:-12:-1

012

4:3

3

6:5

5:36:3

456

5:-16:-1 3:-14:-1

8:7

7

10:9

9:710:7

8910

12:11

11

14:13

13:1114:11

121314

13:714:7 11:712:7

9:-110:-1 7:-18:-113:-114:-1 11:-112:-1

15

0123456789101112131415

BiAi

Gi:iPi:i

Gk-1:jPk-1:jGi:kPi:k

Gi:jPi:j

ii:j

BiAiGi-1:-1

Si

iLegend

G-1 = Cin, P-1 = 0

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Prefix Adder Delay

• The delay of an N-bit prefix adder is: tPA = tpg + log2N(tpg_prefix ) + tXOR

where tpg is the delay of the column generate and propagate

gates tpg_prefix is the delay of the black prefix cell

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Flags in CPU

• In general, computer has several flags (registers) to indicate state of operations such as addition and subtraction N: Negative Z: Zero C: Carry V: Overflow

• We have only one adder inside a computer CPU does comparison of signed or unsigned

numbers by subtraction using adder Computer sets the flags depending on the operation

result Then, do these flags provide enough information to

judge that one is bigger than or less than the other?

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Example

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void example(void)

{

unsigned int a, b, c;

signed int aa, bb, cc;

a = 0x10;

b = 0x20;

aa = 0x30;

bb = 0x40;

if (a > b) c = a + b;

else c = a - b;

if (aa > bb) cc = aa + bb;

else cc = aa - bb;

return;

}

• Equality a == b ?

• Do subtraction• True if the Z flag is set

• Unsigned number comparison a > b ?

• Do subtraction• True if C is set and Z is clear

• Signed number comparison a > b ?

• Do subtraction• True if N == V, meaning either

Both N and V are set (1) or Both N and V are clear (0)

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Example

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• Signed number comparison a > b ?

• Do subtraction• True if N == V, meaning either

Both N and V are set (1) or Both N and V are clear (0)

0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000

7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8

• N == V• Both are 0, meaning that overflow didn’t happen

• Examples: 5 – 1, 3 – (-4), (-3) – (-4) • Both are 1, meaning that overflow did happen

• Examples: 5 – (-3), 7 – (-4)

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EFLGAS in x86

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EFLGAS in x86

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CPSR in ARM

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CPSR in ARM

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Lecture 4. Adder & Subtractor Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E...

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Transcript of Lecture 4. Adder & Subtractor Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E...