Computers and Microprocessors Lecture 34 PHYS3360/AEP3630 1.
Lecture 34 1
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Transcript of Lecture 34 1
CKV
Digital Electronics and Computer Organization
Lecture 34: Modular Approach to CPU Design and ASMs
Digital Design
11/27/2014 1
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CKV
ASM Examples
2-bit up down counter (Q2Q1) C = 0 up, C = 1 down
0
1
2
3 Q1
C
Q2
C
Q1, Q2
C
0
0
0
0
1
1
00
01
10
11
1
1
C
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ASM Examples
Mealy Sequential Network
X
0
X
A
Z2 Z1
1
B
X
Z1, Z2
C
0
1
1
Z1
0
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Algorithmic State Machines
Register Transfer Example
Clear R
Load F
R0
FE
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Algorithmic State Machines
ASM Block
Consists of state block, decision block and conditional block connected to exit path
One entrance many exits
Operations within the state and conditional boxes are initiated by a common clock pulse
Clock transfers system to one of the next states
When is A incremented, R cleared ?
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Algorithmic State Machines
ASM Block
Incr_A
Clear R
Consists of state block, decision block and conditional block connected to exit path
One entrance many exits
Operations within the state and conditional boxes are initiated by a common clock pulse
Clock transfers system to one of the next states
A incremented, R is cleared on next positive edge of clock
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Algorithmic State Machines
Incr_A
Clear R
Equivalent State Diagram (EF inputs)
Incr_A Moore type output
Clear R Mealy type output
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Algorithmic State Machines
Timing Considerations
Timing of all registers controlled by Master clock
Major difference between conventional flow chart and ASM is timing considerations
Flow chart – increments A only then checks for E and F
ASM – Entire block as a unit , all operations occur in synchronous to clock edge.
Incr_A
Clear R
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Algorithmic State Machines
Timing Considerations
In present State a signal for incrementing A is generated, E and F are checked and Clear R signal is generated when E = 1.
At Next positive edge of clock A is incremented , R is cleared if E =1 and control transfers to next state.
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Algorithmic State Machines
ASM Chart
Does not list register operations within state box
Incr_A
Clear R
Edges annotated with register operations
Conditional boxes with the signals that control register operations
A A + 1
R 0
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Design Example
Serial Binary Multiplier (11 X 7)
A Q 0000 0111 Initial 1101 0111
C
Q0 = 1 Add
Shift 0101 1011
0 0 0
0000 1011 Q0 = 1 Add 1 1000 0101 Shift 0 0011 0101 Q0 = 1 Add 1 1001 1010 Shift 0 0100 1101 Q0 = 0 shift 0
Final Result = 77
B = 1101
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Design Example
Serial Binary Multiplier
Control Unit Datapath unit
Data inputs Multiplier, Multiplicand
Data outputs Product
Control Signals
Load registers
Shift registers
Add registers
Decrement counter
Q0
Zero
Start, ready, reset
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Design Example
Block Diagram
Control Unit
A B Q
C P
Ready Multiplicand Multiplier
Load_regs
Shift_regs
Add_regs
Decr_P
Reset
Start
Q[0]
Zero Product
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Design Example
Datapath Unit
A B Q
C P
Multiplicand Multiplier
Load_regs
Shift_regs
Add_regs
Decr_P
Q[0]
Zero Product
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Design Example
Datapath Unit
Add_ Regs
Load_regs Shift_regs
Load_regs
Shift_regs
Q0
Load_regs
Load_regs
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Design Example
Control Unit
Control Unit
Ready
Load_regs
Shift_regs
Add_regs
Decr_P
Reset
Start
Q[0]
Zero
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Partial ASM Chart
A <= 0
C <= 0
B <= Multiplicand
Q <= Multiplier
P <= m_size
S_Idle
Start 0
1
S_add
Q[0] 1
S_Shift
Zero
0
{C,A} <= A + B
P <= P-1, Decrement Counter
{C,A,Q} <= {C,A,Q} >> 1
Why is it partial ??
Reset
1
0
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Complete ASM Chart
A <= 0
C <= 0
B <= Multiplicand
Q <= Multiplier
P <= m_size
S_Idle, Ready
Start 0
1
S_add, Decr_P
Q[0] 1
S_Shift, Shift_regs
Zero
0
{C,A} <= A + B
P <= P-1, Decrement Counter
{C,A,Q} <= {C,A,Q} >> 1
Add_regs
Load_regs
Reset
0
1
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State Diagram and State table
S_idle = 00, S_add = 01, S_shift = 10
G1 G0
Present State
Start Q[0]
Inputs
Zero G1+ G0
+
Next State
Ready Load_regs
Outputs
Decr_P Add_regs Shift_regs
0
0
0
0
1
1
0
0
1
1
0
0
0
1
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
1
0
0
1
1
0
0
0
1
0
0
1
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
S_idle
S_add
S_shift
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Control Unit
0
1
(S_Idle) T0
(S_add) T1
(S_shift) T2
2X4 Decoder
T3
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Control Signal Generation
G1 G0
Present State
0
0
1
0
1
0
Ready Decr_P Shift_regs
1
0
0
0
1
0
0
0
1
S_idle
S_add
S_shift
Load_regs = 1 when in S_idle state and start = 1
Add_regs = 1 when in S_add state and Q[0] = 1
Ready = G1’ G0’
Decr_P = G1’ G0
Shift_Regs = G1 G0’
Load_Regs = G1’ G0’ Start
Add_Regs = G1’ G0 Q[0]
2 to 4 Decoder
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Control Signal Generation
Ready = G1’ G0’
Decr_P = G1’ G0
Shift_Regs = G1 G0’
Load_Regs = G1’ G0’ Start
Add_Regs = G1’ G0 Q[0]
0
1
(S_Idle) T0
(S_add) T1
(S_shift) T2
2X4 Decoder
G1
G0
Start Q[0]
T3
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Next state Logic
G1 G0
Present State
Start Q[0]
Inputs
Zero G1+ G0
+
Next State
0
0
0
0
1
1
0
0
1
1
0
0
0
1
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
1
0
0
1
1
0
0
0
1
0
0
1
0
G1+ = G1’ G0
G0+ = G1’ G0’ Start + G1 G0’ Zero’
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Next state Logic
G1+ = G1’ G0
G0+ = G1’ G0’ Start + G1 G0’ Zero’
G1’ G0
G1 G0’
G1’ G0’
Start
Zero
Clock
Reset
G1
G0
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Control Unit
0
1
(S_Idle) T0
(S_add) T1
(S_shift) T2
2X4 Decoder
T3
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Multiplexer Based Design for next state Logic
G1 G0
Present State
Start Q[0]
Inputs
Zero G1+ G0
+
Next State
0
0
0
0
1
1
0
0
1
1
0
0
0
1
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
1
0
0
1
1
0
0
0
1
0
0
1
0
0
1
2
3
0
1
2
3
2:1 MUX
2:1 MUX
Start
G0+
G1+
0
Zero’
0
1
0
S1 S0
S1 S0
G1
G0
Input Condition
Start’
Start
Q[0]’
Q[0]
Zero’
Zero
When G1G0 = 00, G0+ = Start’.0 + Start .1
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Multiplexer Based Design for next state Logic
0
1
2
3
0
1
2
3
2:1 MUX
2:1 MUX
Start
G0+
G1+
0
Zero’
0
1
0
S1 S0
S1 S0
G1 G0
G1
G0
Clock Reset
Start
Q[0]
(S_Idle) T0
(S_add) T1
(S_shift) T2
2X4 Decoder
T3
0
1
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Control Unit
Previous Design using Decoder and binary state Assignment
One hot design (one flip-flop per state)
S_idle = 100
S_add = 010
S_shift = 001
Reading Assignment Logic Design for one-hot state controller, Ref 8.8 Morris Mano
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Thank You