Lecture 3 – MSP430 ISA The Instruction Set Reading: Chapter 5: Architecture of the MSP430...

Lecture 3 – MSP430 ISAThe Instruction Set

Reading:

Chapter 5: Architecture of the MSP430 Processor

2

Topics to Cover…

MSP430 ISA Instruction Formats Double Operand Instructions Single Operand Instructions Jump Instructions Addressing Modes Instruction Disassembly Emulated Instructions

Lecture 03 - MSP430 ISA

MSP430 Architecture 3

Lecture 2 Objectives (cont’d)

Upon completion this lecture, students will be able to: Covert a MSP430’s assembly instruction into machine

code. 3 Instruction Format: I, II, III 27 Core Instructions and 24 Emulated Instructions 7 source addressing modes 4 destination addressing modes

MSP430 Architecture 4

Lecture 3 Objectives

Upon completion this lecture, students will be able to: Disassemble a sequence of MSP430’s machine code

into assembly language: Using the opcode to find the corresponding instruction

mnemonic. Append “.b” or “.w” using the b/w bit when appropriate. If double operand instruction, decode and list source

operand. If single or double operand instruction, decode and list

destination operand. If jump instruction, sign extend the 10-bit PC offset,

multiply by 2, and add to the current PC. List that address.

5

Problem Machine

More concrete, machine-dependent; errorprone, harder to write, read, debug, maintain

Abstract, machine-independent;easier to write, read, debug, maintain

Ass

em

ble

r

415E 0001410F532F5F0E4EE1 0000415E 0001531E410F532F5F0E415D 0001410F532F5F0D4EED 0000415F 0001531F410E532E5F0E41EE 0000

Machinelanguageinstructions

Instruction =Many cycles

Levels of Transformation

Com

pile

r

MOV.B 0x0001(SP),R14MOV.W SP,R15INCD.W R15ADD.W R15,R14MOV.B @R14,0x0000(SP)MOV.B 0x0001(SP),R14INC.W R14MOV.W SP,R15INCD.W R15ADD.W R15,R14MOV.B 0x0001(SP),R13MOV.W SP,R15INCD.W R15ADD.W R15,R13MOV.B @R14,0x0000(R13)MOV.B 0x0001(SP),R15INC.W R15MOV.W SP,R14INCD.W R14ADD.W R15,R14MOV.B @SP,0x0000(R14)

Assemblylanguageinstructions

One statement =Many instructions

Cod

erlampDoesntWork(){ if(unPlugged) { plugin(); } else if(burnedOut) { replace(); } else { buyNewLamp(); }}

High-levellanguagestatements

One algorithm =Many statements

Algorithm

Problem solvedby Algorithm

En

gine

er

Problem

Problem


6

Instruction Set Architecture

The computer ISA defines all of the programmer-visible components and operations of the computer

Memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location?

Register set (Register File) how many? what size? how are they used?

Instruction set opcodes data types addressing modes

ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language).

MSP430 ISA


7

MSP430 ISA

RISC/CISC machine 27 orthogonal instructions

8 jump instructions 7 single operand instructions 12 double operand instructions

7 addressing modes. 8/16-bit instruction addressing formats.

Memory architecture 16 16-bit registers 16-bit Arithmetic Logic Unit (ALU). 16-bit address bus (64K address space) 16-bit data bus (8-bit addressability) 8/16-bit peripherals

MSP430 ISA


8

MSP430 Registers

R0 (PC) – Program Counter This register always points to the next instruction to be fetched Each instruction occupies an even number of bytes. Therefore, the

least significant bit (LSB) of the PC register is always zero. After fetch of an instruction, the PC register is incremented by 2, 4,

or 6 to point to the next instruction. R1 (SP) – Stack Pointer

The MSP430 CPU stores the return address of routines or interrupts on the stack

User programs store local data on the stack The SP can be incremented or decremented automatically with

each stack access The stack “grows down” thru RAM and thus SP must be initialized

with a valid RAM address SP always points to an even address, so its LSB is always zero

MSP430 ISA


9

MSP430 Registers

R2 (SR/CG1) – Status Register The status of the MSP430 CPU is contained in register R2 Only accessable through register addressing mode - all other

addressing modes are reserved to support the constants generator

MSP430 ISA

Carry bitC

Zero bitZ

Negative bitN

General interrupt enableGIE

Turns off the CPU.CPUOFF

Oscillator offOSCOFF

Turns off the DCO dc generator.SCG0

Turns off the SMCLK.SCG1

Overflow bitV

R3 (CG2) – Constant Generator

R4-R15 – General Purpose registers

Register As Constant Remarks

R2 00 - Register mode

R2 01 (0) Absolute mode

R2 10 00004h +4, bit processingR2 11 00008h +8, bit processing

R3 00 00000h 0, word processing

R3 01 00001h +1R3 10 00002h +2, bit processingR3 11 0FFFFh -1, word processing


10

16 bit Arithmetic Logic Unit (ALU). Performs instruction arithmetic and

logical operations Instruction execution affects the state

of the following flags: Zero (Z) Carry (C) Overflow (V) Negative (N)

The MCLK (Master) clock signal drives the CPU.

MSP430 ALU

MSP430 ISA


11

MSP430 Memory OrganizationMSP430 ISA


12

MSP430 Instructions

There are three formats used to encode instructions for processing by the CPU core Double operand Single operand Jumps

The instructions for double and single operands, depend on the suffix used, (.w) word or (.b) byte

These suffixes allow word or byte data access If the suffix is ignored, the instruction processes

word data by default

Instruction Formats


13

MSP430 InstructionsInstruction Formats

Op-code Instruction Format0000 Undefined

Single Operand0001 RCC, SWPB, RRA, SXT, PUSH, CALL, RETI0010 JNE, JEQ, JNC, JC

Jumps0011 JN, JGE, JL, JMP0100 MOV

Double Operand

0101 ADD0110 ADDC0111 SUBC1000 SUB1001 CMP1010 DADD1011 BIT1100 BIC1101 BIS1110 XOR1111 AND

1111111011011100101110101001100001110110010101000011001000010000

4 to 16 Decoder

Op-code

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0

Instruction Register

Memory0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 mov.w r5,r4

0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 rrc.w r5

0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0 jc main

0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 mov.w #0x0600,r1

0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

PC


14

MPS430 Instruction Formats

Format I: Instructions with two operands:15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code S-reg Ad b/w As D-reg

MSP430 Instructions

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code b/w Ad D/S-reg

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code Condition 10-bit, 2’s complement PC offset

Format II: Instruction with one operand:

Format III: Jump instructions:


15

Format I: Double Operand

Double operand instructions (12 instructions):Mnemonic Operation Description

Arithmetic instructions

ADD(.B or .W) src,dst src+dstdst Add source to destination

ADDC(.B or .W) src,dst src+dst+Cdst Add source and carry to destination

DADD(.B or .W) src,dst src+dst+Cdst (dec) Decimal add source and carry to destination

SUB(.B or .W) src,dst dst+.not.src+1dst Subtract source from destination

SUBC(.B or .W) src,dst dst+.not.src+Cdst Subtract source and not carry from destination

Logical and register control instructions

AND(.B or .W) src,dst src.and.dstdst AND source with destination

BIC(.B or .W) src,dst .not.src.and.dstdst Clear bits in destination

BIS(.B or .W) src,dst src.or.dstdst Set bits in destination

BIT(.B or .W) src,dst src.and.dst Test bits in destination

XOR(.B or .W) src,dst src.xor.dstdst XOR source with destination

Data instructions

CMP(.B or .W) src,dst dst-src Compare source to destination

MOV(.B or .W) src,dst srcdst Move source to destination

Double Operand Instructions


16

Example: Double Operand

Copy the contents of a register to another register Assembly: mov.w r5,r4 Instruction code: 0x4504

One word instruction The instruction instructs the CPU to copy the 16-bit 2’s

complement number in register r5 to register r4

Op-codemov

S-regr5

AdRegister

b/w16-bits

AsRegister

D-regr4

0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0

Double Operand Instructions


17

Format II: Single Operand

Single operand instructions:

Mnemonic Operation Description


RRA(.B or .W) dst MSBMSB…LSBC

Roll destination right

RRC(.B or .W) dst CMSB…LSBC Roll destination right through carry

SWPB( or .W) dst Swap bytes Swap bytes in destination

SXT dst bit 7bit 8…bit 15 Sign extend destination

PUSH(.B or .W) src SP-2SP, src@SP Push source on stack

Program flow control instructions

CALL(.B or .W) dst SP-2SP,PC+2@SPdstPC

Subroutine call to destination

RETI @SP+SR, @SP+SP Return from interrupt

Single Operand Instructions


18

Example: Single Operand

Logically shift the contents of register r5 to the right through the status register carry

Assembly: rrc.w r5 Instruction code: 0x1005

One word instruction The CPU shifts the 16-bit register r5 one bit to the right

(divide by 2) – the carry bit prior to the instruction becomes the MSB of the result while the LSB shifted out replaces the carry bit in the status register

Op-coderrc

b/w16-bits

AdRegister

D-regr5

0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1

Single Operand Instructions


19

Jump Instruction Format

Jump instructions are used to direct program flow to another part of the program.

The condition on which a jump occurs depends on the Condition field consisting of 3 bits:

000: jump if not equal 001: jump if equal 010: jump if carry flag equal to zero 011: jump if carry flag equal to one 100: jump if negative (N = 1) 101: jump if greater than or equal (N = V) 110: jump if lower (N V) 111: unconditional jump

Jump Instructions

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code Condition 10-bit, 2’s complement PC offset


20

Jump Instruction Format

Jump instructions are executed based on the current PC and the status register

Conditional jumps are controlled by the status bits Status bits are not changed by a jump instruction The jump off-set is represented by the 10-bit, 2’s

complement value:

Thus, the range of the jump is -511 to +512 words, (-1023 to 1024 bytes ) from the current instruction

Note: Use a BR emulated instruction to jump to any address

22 offsetoldnew PCPCPC

Jump Instructions


21

Example: Jump Format

Continue execution at the label main if the carry bit is set Assembly: jc main Instruction code: 0x2fe4

One word instruction The CPU will add to the incremented PC (R0) the value

-28 x 2 if the carry is set

Op-codeJC

ConditionCarry Set

10-Bit, 2’s complement PC offset-28

0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0

Jump Instructions


MSP430 Addressing Modes

the ways in which operands can be specified.

23

Source Addressing Modes

The MSP430 has four modes for the source address: 00 = Rs - Register 01 = x(Rs) - Indexed Register 10 = @Rs - Register Indirect 11 = @Rs+ - Indirect Auto-increment

In combination with registers R0-R3, three additional source addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR) #n – Immediate, @PC+

Addressing Modes


24

Destination Addressing Modes

There are two modes for the destination address: 0 = Rd - Register 1 = x(Rd) - Indexed Register

In combination with registers R0/R2, two additional destination addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR)

Addressing Modes


25

00 = Register ModeAddressing Modes

Registers

ALU

CPUMemory

ADDER

add.w r4,r10 ;r10 = r4 + r10

PCPC

R10

R4

IRData Bus (+1

cycle)0x540

a0x540a

Address Bus

PC


Memory

26

01 = Indexed ModeAddressing Modes

Registers

ALU

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

add.w 6(r4),r10 ;r10 = M(r4+6) + r10

0x0006

PCPCPC

R10

R4

IRData Bus (+1

cycle)0x541

a0x541a

Address Bus

PC


Memory

27

10 = Indirect Register ModeAddressing Modes

Registers

ALU

Address Bus

Data Bus (+1 cycle)

CPU

ADDER

add.w @r4,r10 ;r10 = M(r4) + r10

PCPC

R10

R4

IRData Bus (+1

cycle)0x542

a

Address Bus

0x542a PC


Memory

28

Addressing Modes

Registers

ALU

Data Bus (+1 cycle)

CPU

ADDER

11 = Indirect Auto-increment Mode

add.w @r4+,r10 ;r10 = M(r4+) + r10

PCPC

R10

R4

IRData Bus (+1

cycle)0x543

a

Address Bus

PC0x543

a

Address Bus0002


Memory

29

Addressing Modes

Registers

ALU

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

01 w/R0 = Symbolic Mode (PC Relative)

cnt

add.w cnt,r10 ;r10 = M(cnt) + r10

0x000c

PCPCPC

PC

R10

IRData Bus (+1

cycle)0x501

a

Address Bus

0x501a PC


Memory

30

Addressing Modes

Registers

ALU

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

cnt

01 w/R2 = Absolute Mode

0000

add.w &cnt,r10 ;r10 = M(cnt) + r10

0xc018

PCPCPC

R10

IRData Bus (+1

cycle)0x521

a

Address Bus

0x521a PC


Memory

31

Addressing Modes

Registers

ALU

CPU

ADDER

11 w/R0 = Immediate Mode

add.w #100,r10 ;r10 = #100 + r10

PCPCPC

R10

Data Bus (+1 cycle)

IRData Bus (+1

cycle)0x503

a

Address Bus

PC0x503

a0x0064


Memory

32

Addressing Modes

Registers

ALU

CPU

ADDER

Constant Generator

add.w #1,r10 ;r10 = #1 + r10

PCPC

R10

00000001000200040008ffff

IRData Bus (+1

cycle)0x531

a

Address Bus

PC0x531

a


Memory

33

Addressing Modes

Registers

ALU

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

ADDER

3 Word Instruction (6 cycles)

cnt

add.w cnt,var ;M(var) = M(cnt) + M(var)

0x000c

PCPCPC

varAddress Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

PC

Data Bus (+1 cycle)0x021

9

IRData Bus (+1

cycle)0x501

a

Address Bus

0x501a

PCPC


34

Addressing Mode Examples

Source Destination

Example Rn x(Rn) Sym &abs @Rn @Rn+ #n Rn x(Rn) Sym &abs Len Operation

mov r10,r11 1 r10 r11

mov 2(r5),6(r6) 3 M(2+r5) M(6+r6)

mov EDE,TONI 3 M(EDE) M(TONI)

mov &MEM,&TCDAT 3 M(MEM) M(TCDAT)

mov @r10,r11 1 M(r10) r11

mov @r10+,tab(r6) 2 M(r10) M(tab+r6) , r10+2 r10

mov #45,TONI 3 #45 M(TONI)

mov #2,&MEM C 2 #2 M(MEM)

mov #1,r11 C 1 #1 r11

mov #45,r11 2 #45 r11

Instruction Length


Instruction Length

The number of words required to represent the instruction in machine code.

36

Quiz

What is the length (in words) for each of the following instructions?

Instruction L Instruction Ladd.w r5,r6 mov.w EDE,TONIadd.w cnt(r5),r6 mov.b &MEM,&TCDATadd.w @r5,r6 mov.w @r10,r11add.w @r5+,r6 mov.b @r10+,tab(r6)add.w cnt,r6 mov.w #45,TONIadd.w &cnt,r6 mov.w #2,&MEMadd.w #100,r6 mov.b #1,r11mov.w r10,r11 mov.w #45,r11mov.w @r5,6(r6) mov.b #-1,-1(r15)mov.w 0(r5),6(r6) mov.w @r10+,r10

Instruction Length

1.2.3.4.5.6.7.8.9.

10.


37

Cycles Per Instruction (CPI)

Instruction timing: 1 cycle to fetch instruction word +1 cycle if source is @Rn, @Rn+, or #Imm +2 cycles if source uses indexed mode

1st to fetch base address 2nd to fetch source Includes absolute and symbolic modes

+2 cycles if destination uses indexed mode +1 cycle if writing destination back to memory Jump instructions are always 2 cycles


38

Cycles Per Instruction...Instruction Clock Cycles

Jump instructions are always 2 cycles.


39

Example Cycles Per Instruction...

Example Src Dst Cycles Length

add R5,R8 Rn Rm 1 1

add @R5,R6 @Rn Rm 2 1

mov @R5+,R0 @Rn+ PC 3 1

add R5,4(R6) Rn x(Rm) 4 2

add R8,EDE Rn EDE 4 2

add R5,&EDE Rn &EDE 4 2

add #100,TAB(R8) #n x(Rm) 5 3

add &TONI,&EDE &TONI &EDE 6 3

add #1,&EDE #1 &EDE 4 2

Instruction Clock Cycles


40

Quiz

How many cyclesfor each instruction?

;*******************************************************************************; ;*******************************************************************************; cycles = ---; MCLK = --- cycles / 10 seconds = --- Mhz; CPI = MCLK / ---; MIPS = MCLK / CPI / 1000000 = --- MIPS

.cdecls C,LIST, "msp430.h" ; MSP430COUNT .equ 0 ; delay count;------------------------------------------------------------------------------ .text ; beginning of executable code;------------------------------------------------------------------------------RESET: mov.w #0x0280,SP ; init stack pointer mov.w #WDTPW+WDTHOLD,&WDTCTL ; stop WDT bis.b #0x01,&P1DIR ; set P1.0 as output

mainloop: xor.b #0x01,&P1OUT ; toggle P1.0 mov.w #COUNT,r15 ; use R15 as delay counter

delayloop: dec.w r15 ; delay over? jnz delayloop ; n jmp mainloop ; y, toggle led

;------------------------------------------------------------------------------; Interrupt Vectors;------------------------------------------------------------------------------ .sect ".reset" ; MSP430 RESET Vector .word RESET ; start address .end


Disassembling Instructions

Convert machine codes into Assembly language instructions

42

How to Disassembly MSP430 Code

1. Begin with a “PC” pointing to the first word in program memory.

2. Retrieve instruction word and increment PC by 2.3. Find and list the corresponding instruction mnemonic

using the opcode.4. Append “.b” or “.w” using the b/w bit when appropriate.5. If double operand instruction, decode and list source

operand.6. If single or double operand instruction, decode and list

destination operand.7. If jump instruction, sign extend the 10-bit PC offset,

multiply by 2, and add to the current PC. List that address.

Instruction Disassembly


43

How to Disassemble MSP430 Code

1. Begin with a “PC” pointing to the first word in program memory.2. Retrieve instruction word and increment PC by 2.


R0 0xf800: 4031 0300 mov.w0xf804: 40b2 5a80 0120 mov.w0xf80a: d0f2 000f 0022 bis.b0xf810: 430e mov.w0xf812: 43a0 09ec mov.w0xf816: 4ec2 0021 mov.b0xf81a: 531e add.w0xf81c: f03e 000f and.w0xf820: 120e push.w0xf822: 403e 0200 mov.w0xf826: 122e push.w0xf828: 8391 0000 sub.w0xf82c: 23fd jne0xf82e: 411e 0002 mov.w0xf832: 5011 0004 add.w0xf836: 3fef jmp


44


3. Find and list the corresponding instruction mnemonic using the opcode (most significant 4-9 bits).

4. Append “.b” or “.w” using the b/w bit when appropriate


0xf800: 4031 0300 mov.w0xf804: 40b2 5a80 0120 mov.w0xf80a: d0f2 000f 0022 bis.b0xf810: 430e mov.w0xf812: 43a0 09ec mov.w0xf816: 4ec2 0021 mov.b0xf81a: 531e add.w0xf81c: f03e 000f and.w0xf820: 120e push.w0xf822: 403e 0200 mov.w0xf826: 122e push.w0xf828: 8391 0000 sub.w0xf82c: 23fd jne0xf82e: 411e 0002 mov.w0xf832: 5011 0004 add.w0xf836: 3fef jmp


45


5. If double operand instruction, decode and list source operand.


0xf800: 4031 0300 mov.w #0x03000xf804: 40b2 5a80 0120 mov.w #0x5a800xf80a: d0f2 000f 0022 bis.b #0x000f0xf810: 430e mov.w #00xf812: 43a0 09ec mov.w #20xf816: 4ec2 0021 mov.b r140xf81a: 531e add.w #10xf81c: f03e 000f and.w #0x000f0xf820: 120e push.w0xf822: 403e 0200 mov.w #0x02000xf826: 122e push.w0xf828: 8391 0000 sub.w #10xf82c: 23fd jne0xf82e: 411e 0002 mov.w 0x0002(r1)0xf832: 5011 0004 add.w 0x0004(r0)0xf836: 3fef jmp


46


6. If single or double operand instruction, decode and list destination operand.


0xf800: 4031 0300 mov.w #0x0300,sp0xf804: 40b2 5a80 0120 mov.w #0x5a80,&0x01200xf80a: d0f2 000f 0022 bis.b #0x000f,&0x00220xf810: 430e mov.w #0,r140xf812: 43a0 09ec mov.w #2,0x09ec(r0)0xf816: 4ec2 0021 mov.b r14,&0x00210xf81a: 531e add.w #1,r140xf81c: f03e 000f and.w #0x000f,r140xf820: 120e push r140xf822: 403e 0200 mov.w #0x0200,r140xf826: 122e push @r140xf828: 8391 0000 sub.w #1,0x0000(r1)0xf82c: 23fd jne0xf82e: 411e 0002 mov.w 0x0002(r1),r140xf832: 5011 0004 add.w 0x0004(r0),r10xf836: 3fef jmp


47


7. If jump instruction, sign extend the 10-bit PC offset, multiply by 2, and add to the current PC. List that address.


0xf800: 4031 0300 mov.w #0x0300,sp0xf804: 40b2 5a80 0120 mov.w #0x5a80,&0x01200xf80a: d0f2 000f 0022 bis.b #0x000f,&0x00220xf810: 430e mov.w #0,r140xf812: 43a0 09ec mov.w #2,0x09ec(r0)0xf816: 4ec2 0021 mov.b r14,&0x00210xf81a: 531e add.w #1,r140xf81c: f03e 000f and.w #0x000f,r140xf820: 120e push r140xf822: 403e 0200 mov.w #0x0200,r140xf826: 122e push @r140xf828: 8391 0000 sub.w #1,0x0000(r1)0xf82c: 23fd jne $-0x00060xf82e: 411e 0002 mov.w 0x0002(r1),r140xf832: 5011 0004 add.w 0x0004(r0),r10xf836: 3fef jmp $-0x0026


48

How to Decode an Operand

1. To decode a source operand:a. Decode the addressing mode from the “As” bits (00=register, 01=indexed,

10=indirect, or 11=indirect auto-increment) and source register from the “S-Reg” bits.

b. If “@R2”, “@R2+”, “R3”, “x(R3)”, “@R3”, or “@R3+”, list appropriate constant preceded by pound sign (ie #1).

c. Else if “x(R0)”, change to symbolic mode, retrieve index (next code word), add index word to PC, increment PC, and list that address as operand (0x8023).

d. Else if “x(R2)”, change to absolute mode, retrieve address (next code word), increment PC, and list address preceded by an ampersand symbol (ie. &addr).

e. Else if “@PC+”, change to immediate mode, retrieve immediate value (next code word), increment PC, and list immediate value preceded by the pound symbol (ie. #100).

f. Else if register mode, list register (ie. Rn).g. Else if indexed mode, retrieve index (next code word), increment PC, and list

index followed by the register in parentheses (ie. 0x0200(R4)).h. Else if indirect mode, list the register preceded by an @ symbol (ie. @R4).i. Else indirect auto-increment mode, list the register preceded by an @ symbol and

followed by a plus symbol (ie. @R4+).2. To decode a destination operand, use the “Ad” bit and the destination

register bits. Follow the same steps as for the source operand (except there will only be register and indexed modes – no constants, immediate, or indirect modes).



49

Addressing ModesInstruction Disassembly

Address Mode As Ad Registers Syntax Operation

Register 00 0 R0-R2, R4-R15 Rn Register Contents.

0 00 – R3 #0 0 Constant source / bit bucket destination

Symbolic 01 1 R0 ADDR (PC+next word) points to operand. (X(PC))

Indexed 01 1 R1, R4-R15 X(Rn) (Rn+X) points to operand. X is next code word.

Absolute 01 1 R2 &ADDR Next code word is the absolute address. (X(SR))

+1 01 – R3 #1 +1 Constant

Indirect 10 – R0-R1,R4-R15 @Rn Rn points to operand.

+4 10 – R2 #4 +4 Constant

+2 10 – R3 #2 +2 Constant

Immediate 11 – R0 #N Next word is the constant N. (@PC+)

Indirect auto-inc 11 – R1,R4-R15 @Rn+ Rn points to operand, Rn is incremented (1 or 2).

+8 11 – R2 #8 +8 Constant

-1 11 – R3 #-1 -1 Constant


50

Quiz

Disassemble the following MSP430 instructions:Address Data0x8010: 40310x8012: 06000x8014: 40B20x8016: 5A1E0x8018: 01200x801a: 430E0x801c: 535E0x801e: F07E0x8020: 000F0x8022: 12300x8024: 000E0x8026: 83910x8028: 00000x802a: 23FD0x802c: 413F0x802e: 3FF6

Quiz


Emulated Instructions

AKA Pseudo-Instructions

52


In addition to the 27 instructions defined by the MSP 430 ISA, there are 24 additional emulated instructions.

The emulated instructions make reading and writing code more easy, but do not have their own op-codes.

Emulated instructions are replaced automatically with native MSP 430 instructions by assembler.

There are no penalties for using emulated instructions.



53


Mnemonic Operation Emulation Description

Arithmetic instructions

ADC(.B or .W) dst dst+Cdst ADDC(.B or .W) #0,dst Add carry to destination

DADC(.B or .W) dst dst+Cdst (decimally)

DADD(.B or .W) #0,dst Decimal add carry to destination

DEC(.B or .W) dst dst-1dst SUB(.B or .W) #1,dst Decrement destination

DECD(.B or .W) dst dst-2dst SUB(.B or .W) #2,dst Decrement destination twice

INC(.B or .W) dst dst+1dst ADD(.B or .W) #1,dst Increment destination

INCD(.B or .W) dst dst+2dst ADD(.B or .W) #2,dst Increment destination twice

SBC(.B or .W) dst dst+0FFFFh+Cdstdst+0FFhdst

SUBC(.B or .W) #0,dst Subtract source and borrow /.NOT. carry from dest.



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INV(.B or .W) dst .NOT.dstdst XOR(.B or .W) #0(FF)FFh,dst

Invert bits in destination

RLA(.B or .W) dst CMSBMSB-1LSB+1LSB0

ADD(.B or .W) dst,dst Rotate left arithmetically

RLC(.B or .W) dst CMSBMSB-1LSB+1LSBC

ADDC(.B or .W) dst,dst Rotate left through carry

Program flow control

BR dst dstPC MOV dst,PC Branch to destination

DINT 0GIE BIC #8,SR Disable (general) interrupts

EINT 1GIE BIS #8,SR Enable (general) interrupts

NOP None MOV #0,R3 No operation

RET @SPPCSP+2SP

MOV @SP+,PC Return from subroutine



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Data instructions

CLR(.B or .W) dst 0dst MOV(.B or .W) #0,dst Clear destination

CLRC 0C BIC #1,SR Clear carry flag

CLRN 0N BIC #4,SR Clear negative flag

CLRZ 0Z BIC #2,SR Clear zero flag

POP(.B or .W) dst @SPtempSP+2SPtempdst

MOV(.B or .W) @SP+,dst

Pop byte/word from stack to destination

SETC 1C BIS #1,SR Set carry flag

SETN 1N BIS #4,SR Set negative flag

SETZ 1Z BIS #2,SR Set zero flag

TST(.B or .W) dst dst + 0FFFFh + 1dst + 0FFh + 1

CMP(.B or .W) #0,dst Test destination



Lecture 3 – MSP430 ISA The Instruction Set Reading: Chapter 5: Architecture of the MSP430...

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Transcript of Lecture 3 – MSP430 ISA The Instruction Set Reading: Chapter 5: Architecture of the MSP430...