Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers...
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Transcript of Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers...
![Page 1: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/1.jpg)
Lecture #22Page 1
ECE 4110– Sequential Logic Design
Lecture #22
• Agenda
1. MSI: Multipliers
• Announcements
1. HW #10 due.
2. Next Quiz 2.
![Page 2: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/2.jpg)
Lecture #22Page 2
Multipliers
• Multipliers
- binary multiplication of an individual bit can be performed using combinational logic:
A * B P
0 0 0
0 1 0 we can say that: P = A·B
1 0 0
1 1 1
- for multi-bit multiplication, we can mimic the algorithm that we use when doing multiplication by hand
ex) 1 2 this number is the "Multiplicand" x 3 4 this number is the "Multiplier" 4 8 1) multiplicand for digit (0) + 3 6 2) multiplicand for digit (1) 4 0 8 3) Sum of all multiplicands
- this is called the "Shift and Add" algorithm
![Page 3: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/3.jpg)
Lecture #22Page 3
Multipliers
• "Shift and Add" Multipliers
- example of Binary Multiplication using our "by hand" method
11 1 0 1 1 - multiplicand x 13 x 1 1 0 1 - multiplier 33 1 0 1 1 11 0 0 0 0 - these are the individual multiplicands 1 0 1 1 + + 1 0 1 1 1 4 3 1 0 0 0 1 1 1 1 - the final product is the sum of all multiplicands
- this is simple and straight forward. BUT, the addition of the individual multiplicand products requires as many as n-inputs.
- we would really like to re-use our Full Adder circuits, which only have 3 inputs.
![Page 4: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/4.jpg)
Lecture #22Page 4
Multipliers
• "Shift and Add" Multipliers
- we can perform the additions of each multiplicand after it is created
- this is called a "Partial Product"
- to keep the algorithm consistent, we use "0000" as the first Partial Product
1 0 1 1 - Original multiplicand x 1 1 0 1 - Original multiplier
0 0 0 0 - Partial Product for 1st multiply 1 0 1 1 - Shifted Multiplicand for 1st multiply 1 0 1 1 - Partial Product for 2nd multiply 0 0 0 0 - Shifted Multiplicand for 2nd multiply 0 1 0 1 1 - Partial Product for 3rd multiply 1 0 1 1 - Shifted Multiplicand for 3rd multiply 1 1 0 1 1 1 - Partial Product for 4th multiply 1 0 1 1 - Shifted Multiplicand for 4th multiply 1 0 0 0 1 1 1 1 - the final product is the sum of all multiplicands
![Page 5: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/5.jpg)
Lecture #22Page 5
Multipliers
• "Shift and Add" Multipliers
- Graphical view of product terms and summation
![Page 6: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/6.jpg)
Lecture #22Page 6
Multipliers
• "Shift and Add" Multipliers
- Graphical View of interconnect for an 8x8 multiplier. Note the Full Adders
![Page 7: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/7.jpg)
Lecture #22Page 7
Multipliers
• "Sequential" Multipliers
- the main speed limitation of the Combinational "Shift and Add" multiplier is the delay through the adder chain.
- in the worst case, the number of delay paths through the adders would be [n + 2(n-2)]
ex) 4-bit = 8 Full Adders 8-bit = 20 Full Adders
- we can decrease this delay by using a register to accumulate the incremental additions as they take place.
- this would reduce the number of operation states to [n-1]
• "Carry Save" Multipliers
- another trick to speed up the multiplication is to break the carry chain
- we can run the 0th carry from the first row of adders into adder for the 2nd row
- a final stage of adders is needed to recombine the carrys. But this reduces the delay to [n+(n-2)]
![Page 8: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/8.jpg)
Lecture #22Page 8
Multipliers
• "Carry Save" Multipliers
![Page 9: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/9.jpg)
Lecture #22Page 9
Signed Multipliers
• Multipliers
- we leaned the "Shift and Add" algorithm for constructing a combinational multiplier
- but this only worked for unsigned numbers
- we can create a signed multiplier using a similar algorithm
• Convert to Positive
- one of the simplest ways is to first convert any negative numbers to positive, then use the unsigned multiplier
- the sign bit is added after the multiplication following:
pos x pos = pos Remember 0=pos and 1=neg is 2's comp so this is an XOR pos x neg = neg neg x pos = neg neg x neg = pos
![Page 10: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/10.jpg)
Lecture #22Page 10
Signed Multipliers
• 2's Comp Multiplier
- remember that in a "Shift and Add', we created a shifted multiplicand
- the shifted multiplicand corresponded to the weight of the multiplier bit
- we can use this same technique for 2's comp remembering that
- the MSB of a 2's comp # is -2(n-1)
- we also must remember that 2's comp addition must
- be on same-sized vectors - the carry is ignored
- we can make partial products the same size as shifted multiplicands by doing a "2's comp sign extend"
ex) 1011 = 11011 = 1110111
- since the MSB has a negative weight, we NEGATE the shifted multiplicand for that bit prior to the last addition.
![Page 11: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/11.jpg)
Lecture #22Page 11
Signed Multipliers
• 2's Comp Shift and Add Multipliers
- we can perform the additions of each multiplicand after it is created
- this is called a "Partial Product"
- to keep the algorithm consistent, we use "0000" as the first Partial Product
1 0 1 1 - Original multiplicand x 1 1 0 1 - Original multiplier
0 0 0 0 0 - Partial Product for 1st multiply w/ Sign Extension 1 1 0 1 1 - Shifted Multiplicand for 1st multiply w/ Sign Extension 1 1 1 0 1 1 - Partial Product for 2nd multiply w/ Sign Extension 0 0 0 0 0 - Shifted Multiplicand for 2nd multiply w/ Sign Extension 1 1 1 1 0 1 1 - Partial Product for 3rd multiply w/ Sign Extension 1 1 0 1 1 - Shifted Multiplicand for 3rd multiply w/ Sign Extension 1 1 1 0 0 1 1 1 - Partial Product for 4th multiply w/ Sign Extension 0 0 1 0 1 - NEGATED Shifted Multiplicand for 4th multiply w/ Sign Extension 1 0 0 0 0 1 1 1 1 - the final product is the sum of all multiplicands ignore Carry_Out
![Page 12: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/12.jpg)
Lecture #22Page 12
Division
• Division - "Repeated Subtraction"
- a simple algorithm to divide is to count the number of times you can subtract the divisor from the dividend
- this is slow, but simple
- the number of times it can be subtracted without going negative is the "Quotient"
- if the subtracted value results in a zero/negative number, whatever was left prior to the subtraction is the "Remainder"
![Page 13: Lecture #22 Page 1 ECE 4110– Sequential Logic Design Lecture #22 Agenda 1.MSI: Multipliers Announcements 1.HW #10 due. 2.Next Quiz 2.](https://reader034.fdocuments.us/reader034/viewer/2022051401/56649e405503460f94b30f81/html5/thumbnails/13.jpg)
Lecture #22Page 13
Division
• Division - "Shift and Subtract"
- Division is similar to multiplication, but instead of "Shift and Add", we "Shift and Subtract"