Lecture 21

OUTLINE

The MOSFET (cont’d) • P-channel MOSFET• CMOS inverter analysis• Sub-threshold current• Small signal model

Reading: Pierret 17.3; Hu 6.7, 7.2

P-Channel MOSFET• The PMOSFET turns on when VGS < VT

– Holes flow from SOURCE to DRAIN DRAIN is biased at a lower potential than the SOURCE

• In a CMOS technology, the PMOS & NMOS threshold voltages are usually symmetric about 0, i.e. VTp = -VTn

P+ P+

N

GATEVS VD

VG

ID

VB

• VDS < 0

• IDS < 0

• |IDS| increases with

• |VGS - VT|

• |VDS| (linear region)

EE130/230M Spring 2013 Lecture 21, Slide 2

DSDSTpGSeffpoxeDS VVm

VVCL

WI )

2(,

Long-Channel PMOSFET I-V

• Linear region:

• Saturation region:

2, )(

2 TpGSeffpoxeDsatDS VVCmL

WII

m

VVV

TpGS

DS

0

m

VVV

TpGS

DS

m = 1 + (3Toxe/WT) is the bulk-charge factor

EE130/230M Spring 2013 Lecture 21, Slide 3

CMOS Inverter: Intuitive Perspective

VDD

Rn

VIN = VDD

CIRCUIT SWITCH MODELS

VDD

Rp

VIN = 0V

VOUT = 0V VOUT = VDD

Low static power consumption, sinceone MOSFET is always off in steady state

VDD

VIN VOUT

S

D

G

GS

D

EE130/230M Spring 2013 Lecture 21, Slide 4

Voltage Transfer Characteristic

VIN

VOUT

VDD

VDD00

N: offP: lin

N: linP: off

N: linP: sat

N: satP: lin

N: satP: sat

A B D E

C

EE130/230M Spring 2013 Lecture 21, Slide 5

CMOS Inverter Load-Line Analysis

VOUT=VDSn

IDn=-IDp

0

IDn=-IDp

–V

GSp =VIN -V

DD

+

VIN = VDD + VGSp

increasingVIN

increasingVIN

VIN = 0 V VIN = VDD

VDD

VOUT = VDD + VDSp

VDSp = 0VDSp = - VDD

–

VDSp=VOUT-VDD

+

0

EE130/230M Spring 2013 Lecture 21, Slide 6

VOUT=VDSn

IDn=-IDp

00

Load-Line Analysis: Region A

VIN VTn

IDn=-IDp

–V

GSp =VIN -V

DD

+

–

VDSp=VOUT-VDD

+

VDD

EE130/230M Spring 2013 Lecture 21, Slide 7

00

Load-Line Analysis: Region B

VDD/2 > VIN > VTn

IDn=-IDp

–V

GSp =VIN -V

DD

+

–

VDSp=VOUT-VDD

+

VOUT=VDSn

IDn=-IDp

VDD

EE130/230M Spring 2013 Lecture 21, Slide 8

00

Load-Line Analysis: Region D

VDD – |VTp| > VIN > VDD/2IDn=-IDp

–V

GSp =VIN -V

DD

+

–

VDSp=VOUT-VDD

+

VOUT=VDSn

IDn=-IDp

VDD

EE130/230M Spring 2013 Lecture 21, Slide 9

00

Load-Line Analysis: Region E

VIN > VDD – |VTp|IDn=-IDp

–V

GSp =VIN -V

DD

+

–

VDSp=VOUT-VDD

+

VOUT=VDSn

IDn=-IDp

VDD

EE130/230M Spring 2013 Lecture 21, Slide 10

MOSFET Effective Drive Current, IEFF

NMOS DRAIN VOLTAGE = VOUT

VIN = VDD

NM

OS

DRA

IN C

URR

ENT

VDD0.5VDD

IDsat

V2 IEFF =IH + IL

2tpHL

tpLH

V1 TIME

VDD

VDD/2V1 V2 V3

CMOS inverter chain:V3

VIN = ½VDD

IH

ILGND

VDDS

S

D

DVIN

VOUT

CMOS inverter:

M. H. Na et al., IEDM Technical Digest, pp. 121-124, 2002

EE130/230M Spring 2013 Lecture 21, Slide 11

Propagation Delay, d

d is reduced by increasing IEFF and reducing load capacitance C

CMOS inverter chain: VDD

VDD

Voltage waveforms:

EFF

DDpLHpHLd I

CVtt

22

1

EE130/230M Spring 2013 Lecture 21, Slide 12

Sub-Threshold Current• For |VG| < |VT|, MOSFET current flow is limited by carrier

diffusion into the channel region.

• The electric potential in the channel region varies linearly with VG, according to the capacitive voltage divider formula:

• As the potential barrier to diffusion increases linearly with decreasing VG, the diffusion current decreases exponentially:

mkTqVDS

GeI /

EE130/230M Spring 2013

GGdepoxe

oxeC V

mV

CC

CV

1

Lecture 21, Slide 13

Sub-Threshold Swing, S

)1)(10(

)(log

min,

1

10

oxe

dep

GS

DS

C

Cln

q

kT

dV

IdS

EE130/230M Spring 2013 Lecture 21, Slide 14

Inverse slope is subthreshold swing, S[mV/dec]

log ID

VT

VGS0NMOSFET Energy Band Profile

incr

easi

ng E

distance

n(E) exp(-E/kT)

SourceDrain

increasing VGS

VT Design Trade-off

EE130/230M Spring 2013 Lecture 21, Slide 15

• Low VT is desirable for high ON current:IDsat (VDD - VT) 1 < < 2

• But high VT is needed for low OFF current:

VT cannot be aggressively reduced!

Low VT

High VT

IOFF,high VT

IOFF,low VT

VGS

log ID

0

How to minimize S?

EE130/230M Spring 2013 Lecture 21, Slide 16

)1)(10( min,

oxe

dep

C

Cln

q

kTS

MOSFET Small Signal Model• Conductance parameters:

)(

0

TGSoxeeff

constVG

Dm

Dsat

constVD

Dd

VVmL

CW

V

Ig

IV

Ig

D

G

gmddd vgvgi

EE130/230M Spring 2013

A small change in VG or VDS will result in a small change in ID

Lecture 21, Slide 17

low-frequency:

high-frequency:

Parasitic Components

EE130/230M Spring 2013 Lecture 21, Slide 18

MOSFET Cutoff Frequency, fT

Higher MOSFET operating frequency is achieved by decreasing the channel length L

)(22 2 TGS

eff

oxe

mT VV

mLC

gf

EE130/230M Spring 2013 Lecture 21, Slide 19

The cut-off frequency fT is defined as the frequency when the current gain is reduced to 1.

input current = GGvCj

output current = Gmvg

vG here is ac signalCG is approximately equal to the gate capacitance, W L Cox

At the cutoff frequency (T = 2fT): 12

GGT

Gm

vCf

vg