Lecture 18 OUTLINE The MOS Capacitor (cont’d) – Effect of oxide charges – V T adjustment –...

Lecture 18

OUTLINE• The MOS Capacitor (cont’d)

– Effect of oxide charges

– VT adjustment

– Poly-Si gate depletion effect

Reading: Pierret 18.2-18.3; Hu 5.7-5.9

Oxide ChargesIn real MOS devices, there is always some charge within the oxide and at the Si/oxide interface.

EE130/230A Fall 2013 Lecture 18, Slide 2

• Within the oxide:– Trapped charge Qot

• High-energy electrons and/or holes injected into oxide

– Mobile charge QM• Alkali-metal ions, which have

sufficient mobility to drift in oxide under an applied electric field

• At the interface:– Fixed charge QF

• Excess Si (?)– Trapped charge QIT

• Dangling bonds

R. F. Pierret, Semiconductor Device Fundamentals, Fig. 18.4

Effect of Oxide Charges• In general, charges in the oxide cause a shift in the

gate voltage required to reach threshold condition:

(x is defined to be 0 at metal-oxide interface)

For example, positive charge in the oxide near to the p-type Si substrate (for an NMOS device) helps to deplete the surface of holes, so that the gate voltage that must be applied to invert the surface (to become n-type) is reduced, i.e. VT is reduced VT is negative.

• In addition, oxide charge can affect the field-effect mobility of mobile carriers (in a MOSFET) due to Coulombic scattering.

ox

oxSiO

T dxxxV0

)(1

2


Fixed Oxide Charge, QF

ox

FMSFB C

QV Ec

EFS

Ev

Ec= EFM

Ev

M O S

3.1 eV

4.8 eV

|qVFB |

qQF / Cox


Parameter Extraction from C-VFrom a single C-V measurement, we can extract muchinformation about the MOS device:• Suppose we know the gate material is heavily doped n-type

poly-Si (M= 4.1 eV), and the gate dielectric is SiO2 (r = 3.9):

1. From Cmax = Cox we can determine oxide thickness xo

2. From Cmin and Cox we can determine substrate doping (by iteration)

3. From substrate doping and Cox we can find flat-band capacitance CFB

4. From the C-V curve, we can find

5. From M, S, Cox, and VFB we can determine Qf

FBCCGFB VV


Determination of M and QF

FSiO

oMSFB Q

xV

2

Measure C-V characteristics of capacitors with different oxide thicknesses. Plot VFB as a function of xo:


C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-21

Mobile Oxide Charge, QM

FBoxM VCQ

Na+ located at upper SiO2 interface no effect on VFB

Na+ located at lower SiO2 interface reduces VFB VFB

ox

SIT

x

oxSiOox

FMSFB C

Qdxxx

C

QV

o )()(

1

02

Positive oxide charge shifts the flatband voltage in the negative direction:

Lecture 19, Slide 7EE130/230A Fall 2013

Bias-Temperature Stress (BTS) Measurement

R. F. Pierret, Semiconductor Device Fundamentals, p. 657

Interface Trap Charge, QIT

Traps cause “sloppy” C-V and also greatly degrade mobility in channel

ox

SITG C

QV

)(

“Donor-like” traps arecharge-neutral whenfilled, positively chargedwhen empty

Positive oxide chargecauses C-V curve toshift toward left.As VG decreases, there is more positive interface charge and hence the “ideal C-V curve” is shifted more to the left.

(a)

(a) (b)

(b)

(c)

(c)




VT Adjustment• In modern IC fabrication processes, the threshold voltages of

MOS transistors are adjusted by adding dopants to the Si by a process called “ion implantation”:– A relatively small dose NI (units: ions/cm2) of dopant atoms is

implanted into the near-surface region of the semiconductor– When the MOS device is biased in depletion or inversion, the

implanted dopants add to (or substract from) the depletion charge near the oxide-semiconductor interface.

ox

IT C

qNV

atomsacceptor for 0

atomsdonor for 0

I

I

N

N


Poly-Si Gate Technology• A heavily doped film of polycrystalline silicon (poly-Si) is often

employed as the gate-electrode material in MOS devices.

– There are practical limits to the electrically active dopant concentration (usually less than 1x1020 cm-3)

The gate must be considered as a semiconductor, rather than a metal

p-type Si

n+ poly-Si

n-type Si

p+ poly-Si

NMOS PMOS


MOS Band Diagram w/ Gate Depletion

)( TpolyGoxinv VVVCQ

How can gate depletion be minimized?

VG is effectively reduced:Ec

EFSEv

Ev

qVG

qS

WT

p-type Sin+ poly-Si gate

Ec

qVpoly

Wpoly

Si biased to inversion:

poly

polySipoly qN

VW

2


Gate Depletion Effect

n+ poly-Si

Gauss’s Law dictates that Wpoly = oxEox / qNpoly

)3/(

11

2

2

11

polyo

SiO

Si

poly

SiO

o

polyox

Wx

Wx

CCC

xo is effectively increased:

)3/()( 2

polyo

SiOTGinv Wx

VVQ

p-type Si

-- - - --

+ + + + + +

N+

+ +

-- -

Cpoly

Cox


Example: Gate Depletion EffectThe voltage across a 2 nm oxide is Vox = 1 V. The active dopant concentration within the n+ poly-Si gate is Npoly = 8 1019 cm-3 and the Si substrate doping concentration NA is 1017 cm-3.

Find (a) Wpoly , (b) Vpoly , and (c) VT .

Solution:

(a) Wpoly = oxEox / qNpoly = oxVox / xoqNpoly

cm103.1

]cm[108]C[106.1]cm[102

)V][1F/cm][1085.89.3

7

3-19197

14


(b) poly

polySipoly qN

VW

2

V 11.02/2 Sipolypolypoly WqNV

(c)

V 97.0V 11.0V 1V 84.0V 98.0

V 98.0ln2

2

T

i

AGFB

polyoxFFBT

V

n

N

q

kT

q

EV

VVVV


Inversion-Layer Thickness, Tinv

The average inversion-layer location below the Si/SiO2 interface is called the inversion-layer thickness, Tinv .


C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-24

Effective Oxide Thickness, Toxe

33invpoly

ooxe

TWxT

(VG + VT)/Toxe can be shown to be the average electric field in the inversion layer.

Tinv of holes is larger than that of electrons due to difference in effective masses.EE130/230A Fall 2013 Lecture 18, Slide 16 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-25

Effective Oxide Capacitance, Coxe

33invpoly

ooxe

TWxT

dVVVCQ T

V

V oxeinv

G

T

)(

EE130/230A Fall 2013 Lecture 18, Slide 17 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-26

Lecture 18 OUTLINE The MOS Capacitor (cont’d) – Effect of oxide charges – V T adjustment –...

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