Lecture 16: Storage and I/O
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Transcript of Lecture 16: Storage and I/O
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Lecture 16: Storage and I/O
EEN 312: Processors: Hardware, Software, and Interfacing
Department of Electrical and Computer Engineering
Spring 2014, Dr. Rozier (UM)
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QUIZ
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Introduction• I/O devices can be characterized by
– Behaviour: input, output, storage– Partner: human or machine– Data rate: bytes/sec, transfers/sec
• I/O bus connections
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I/O System Characteristics
• Dependability is important– Particularly for storage devices
• Performance measures– Latency (response time)– Throughput (bandwidth)– Desktops & embedded systems
• Mainly interested in response time & diversity of devices– Servers
• Mainly interested in throughput & expandability of devices
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Dependability
• Fault: failure of a component– May or may not lead to
system failure
Service accomplishmentService delivered
as specified
Service interruptionDeviation from
specified service
FailureRestoration
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Dependability Measures
• Reliability: mean time to failure (MTTF)• Service interruption: mean time to repair (MTTR)• Mean time between failures
– MTBF = MTTF + MTTR
• Availability = MTTF / (MTTF + MTTR)• Improving Availability
– Increase MTTF: fault avoidance, fault tolerance, fault forecasting
– Reduce MTTR: improved tools and processes for diagnosis and repair
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Disk Storage• Nonvolatile, rotating magnetic storage
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Disk Sectors and Access
• Each sector records– Sector ID– Data (512 bytes - 4096 bytes currently)– Error correcting code (ECC)
• Used to hide defects and recording errors– Synchronization fields and gaps
• Access to a sector involves– Queuing delay if other accesses are pending– Seek: move the heads– Rotational latency– Data transfer– Controller overhead
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Disk Access Example
• Given– 512B sector, 15,000rpm, 4ms average seek time,
100MB/s transfer rate, 0.2ms controller overhead, idle disk
• Average read time– 4ms seek time
+ ½ / (15,000/60) = 2ms rotational latency+ 512 / 100MB/s = 0.005ms transfer time+ 0.2ms controller delay= 6.2ms
• If actual average seek time is 1ms– Average read time = 3.2ms
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Disk Performance Issues
• Manufacturers quote average seek time– Based on all possible seeks– Locality and OS scheduling lead to smaller actual average
seek times
• Smart disk controller allocate physical sectors on disk– Present logical sector interface to host– SCSI, ATA, SATA
• Disk drives include caches– Prefetch sectors in anticipation of access– Avoid seek and rotational delay
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Flash Storage
• Nonvolatile semiconductor storage– 100× – 1000× faster than disk– Smaller, lower power, more robust– But more $/GB (between disk and DRAM)
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Flash Types
• NOR flash: bit cell like a NOR gate– Random read/write access– Used for instruction memory in embedded systems
• NAND flash: bit cell like a NAND gate– Denser (bits/area), but block-at-a-time access– Cheaper per GB– Used for USB keys, media storage, …
• Flash bits wears out after 1000’s of accesses– Not suitable for direct RAM or disk replacement– Wear leveling: remap data to less used blocks
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• Stores information in an array of cells made from floating gate transistors.
• In a single-level cell (SLC) device, each cell stores one bit.
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Floating gate transistor
• Floating-gate MOSFET (FGMOS)– Field effect transistor– Similar to a conventional MOSFET, but the gate is
electrically isolated.– Creates a floating node in DC.– Inputs are only capacitively connected to the
floating gate.– Surrounding the gate in highly resistive material
means the charge will remain unchanged for long periods.
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• Each transistor has two gates instead of one.– Control gate (CG)– Floating gate (FG)
insulated by oxide layer– Any electrons placed in
FG become trapped.
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• When the FG holds a charge it screens and partially cancels the field from the CG.
• More voltage has to be applied to the CG to make the channel conduct.
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• Cells can be read by applying an intermediate voltage to test if it is conducting or insulating.
• Current flow then is read as 1 or 0.
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Multi-Level Cells
• Cells can contain more than 1-bit
• Increase the number of states the cell can be in, increases the number of bits that can be stored.
• Generally we have four possible states per MLC.
• How many bits?
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Multi-Level Cells
• More cells makes for cheaper FLASH.
• Also means more prone to errors or faults.
• Samsung has just patented 8-state technology.
• How many bits?
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Programming and Erasing
• We need high voltage to program and erase.• Only have a single voltage supply
– Use charge pumps to produce high on-chip voltages.
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Programming and Erasing
• Charge pumps– DC to DC converter– Uses capacitors to store charge and create a
higher or lower voltage source.
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Programming and Erasing
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For next time
• Read Chapter 6, Sections 6.1 – 6.5