Lecture 11 Processor Microarchitecture (Part 2) · Hardwired FSM 7 . Control Signal Output Table 8...
Transcript of Lecture 11 Processor Microarchitecture (Part 2) · Hardwired FSM 7 . Control Signal Output Table 8...
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Xuan ‘Silvia’ Zhang Washington University in St. Louis
http://classes.engineering.wustl.edu/ese566/
Lecture 11 Processor Microarchitecture (Part 2)
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Quiz: Adding a New Auto-Incrementing Load Instruction
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Single-Cycle Processor Control Unit
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Estimating Cycle Time—Longest Critical Path
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Quiz: Adding a New Auto-Incrementing Load Instruction
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FSM Processor Control Unit
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Hardwired FSM
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Control Signal Output Table
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Vertically Microcoded FSM
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Vertically Microcoded FSM
• Use memory array to encode control logic and state transition logic – called control state – more flexible than random logic
• Enable a more systematic approach to implementing complex multi-cycle instructions
• Microcoding can produce good performance – if accessing the control store is much faster than
accessing main memory
• Read-only control stores might be replaceable – enable in-field updates
• Read-write control stores can simplify diagnostics and microcode patches
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Estimating Cycle Time
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PARCv1 Pipelined Processor
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High-Level Idea for Pipelined Processors
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High-Level Idea for Pipelined Processors
• Key pipeline traits – multiple transactions operate simultaneously using
different resources – pipelining does not help the transaction latency – pipelining does help the transaction throughput – potential speed up is proportional to the number of
pipelined stages – potential speed up is limited by the slowest pipeline
stage – potential speed up is reduced by time to fill the
pipeline
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High-Level Idea for Pipelined Processors
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Pipelined Processor Datapath and Control Unit
• Incrementally develop an unpipelined datapath • Keep data flowing from left to right • Position control signal table early in the diagram • Divide datapath/control into stages by inserting
pipeline registers • Keep the pipeline stages roughly balanced • Forward arrows should avoid “skipping” pipeline
registers • Backward arrows will need careful consideration
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Pipelined Processor Datapath and Control Unit
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Quiz: Adding a New Auto-Incrementing Load Instruction
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Pipeline Hazards
• RAW data hazards – an instruction depends on a data value produced by an
earlier instruction
• Control hazards – whether or not an instruction should be executed
depends on a control decision made by an earlier one
• Structural hazards – an instruction in the pipeline needs a resource being
used by another instruction in the pipeline
• WAW and WAR name hazards – an instruction in the pipeline is writing a register that
an earlier instruction in the pipeline is either writing or reading
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Proposed Solutions: Stalling and Squashing Instructions
• Stalling – an instruction originates a stall due to a hazard,
causing all instructions earlier in the pipeline to also stall. When the hazard is resolved, the instruction no longer needs to stall and the pipeline starts flowing again.
• Squashing – an instruction originates a squash due to a hazard, and
squashes all previous instructions in the pipeline (but not itself). We restart the pipeline to begin executing a new instruction sequence.
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Control Logic with No Stalling and No Squashing
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Control Logic with Stalling and No Squashing
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Control Logic with Stalling and Squashing
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Control Logic with Stalling and Squashing
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Questions?
Comments?
Discussion?
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Acknowledgement
Cornell University, ECE 4750
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