Lecture 1: Circuits & Layout - vlsi.hongik.ac.krvlsi.hongik.ac.kr/lecture/이전 강의...
Transcript of Lecture 1: Circuits & Layout - vlsi.hongik.ac.krvlsi.hongik.ac.kr/lecture/이전 강의...
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Introduction toCMOS VLSICMOS VLSI
Design
Lecture 1: Circuits & Layout
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OutlineOutline A Brief History A Brief History CMOS Gate Design P T i t Pass Transistors CMOS Latches & Flip-Flops St d d C ll L t Standard Cell Layouts Stick Diagrams
CMOS VLSI Design1: Circuits & Layout Slide 2
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A Brief HistoryA Brief History 1958: First integrated circuit 1958: First integrated circuit
– Flip-flop using two transistors– Built by Jack Kilby at Texas Instrumentsy y
2003– Intel Pentium 4 processor (55 million transistors)– 512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 yearsNo other technology has grown so fast so long– No other technology has grown so fast so long
Driven by miniaturization of transistors– Smaller is cheaper, faster, lower in power!p , , p– Revolutionary effects on society
CMOS VLSI Design1: Circuits & Layout Slide 3
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Annual SalesAnnual Sales 1018 transistors manufactured in 2003 1018 transistors manufactured in 2003
– 100 million for every human on the planet
200
Globa
100
150
l Sem
icon(B
illions o
50
nductor Bil
of US
$)
01982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002
Year
lings
CMOS VLSI Design1: Circuits & Layout Slide 4
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Invention of the TransistorInvention of the Transistor Vacuum tubes ruled in first half of 20th century Large Vacuum tubes ruled in first half of 20th century Large,
expensive, power-hungry, unreliable 1947: first point contact transistor 1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell LabsRead Crystal Fire– Read Crystal Fireby Riordan, Hoddeson
CMOS VLSI Design1: Circuits & Layout Slide 5
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Transistor TypesTransistor Types Bipolar transistors Bipolar transistors
– npn or pnp silicon structureS ll t i t thi b l t l– Small current into very thin base layer controls large currents between emitter and collectorBase currents limit integration density (전류 sum)– Base currents limit integration density (전류 sum)
Metal Oxide Semiconductor Field Effect TransistorsnMOS and pMOS MOSFETS– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current between source and drainbetween source and drain
– Low power allows very high integration
CMOS VLSI Design1: Circuits & Layout Slide 6
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MOS Integrated Circuits 1970’s processes usually had only nMOS transistors
MOS Integrated Circuits 1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle powerIntel 1101 256-bit SRAM Intel 4004 4-bit Proc
CMOS VLSI Design1: Circuits & Layout Slide 7
p p p
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Moore’s LawMoore’s Law 1965: Gordon Moore plotted transistor on each chip 1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scaleT i t t h d bl d 26 th– Transistor counts have doubled every 26 months
1,000,000,000
Integration Levels
Trans Intel486Pentium
Pentium ProPentium II
Pentium IIIPentium 4
1,000,000
10,000,000
100,000,000Integration Levels
SSI: 10 gates
istors
40048008
8080
8086
80286Intel386
1 000
10,000
100,000 MSI: 1000 gates
LSI: 10,000 gates
Year
1,000
1970 1975 1980 1985 1990 1995 2000
, g
VLSI: > 10k gates
CMOS VLSI Design1: Circuits & Layout Slide 8
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Corollaries Corollaries (..에 다른 귀결)
Many other factors grow exponentially Many other factors grow exponentially – Ex: clock frequency, processor performance
10,000
1,000
,
4004
8008
100
8080
8086
80286
Intel386
Clock S
peed (M
1
10 Intel486
Pentium
Pentium Pro/II/III
Pentium 4
MH
z)
Year
1970 1975 1980 1985 1990 1995 2000 2005
CMOS VLSI Design1: Circuits & Layout Slide 9
Year
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CMOS Gate DesignCMOS Gate Design Activity: Activity:
– Sketch a 4-input CMOS NAND gate
CMOS VLSI Design1: Circuits & Layout Slide 10
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CMOS Gate DesignCMOS Gate Design Activity: Activity:
– Sketch a 4-input CMOS NOR gate
A
BB
C
DY
CMOS VLSI Design1: Circuits & Layout Slide 11
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Complementary CMOSComplementary CMOS Complementary CMOS logic gates Complementary CMOS logic gates
– nMOS pull-down networkMOS ll t k
pMOSpull-up– pMOS pull-up network
– a.k.a. static CMOS
pull-upnetwork
outputinputs
nMOSpull-downnetwork
Pull-up OFF Pull-up ONp pPull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)Pull down ON 0 X (crowbar)
CMOS VLSI Design1: Circuits & Layout Slide 12
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Series and ParallelSeries and Parallel nMOS: 1 = ON a a a a a
nMOS: 1 = ON pMOS: 0 = ON S i b th t b ON
(a)
a
b b
g1
g2
0
0
b
0
1
b
1
0
b
1
1
OFF OFF OFF ON
Series: both must be ON Parallel: either can be ON
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
(b)
b b b b b
ON OFF OFF OFF
a a
g1 g2 0 0
a
0
a
1
a
11 0 1
(c)
b b
g1 g2 0 0
OFF ON ON ON
b
0
b
1
b
11 0 1
(d) ON ON ON OFF
a
b
0 0
a
b
0
a
b
1
a
b
11 0 1
a
b
g1 g2
CMOS VLSI Design1: Circuits & Layout Slide 13
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Conduction ComplementConduction Complement Complementary CMOS gates always produce 0 or 1 Complementary CMOS gates always produce 0 or 1 Ex: NAND gate
S i MOS Y 0 h b th i t 1– Series nMOS: Y=0 when both inputs are 1– Thus Y=1 when either input is 0
R i ll l MOS Y– Requires parallel pMOS
R l f C d ti C l t
A
B
Y
Rule of Conduction Complements– Pull-up network is complement of pull-down– Parallel -> series, series -> parallel
CMOS VLSI Design1: Circuits & Layout Slide 14
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Compound GatesㅁAND
Compound Gates Compound gates can do any inverting function Compound gates can do any inverting function Ex: (AND-AND-OR-INVERT, AOI22)Y A B C D
A C A CA
B
C
D
A
B
C
D
(a) (b)
A B C DA B
C D
(c) (d)
B
D
YA
CA
CB Y
A
B
C
D
CD
(e)
(f)
CMOS VLSI Design1: Circuits & Layout Slide 15
( )
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Example: O3AIExample: O3AI Y A B C D Y A B C D
CMOS VLSI Design1: Circuits & Layout Slide 16
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Example: O3AI Example: O3AI Y A B C D Y A B C D
A
B
A
YDC
A B C
D
A B C
CMOS VLSI Design1: Circuits & Layout Slide 17
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Signal StrengthSignal Strength Strength of signal Strength of signal
– How close it approximates ideal voltage source V d GND il t t 1 d 0 VDD and GND rails are strongest 1 and 0 nMOS pass strong 0
B t d d d k 1– But degraded or weak 1 pMOS pass strong 1
B d d d k 0– But degraded or weak 0 Thus nMOS are best for pull-down network
CMOS VLSI Design1: Circuits & Layout Slide 18
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Pass TransistorsPass Transistors Transistors can be used as switches Transistors can be used as switches
g
s d
gg
s d
CMOS VLSI Design1: Circuits & Layout Slide 19
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Pass TransistorsPass Transistors Transistors can be used as switches Transistors can be used as switches
g g = 0 Input Outputg = 1
s ds d
g = 1d
0 strong 0g
g = 1s d 1 degraded 1
g g = 0 Input Output0g
s d
g 0s d
g = 1
0 degraded 0Input Outputg = 0
g = 0s d strong 1
g = 0
CMOS VLSI Design1: Circuits & Layout Slide 20
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Transmission GatesTransmission Gates Pass transistors produce degraded outputs Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well
CMOS VLSI Design1: Circuits & Layout Slide 21
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Transmission GatesTransmission Gates Pass transistors produce degraded outputs Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well
g = 0, gb = 1a b 0 t 0
Input Output
g g = 1, gb = 0a b
g = 1, gb = 0a b
0 strong 0
1 strong 1gb
a b g = 1, gb = 0ggb
g g ga b
gb
a b
gb
a b
gb
CMOS VLSI Design1: Circuits & Layout Slide 22
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TristatesTristates Tristate buffer produces Z when not enabled Tristate buffer produces Z when not enabled
ENEN A Y0 0 A Y
EN
0 11 01 1
EN1 1
A Y
EN
CMOS VLSI Design1: Circuits & Layout Slide 23
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TristatesTristates Tristate buffer produces Z when not enabled Tristate buffer produces Z when not enabled
ENEN A Y0 0 Z A Y
EN
0 1 Z1 0 01 1 1
EN1 1 1
A Y
EN
CMOS VLSI Design1: Circuits & Layout Slide 24
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Nonrestoring TristateNonrestoring Tristate Transmission gate acts as tristate buffer Transmission gate acts as tristate buffer
– Only two transistorsB t t i– But nonrestoring• Noise on A is passed on to Y
EN
A Y
ENCMOS VLSI Design1: Circuits & Layout Slide 25
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Tristate InverterTristate Inverter Tristate inverter produces restored output Tristate inverter produces restored output
– Violates conduction complement ruleB t Z t t– Because we want a Z output
A
YEN
EN
CMOS VLSI Design1: Circuits & Layout Slide 26
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Tristate InverterTristate Inverter Tristate inverter produces restored output Tristate inverter produces restored output
– Violates conduction complement ruleB t Z t t– Because we want a Z output
A AA
Y Y YEN
EN
EN = 0Y = 'Z'
EN = 1Y = A
CMOS VLSI Design1: Circuits & Layout Slide 27
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MultiplexersMultiplexers 2:1 multiplexer chooses between two inputs 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
S
D00 X 0
0 X 1
1 0 X
0
1
D0
D1Y
1 0 X
1 1 X
CMOS VLSI Design1: Circuits & Layout Slide 28
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MultiplexersMultiplexers 2:1 multiplexer chooses between two inputs 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0 0
S
D00 X 0 0
0 X 1 1
1 0 X 0
0
1
D0
D1Y
1 0 X 0
1 1 X 1
CMOS VLSI Design1: Circuits & Layout Slide 29
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Gate Level Mux DesignGate-Level Mux Design (too many transistors)Y SD SD
How many transistors are needed?1 0 (too many transistors)Y SD SD
CMOS VLSI Design1: Circuits & Layout Slide 30
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Gate Level Mux DesignGate-Level Mux Design (too many transistors)Y SD SD
How many transistors are needed? 201 0 (too many transistors)Y SD SD
D1
D0S YD0 Y
44
22 Y
D1S 4
4 22 Y
2D0S
CMOS VLSI Design1: Circuits & Layout Slide 31
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Transmission Gate MuxTransmission Gate Mux Nonrestoring mux uses two transmission gates Nonrestoring mux uses two transmission gates
CMOS VLSI Design1: Circuits & Layout Slide 32
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Transmission Gate MuxTransmission Gate Mux Nonrestoring mux uses two transmission gates Nonrestoring mux uses two transmission gates
– Only 4 transistors (Compared to 20 @previous slide)SS
D0D0
YSD1
S
CMOS VLSI Design1: Circuits & Layout Slide 33
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Inverting MuxInverting Mux Inverting multiplexer Inverting multiplexer
– Use compound AOI22O i f t i t t i t– Or pair of tristate inverters
– Essentially the same thing N i ti lti l d i t @ t t Noninverting multiplexer needs an inverter @output
D0 D1 SD0 S
S
D0 D1
Y
S
D0Y
0S
Y
D0
D1
S
S
S
S
S
S
D1 1SSS S
CMOS VLSI Design1: Circuits & Layout Slide 34
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4:1 Multiplexer4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects 4:1 mux chooses one of 4 inputs using two selects
CMOS VLSI Design1: Circuits & Layout Slide 35
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4:1 Multiplexer4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxesO f t i t t– Or four tristates
D0
S1S0 S1S0 S1S0 S1S0
S0
D0 0
1
S1
D0
D1D1 1
0
1
0
1Y
D2
D3
D2
Y
1D3
D3
CMOS VLSI Design1: Circuits & Layout Slide 36
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D LatchD Latch When CLK = 1 latch is transparent When CLK = 1, latch is transparent
– D flows through to Q like a buffer Wh CLK 0 th l t h i When CLK = 0, the latch is opaque
– Q holds its old value independent of D k t t l t h l l iti l t h
also known as a.k.a. transparent latch or level-sensitive latch
CLK CLK
D Qch
D
D Q
Latc
Q
CMOS VLSI Design1: Circuits & Layout Slide 37
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D Latch DesignD Latch Design Multiplexer chooses D or old Q Multiplexer chooses D or old Q
CLK
1
0
D QCLK
DQ Q
Q
0CLKCLK
CLK
CMOS VLSI Design1: Circuits & Layout Slide 38
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D Latch OperationD Latch Operation
D Q
QD Q
Q
CLK = 1 CLK = 0
CLK
D
CLK
Q
CMOS VLSI Design1: Circuits & Layout Slide 39
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D Flip flopD Flip-flop When CLK rises D is copied to Q When CLK rises, D is copied to Q At all other times, Q holds its value k iti d t i d fli fl t l a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
CLK
op
CLK
D Q
D No change here
FlD QQ
CMOS VLSI Design1: Circuits & Layout Slide 40
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D Flip flop DesignD Flip-flop Design Built from master and slave D latches (transparent Built from master and slave D latches (transparent
latch or level-sensitive latch)CLKC
QMCLK
CLK
Q
CLK
CLK
CLK
DCLK
CLK CLKCLK
CLK
CLK
CLK
CLK
Latc
h
Latc
h
D QQM
CLK
CLKCLK
CMOS VLSI Design1: Circuits & Layout Slide 41
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D Flip flop OperationD Flip-flop OperationQMD
CLK = 0
QQM
D QMQ
CLK = 1
CLK
D
Q
CMOS VLSI Design1: Circuits & Layout Slide 42
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Race ConditionRace Condition Back to back flops can malfunction from clock skew Back-to-back flops can malfunction from clock skew
– Second flip-flop fires lateS fi t fli fl h d t it lt– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition(Should be avoided – 2nd FF should capture the previous data held (hold time))
CLK1 CLK2
CLK1
CLK2CLK1
D Q1op op
CLK2
Q2
CLK2
Q1D Fl
o
Flo Q2
Q2
CMOS VLSI Design1: Circuits & Layout Slide 43
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Nonoverlapping ClocksNonoverlapping Clocks Nonoverlapping clocks can prevent races Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew W ill th i thi l f f d i We will use them in this class for safe design
– Industry manages skew more carefully instead 1
1
2
2
QMQD
11
1
22
2
2
1
CMOS VLSI Design1: Circuits & Layout Slide 44
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Gate LayoutGate Layout Layout can be very time consuming Layout can be very time consuming
– Design gates to fit together nicelyB ild lib f t d d ll– Build a library of standard cells
Standard cell design methodologyV d GND h ld b t ( t d d h i ht)– VDD and GND should abut (standard height) – upside down
– Adjacent gates should satisfy design rulesMOS b d MOS– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
CMOS VLSI Design1: Circuits & Layout Slide 45
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Example: InverterExample: Inverter
CMOS VLSI Design1: Circuits & Layout Slide 46
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Example: NAND3Example: NAND3 Horizontal N diffusion and p diffusion strips Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates M t l1 V il t t Metal1 VDD rail at top Metal1 GND rail at bottom 32 b 40 32 by 40
CMOS VLSI Design1: Circuits & Layout Slide 47
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Stick DiagramsStick Diagrams Stick diagrams help plan layout quickly Stick diagrams help plan layout quickly
– Need not be to scaleD ith l il d k– Draw with color pencils or dry-erase markers
CMOS VLSI Design1: Circuits & Layout Slide 48
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Wiring TracksWiring Tracks A wiring track is the space required for a wire A wiring track is the space required for a wire
– 4 width, 4 spacing from neighbor = 8 pitch T i t l i i t k Transistors also consume one wiring track
CMOS VLSI Design1: Circuits & Layout Slide 49
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Well spacingWell spacing Wells must surround transistors by 6 Wells must surround transistors by 6
– Implies 12 between opposite transistor flavorsL f i t k– Leaves room for one wire track
CMOS VLSI Design1: Circuits & Layout Slide 50
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Area EstimationArea Estimation Estimate area by counting wiring tracks Estimate area by counting wiring tracks
– Multiply by 8 to express in
4 wiring tracks X 8 lambda
CMOS VLSI Design1: Circuits & Layout Slide 51
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Example: O3AIExample: O3AI Sketch a stick diagram for O3AI and estimate area Sketch a stick diagram for O3AI and estimate area
– Y A B C D
CMOS VLSI Design1: Circuits & Layout Slide 52
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Example: O3AIExample: O3AI Sketch a stick diagram for O3AI and estimate area Sketch a stick diagram for O3AI and estimate area
– Y A B C D
CMOS VLSI Design1: Circuits & Layout Slide 53
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Example: O3AIExample: O3AI Sketch a stick diagram for O3AI and estimate area Sketch a stick diagram for O3AI and estimate area
– Y A B C D
CMOS VLSI Design1: Circuits & Layout Slide 54
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HomeworkHomework Sketch a stick diagram for a 4 input NOR gate Sketch a stick diagram for a 4-input NOR gate
CMOS VLSI Design1: Circuits & Layout Slide 55
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HomeworkHomework Sketch a stick diagram for a 4 input NOR gate Sketch a stick diagram for a 4-input NOR gate Euler path를사용하면수학적으로 topology 생성
VDDA
VDDB C D
YY
GND
CMOS VLSI Design1: Circuits & Layout Slide 56