lect18_seq2

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Advanced VLSI Design CMPE 640Sequential Logic Design

Smaller Static Flip-Flops

Positive feedback is not the only means to implement a memory function.

A capacitorcan act as a memory element as well.

In this case, aperiodic refreshis required (in the millisecond range) due to leakage (hence

the word dynamic).

Consider the following "cheaper" (1/2 transmission gate)positive level-sensitivestatic latch

as a step toward deriving a dynamic FF:

1

1

OutStatic as long as 1is kept low.

When 1is high,In

is

OutIn

sampled and stored oninternal capacitors.

A B

Logic 1 degraded byVt.

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Smaller Static Flip-Flops

A master-slave FF is created by cascading two of these latches and reversing the clocks.

The problem with this latch is that 1and 1might overlap, which may cause two types of

failures:

Node A can become undefined as it is driven by bothD andBwhen 1and 1 are both

high.

Dcan propagate through both the master and slave if both 1and 1are high simulta-

neously for a long enough period (race condition).

1

1QM

D

1

1Q

AN1

N2

AB

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Single Phase Clock Skew/Slew

Clock skew causes conflicts and transparency.

Clock slew (slow rise and fall times) can also cause transparency:

Clock skew is a dominant problem in current high performance designs.

1

1

Both n transistors are "on".

1

1

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Pseudo-Static Two-Phase Flip-Flops

The fix is to use two non-overlapping clocks 1and 2:

A large t-12allows proper operation even in the presence of clock skew.

Note that nodeAfloats (dynamic) during the time period t-12but is driven during t-1and

t-2(static).

Hence, the namepseudostatic.

2

1QM

D

1

2Q

AA

1

2

t12t1

t2

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CMOS Dynamic Two-Phase Flip-Flops

This version is simplier (6 trans) and is often used in pipelined datapaths for microproces-sors and signal processors.

Disadv: 2non-overlapping clocksrequired (4 if transmission gates are used).

These implementations MUST be simulated at all process corners (under worst-case condi-

tions).

1

D

2

Q

Degraded 1 values may increase static current if below Vtp.

1

D

2

Q

VDDVDDp leakers

p leakersprovide fully restored logic levels.

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Two-Phase Clocking

Clock skew/slew:

1logic

large delay

1

2logic

small delay

2

Both n-transistors

Nonoverlapping clocks: become transparent!

Overlap!

Slew

Skew

1

2

Excessive loadscan increaserise/fall times.

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C2MOS Register

C2MOS: A clever method which is insensitiveto clock skew:

VDD

D

1

1

VDD

Q

1

VDD

1

GND

D Q

Note: Dual phase version is identicalexcept 2and 2are used to drivethe n/p-trans in the right inverter.

1

1

1

1

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C2MOS Register

C2MOS is insensitiveto overlap as long as the rise and fall times of the clk edges (clock

slew) are sufficiently small:

VDD

D1

1

VDD

Q

1

1

VDD

D

VDD

Q

VDD

D

VDD

Q

1-1 overlap 0-0 overlap

1 1

No race is possible!

In order for Dto race to theQ, a pull-upfollowed by apull-down mustbe enabled.

0 0

Acts as a negative edge-triggeredmaster-slave D FF.

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C2MOS Register

Racesare just not possible since the overlaps activate either the pull-up or the pull-down

networks but never both simultaneously.

The inverters force 0-1 and 1-0 propagation modes only.

However, if the rise and fall times of the clock are slow, there exists a time slot in which

bothn- and p-transistors are conducting simultaneously.

Correct operation requires the clock rise/fall times be smaller than about5 timesthe propa-

gation delay through the FF.

This is not hard to meet in practical designs, making C2MOS especially attractive in high

speed designs where avoiding clock overlap is hard.

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Pipelining

The minimum allowed clock for the pipelined system is:

Implementation using pass-transistor based D latches

As indicated, races can occur when and overlap.

Reg

Reg

a

babs log

Reg

out+

Reg

Reg

a

babs log

Reg

out+

Tmin tq max td,add td,abs td,log, ,( ) ts+ +=

In

C1 C2F G

C3

Out

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Pipelining

C2MOS latches can be used instead, but ONLY if the logic functions, F, implemented

between the latches are non-inverting.

If Fis inverting, and and overlap (1-1), then C2is discharged as shown above.

NORA-CMOS(NO-RAce) targets the implementation of fast pipelined datapaths by com-

bining C2MOS with np-CMOS dynamic function blocks.

In

C1 C2F G

Out

C3

1

0 1

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Pipelining with NORA-CMOS

PDN

In1In

2In3

PUN

Out

-module

Combo Latch

PDN

In1

In2In3

Out

-module

In4

In4

Evaluating

when is 1.

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Pipelining with NORA-CMOS

The NORA datapath consists of a chain of alternating and modules.

While one class of modules isprechargingwith its output latch in hold mode, the other

class is evaluating.

Note that dynamic and static logic can be mixed freely.

Rule: # of static inversions between C2MOS latches should be even. When dynamicgates

are present, the # of static inverters between a latch and dynamic gate and between the last

dynamic gate and latch should be even.

PDNIn1

In2

Out

0-0 clock overlap This implementationis problematic

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True Single-Phase Clocked Logic (TSPCL)

The NORA design style can be simplified so that a single clockis sufficient.

For the doubled n-C2MOS latch, when = 1, the latch is in the transparentevaluatemode

and corresponds to 2 cascaded inverters (non-inverting).

When= 0, both inverters are disabled (holdmode) -- only the pull-up network is still

active.

The dual stage approach completely eliminates races.

This style combines the advantages of C2MOS and eliminates all constraints.

Out

Doubled n-C2MOS latch

Doubled p-C2MOS latch

Out

In In

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True Single-Phase Clocked Logic (TSPCL)

The one disadvantage is that 6 transistors (vs. 4) are needed per latch.

A further simplification is to control onlythe first inverter with the clock.

In

PUN

PDN

Includelogic inthe latch

Static

logic Out

OutIn

-latch -latch

OutIn

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True Single-Phase Clock Logic (TSPC)

This reduces the number of transistors and the clock load is reduced in half.

Problem: not all node voltages experience the full logic swing.

NodeA(for Vin= 0V) maximally reaches VDD- VTn.

This results in a reduced drive for the output NMOS transistor and a loss in perfor-

mance.

This design methodology is called True Single-Phase Clock Logic(TSPC).

It allows for the implementation of dynamic sequential circuits with a single clock.

OutIn

-latch

A

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True Single-Phase Clock Logic (TSPC)

Edge-triggered FFs:

Split-outputversion reduces clock load in half, while performing well.

D

Positive edge-triggered

Q

D

Negative edge-triggered

Q

D

Positive edge-triggered

Q

Doublelatch versions

Split-output latch

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Monostable Sequential Circuits

A circuit that generates a pulse of apredetermined widthevery time the circuit is triggered

by a pulse or transition event (one-shot).

The circuit has only one stable state-- the quiescent state.

The trigger causes the circuit to go temporarily into a quasi-stablestate.

It returns to its quiescent state after a time period determined by the circuit parameters.

Useful for address transition detection(ATD)to generate timing in static memories for

subsequent operations.

We've seen this version in edge-triggered FFs.

DELAYtd Out

In

td

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Monostable Sequential Circuits

A second class uses feedback combined with anRC timing networkto generate a pulse of

fixed width.

Initially,Inand Outare low and thereforeAis high.Bis high via resistor R.

PulsingInhigh causesAto go low, pulling nodeBwith it.

NodeBgets pulled high again with time constant RC.

Outgoes low whenBreaches VM, which causesA to go high again (noteInhas

already gone low again).

The width (t2- t1) is determined by the time-constant RC and VM.

Unfortunately, VMis relatively sensitive to process variations.

C

A OutIn

B

In

B

t1 t2

Out

R

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Astable Sequential Circuits

A circuit with no stable states.

The output oscillates back and forth between two quasi-stablestates with a period

determined by circuit parameters.

The main application of such a circuit is on-chip clock generation.We already looked at the ring oscillatoras an example.

The period T of the oscillation is:

where tpis the propagation delay of the composing gates.

v0 v1 v2 v3 v4

Ring oscillator

T 2 tp N= where N is the # of inverters in the chain.

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By tapping the ring oscillator at different stages, a wide range of clock signals with differ-

ent duty-cycles and phases can be derived.

It is often desirable to tune the frequency of oscillation.

An example is a Voltage-controlled Oscillator(VCO), whose frequency is proportional tothe value of a control voltage.

0 1 2 N-1

Out

Iref

M5M3

M1 Iref

M2

M4M6

In

Vctrl

Currentstarvedinverters

Current sources

Controls value of Iref

Lowering the value of Vctrlreduces the discharge currentand hence tpHL.

Polaritycorrectinginverter

Sharpensrise and

fall times

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Charging current is controlled via M5.

Irefis translated into a charging current through the current mirrorM6- M4.

Here, M6acts as a diodeand sets a bias voltage VGS6, that is controlled by Iref.

With VGS4= VGS6and both devices operating insaturation, IDS4= IDS6= Iref.

Since both M3and M5operate in saturation, a quadratic relation exists between Vctrl and

Iref(and tp).

This allows the frequency of the VCO to be controlled over a large range.

A Schmitt trigger is used tosharpenthe weakened rise and fall times of the current-staredinverter.

Note that transistors M5and M6 can be shared over all inverters in the chain.

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