lect07_mos2

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Advanced VLSI Design CMPE 640MOS Transistor Details

Dynamic Behavior

MOS Structure Capacitances:

The gate of a MOS transistor is isolated from the channel by the gate oxide where:

For the I-V equations, it is useful to have Coxas largeas possible, by keeping the

oxide very thin.

This capacitance is called gate capacitance and is given by:

This gate capacitance can be decomposed into several parts:

One part contributes to the channel charge.

A second part is due to the topological structure of the transistor.

Let's consider the latter first.

Coxox

tox-------=

Cg CoxWL=

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Dynamic Behavior

MOS Structure Capacitances, Overlap:

Lateral diffusion: source and drain diffusion extend under the oxide by an amount xd.

The effective channel length (Leff) is less than the drawn lengthL by 2*xd.

This also gives rise to a linear, fixed capacitance called overlap capacitance.

Since xdis technology dependent, it is usually combined with Cox.

poly

drainsource xdxd

L

n+n+W

Poly

n+ n+Leff

tox

CgsO CgdO CoxxdW COW= = =

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Dynamic Behavior

Channel Charge

The gate-to-channel capacitance is composed of three components, Cgs, Cgdand Cgb.

Each of these is non-linear and dependent on the region of operation.

Estimates or average values are often used:

Triode: Cgb~=0 since the inversion region shields the bulk electrode from the gate.

Saturation: Cgband Cgdare ~= 0 since the channel is pinched off.

Operation Region Cgb Cgs CgdCutoff CoxWLeff 0 0

Triode 0 CoxWLeff/2 CoxWLeff/2

Saturation 0 (2/3)CoxWLeff 0

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Dynamic Behavior

Junction or Diffusion CapacitancesThis component is caused by the reverse-biased source-bulk and drain-bulkpn-junc-

tions.

We determined that this capacitance is non-linearand decreasesas reverse-bias is

increased.

Bottom-plate junction:

Depletion region capacitance is:

with a grading coefficient of m = 0.5 (for an abrupt junction)

Bottom

sidewall

W

LS

xj

channel

ND

sidewall

channel-stop

implant NA+

Cbo ttom CjWLS=

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Dynamic Behavior

MOS Structure Capacitances, Junction or Diffusion:Side-wall junction

Formed by the source region with doping NDand the p+channel-stop implant with

doping NA+.

Since the channel-stop doping is usually higher than the substrate, this results in a

higher unit capacitance:

with a grading coefficient of m = 1/3.

Note that the channel side is not included in the calculation.

xj is usually technology dependent and combined with C'jswas Cjsw.

Total junction(small-signal) capacitance is:

As we've done before, we linearize these and use average cap.

Csw Cjswxj W 2 LS+( )=

Cdif f Cbot tom Csw+ Cj AREA Cjsw PERIMETER+= =

Cdi ff CjLSW= Cjsw 2LS W+( )+

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Dynamic Behavior

Capacitive Device Model

The previous model can be summarized as:

The dynamic performance of digital circuits is directly proportional to these capaci-

tances.

G

B

DS

CGS CGD

CDB

CSB

CGB

CGS= Cgs+ CgsOCGD= Cgd+ CgdOCGB= CgbC

SB= C

SdiffCDB= CDdiff

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Dynamic Behavior

Example:Given:

tox 6nm=

L 0.24um=

W 0.36um=LD LS 0.625um= =

Cj0 2 103F m

2=

Cjsw0

2.75 1010

F m=

Determine the zero-bias value of all relevant capacitances.

Gate capacitance, Cox, per unit area is derived as:

ox tox

3.5 102fF um

6310 um

---------------------------------------------- 5.8fF um

2

= =

Total gate capacitance Cgis:

Cg WLCox 0.36um 0.24um 5.8fF um2

0.5fF= = =

Cox =

Overlap capacitance is:CGSO CGDO WCO 0.108fF= = =

Total gate capacitance is:

Cgtot Cg 2 CGSO+ 0.716fF= =

CO 3 1010

F m=

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Dynamic Behavior

Example (cont):

In this example, diffusion capacitance dominates gate capacitance (0.89 fF vs. 0.716

fF).

Note that this is the worst case condition. Increasing reverse bias reduces diffusion

capacitance (by about 50%).

Also note that side-wall dominates diffusion. Advanced processes use SiO2to isolate

devices (trench isolation) instead of NA+ implant.

Usually, diffusion is at most equal to gate, very often it is smaller.

Diffusion capacitance is the sum of bottom:

Cj0LDW 2fF um2

0.625um 0.36um 0.45fF= =

Plus side-wall (under zero-bias):

Cjsw0 2LD W+( ) 2.75110 2 0.625um 0.36um+( ) 0.44fF= =

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Source-Drain Resistance

Scaling causes junctions to be shallowerand contact openings to be smaller.This increases the parasitic resistance in series with the source and drain.

This resistance can be expressed as:

The series resistance degrades performance by decreasing drain current.

Silicidationused -- low-resistivity material such as titaniumor tungsten.

G

S D

RS RD

W

LD

Draincontact

Drain

Gate

VGS,eff

RS D,

LS D,

W

-----------R RC+=

RC Contact Resistance=

R Sheet resistance 2 100( )=

LS,D= length of source/drain region.

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Secondary Effects

Long-channel devices

One-dimensional model discussed thus far.

Assumed:

All current flows on the surface of the silicon.

Electric fields are oriented along that plane.

Appropriate for manual analysis.

Short-channel deviceIdeal model does not hold well when device dimensions reach sub-micron range.

The length of the channel becomes comparable to other device parameters such as

the depth of the drain and source junctions.

Two-dimensional model is needed.

Computer simulation required.

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Secondary Effects

Threshold variationsIdeal model assumed threshold voltagewas only a function of technology parameters

and applied body bias, VSB.

With smaller dimensions, the VT0becomes a function of L, W and VDS.

For example, the expression for VT0assumed that all depletion charge beneath the

gate originates from the MOS field effects.

We ignored the source and reverse-biased drain depletion regions.

These depletion regions extend under the gate, which in turn reducesthe threshold

voltage necessary to cause strong inversion.

Long-channel threshold

L

VT Short-channel threshold

VDS

VT

Drain-induced barrier loweringfor small L.

Threshold as a functionof length (for low VDS)

Short-channel threshold

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Secondary Effects

Threshold variationsAlso, threshold decreaseswith increasingVDS.

This effect is called drain-induced barrier lowering (DIBL).

For high values of VDS, the source and drain depletion regions can short together

(punch-through).

DIBLis a more serious issue than the variation in VT0as a function of length (since

most transistors are minimum length transistors).

Particularly for DRAMs.

Leakage current of a cell (e.g. subthreshold current of the access transistor) is a

function of voltage on the data line.

word-line

data line

Cx Cbit

Shared with many othercells

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Secondary Effects

Threshold variations

Threshold drift also occurs for short-channel devices over time as a result of hot-car-

rier effects.

In the past, constant voltage scalingwas used which increased the electric field

strength and velocity of the electrons.

The electrons can leave the silicon and tunnel into the gate oxide, given enough

energy.

Trapped electrons in the oxide increasethe threshold of NMOS devices and decrease

the threshold of PMOS devices.

Field strengths of 104V/cm are easily reached in submicron devices.

This problem causes long-term reliability problems.

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Secondary Effects

Variations in the I-V characteristics:

The current-voltage relations deviate significantly from the ideal expressions.

The ideal expressions are:

The most important reasons for this difference are:

Velocity saturation effectsMobility degradation effects

ID12---n

ox

tox-------

WL----- VGS VT( )

2 1 VDS+( )=

ID nox

tox

------- W

L

----- VGS VT( )VDSVDS

2

2

----------=

(Saturation)

(Linear)

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Secondary Effects

Velocity Saturation

We modeled carrier mobility, n, as a constant.

We stated carrier velocity is proportional to the electric field, independent of its

value.

This holds up to a critical value of electric field, c, after which the velocity of the car-

riers tends to saturate:

sat= 107

Constant velocity

n

(cm/sec)

Ec= 1.5 E(V/m)

Constant mobility (slope = )

Velocity saturation

Electrons in p-type silicon:

Ec 1 5V m=

Holes in n-type silicon:

sat 107cm sec=

Therefore, only about 2 volts

with a channel length of 0.25mm.

are needed for NMOS devices

Ec 10V m>

sat 107cm sec= (same)

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Secondary Effects

Velocity Saturation

Revised linear equation:

For long-channel devices (L is large) or small values of VDS, approaches 1, and the

equation simplifies to the traditional equation.

For short channel devices, is less than 1 and current is reduced.

ID

nCox

1VDS

cL----------

+-------------------------

W

L-----

VGS VT( )VDS

VDS2

2----------

=

ID nCox( )W

L-----

VGS VT( )VDS

VDS2

2---------- VDS( )=

V( ) 1

1V

cL---------

+------------------------=with

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Secondary Effects

Velocity Saturation

Revised saturation equation:

Further increases in VDSdoes NOT yield more current and the transistor current satu-

rates at IDSAT.

For VDSAT< VGS- VT(for short channel devices), the device enters saturation before

VDSreaches VGS-VT.

Saturation region is extended.

IDSAT satCoxW VGS VT VDSAT ( )=

ID VDSAT( )nCoxW

L-----

VGS VT( )VDSATVDSAT

2

2---------------=

VDSAT VGS VT( ) VGS VT( )=with

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Secondary Effects

Velocity Saturation

This yields a linearrelationship between the saturation current and the gate-source voltage.

However, reducing the operating voltage does not have such a significant effect in submi-

cron devices as it would for long-channel devices.

Long-channel devices

IDS(mA)

VGS= 1V

VGS= 2V

VGS= 3V

VGS= 4V

VGS= 5V

1.0 2.0 3.0 4.0 5.0

1.0

1.5

Linear

0.5IDS(mA)

VDS(V)

VGS= 1VV

GS

= 2V

VDS= VGS- VT

VGS= 3V

VGS= 4V

VGS= 5V

1.0 2.0 3.0 4.0 5.0

1

2

Square

Short-channel devicesVDS(V)

Linear relationship with VGSExtended saturation region (to be discussed).

W 100m=L 20m=W 4.6m=L 1.2m=

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Secondary Effects

Mobility Degradation

Mobility degradationis a second effect of reducing channel-length.

This reduces transistor current even at "normal" electric field levels.

The reduction in the electron mobilityis caused by the verticalcomponent of the elec-tric field (which was ignored before).

n

(cm

2/Vsec)

Et(V/m)

Mobility Degradation

n0700

250

100

Etis the transversal

electrical field.

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Secondary Effects

Subthreshold Conduction

The transistor is partially conducting for voltages below the threshold voltage.

The region is referred to as weak-inversion.

Right logarithmic plot shows current decays in an exponential fashion.

Sub-thresholdoperation

0.5 1.0 1.50

0.25

IDm

A

(

)

VGS(V)

VDSis held constant

at 5V.

0.5 1.0 1.5VGS(V)

VT

0.00.010-12

10-10

10-8

10-6

10-410

-2

Linear

Subthreshold exponentialregion

ID

A(

)

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Secondary Effects


In the absense of a conducting channel, the n+ (source) - p (bulk) - n+(drain) terminals

actually form aparasitic bipolar transistor.

The rate of decrease of current is described by:

Ideally, IDshould fall to zero very quickly after VGSfalls below VT.

The inverserate of decline of the current w.r.t. VGSbelow VTis a quality measure of a

device, and can be quantified by the slope factorS.

S measures by how much VGShas to be reduced for the drain current to drop by a

factor of 10.

ID ISe

VGS

nkT q----------------

1 e

VDS

kT q------------------

1 VDS+( )=where ISand n areempirical parameters

(n ~1.5)

S n kT

q------

10( )ln= mV/decade

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Secondary Effects


For an ideal transistor, with the sharpest possible roll off, n= 1 and (kT/q)ln(10)evalu-

ates to 60 mV/decade at room temperature.

Therefore, subthreshold current drops by a factor of 10 for a reduction in VGSof 60

mV.

Unfortunately, nis greater than 1 for actual devices and current falls at a reduced rate

(90 mV/decade for n= 1.5).

The current roll-off isfurther decreasedby a rise in operating temperature (most chips

operate at a temperature considerably above room temp).

Minimizing these leakages is particularly important in dynamiccircuits, which store

logic values as charge on a capacitor.

The value of nis affected by different process technologies, e.g., SOI.

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SPICE Models

The complexity of the behavior of the short-channel MOS transistor has resulted in a vari-

ety of models of different accuracy and computing efficiency.

The LEVEL parameter in the model statement selects the model:

LEVEL 1:Implements the Shichman-Hodgesmodel, which is based on the square law long-chan-

nel expressions.

Best used to verify a manual analysis.

LEVEL 2:

Geometry-based model, which uses detailed device physicsto define its equations.

It handles effects such as velocity saturation, mobility degradationandDIBLbut is too

complex and inaccurate to handle all 3D effects.

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SPICE Models

LEVEL 3:

A semi-empirical model (depends on measured device data to define its parameters).

Works well for channel lengths down to 1 mm.

LEVEL 4(LEVEL 49):Berkeley Short-Channel IGFET Model (BSIM).

Provides an analytically simple model that is based on a small number of parameters

extracted from experimental data.

It is accurate as well as simple and is the most popular model.

LEVEL 5 - n:

There are many other models supplied by SPICE vendors and semiconductor manu-

facturers.

Some of the parameters on the following slides are redundant.

For example, PHIcan be computed from process model parameters.

User-defined values always override those that can be computed.

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SPICE Parameters LEVELs 1-3

Parameter Name Symbol SPICE name Units Default ValueTransverse Field Exponent

(mobility)UTRA - 0

Source Resistance RS RS 0

Drain Resistance RD RD 0

Sheet Resistance (Source/Drain) R/sq RSH /sq 0Zero-Bias Bulk Junction Cap Cj0 CJ F/m2 0

Bulk Junction Grading Coeff. m MJ - 0.5Zero-Bias Side-Wall Junction Cap. Cjsw0 CJSW F/m 0

Side-Wall Grading Coeff. msw MJSW - 0.3

Gate-Bulk Overlap Cap. CgbO CGBO F/m 0Gate-Source Overlap Cap. CgsO CGSO F/m 0

Gate-Drain Overlap Cap. CgdO CGDO F/m 0

Bulk Junction Leakage Current IS IS A 0

Bulk Junction Leakage CurrentDensity

JS

JSA/m

2 1E-8

Bulk Junction Potential 0 PB V 0.8

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SPICE Individual Transistor Parameters

The following parameters are specified on the device line, not within the transistor.

Note that zero is assumed for many of these if left unspecified !

NRSand NRDmultiply the sheet resistance RSHspecified in the model to give the series

source and drain resistance.

Parameter Name Symbol SPICE name Units Default Value

Drawn Length L L m -Effective Width W W m -

Source Area AREA AS m2 0

Drain Area AREA AD m2 0Source Perimeter PERIM PS m 0Drain Perimeter PERIM PD m 0

Squares of Source Diffusion NRS - 1Squares of Drain Diffusion NRD - 1

M1 2 1 0 0 NMOS W=1. 8U L=1. 2U NRS=0. 333 NRD=0. 333

+ AD=6. 5P PD=9. 0U AS=6. 5P PS=9. 0U

M2 2 1 5 5 PMOS W=5. 4U L=1. 2U NRS=0. 111 NRD=0. 111

+ AD=16. 2P PD=11. 4U AS=16. 2P PS=11. 4U

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