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EECS 151/251ASpring2020 DigitalDesignandIntegratedCircuitsInstructors:Wawrzynek

Lecture 9: CMOS

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From the Bottom Up❑ IC processing ❑ MOS transistors ❑ CMOS Circuits

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Overview of Physical Implementations

❑ Integrated Circuits (ICs)▪ Combinational logic circuits, memory elements, analog

interfaces. ❑ Printed Circuits (PC) boards

▪ substrate for ICs and interconnection, distribution of CLK, Vdd, and GND signals, heat dissipation.

❑ Power Supplies▪ Converts line AC voltage or battery DC voltage to regulated

DC low voltage levels. ❑ Chassis (rack, card case, ...)

▪ holds boards, power supply, fans, provides physical interface to user or other systems.

❑ Connectors and Cables.❑ Peripheral and I/O components.

The stuff out of which we make systems.

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Printed Circuit Boards❑ fiberglass or ceramic ❑ 1-25 conductive layers ❑ ~1-20in on a side ❑ IC packages are soldered down.

Multichip Modules (MCMs)

• Multiple chips directly connected to a substrate. (silicon, ceramic, plastic, fiberglass) without chip packages.

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Integrated Circuits❑ Primarily Crystalline Silicon ❑ 1mm - 25mm on a side ❑ 100 - 20B transistors ❑ (25 - 250M “logic gates”) ❑ 3 - 10 conductive layers ❑ 2019 state-of-the-art feature size

7nm = 0.007 x 10-6 m ❑ “CMOS” most common -

complementary metal oxide semiconductor

• Package provides: – spreading of chip-level signal

paths to board-level – heat dissipation.

• Ceramic or plastic with gold wires.

Chip in Package

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UC Regents Fall 2013 © UCBCS 250 L1: Fab/Design Interface

Chip Fabrication

Silicon “ingots” are grown from a “perfect” crystal seed in a melt, and then purified to “nine nines”.

Ingots sliced into 450μm thick wafers, using a diamond saw.

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9

CMOS Transistors

Top View

❑ MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

The gate acts like a capacitor. A high voltage on the gate attracts charge into the channel. If a voltage exists between the source and drain a current will flow. In its simplest approximation, the device acts like a switch.

Cross-section View

An n-channel MOS transistor (planar)

p-

n+

Vd = 1V

n+

Vs = 0V Polysilicon gate, dielectric, and

substrate form a capacitor.

nFet is off (I is “leakage”)

dielectric

Vg = 0V

I ≈ nA

----------

p-

n+

Vd = 1V

n+

Vs = 0Vdielectric

Vg = 1V+++++++++----------

Vg = 1V, small region near the

surface turns from p-type to n-type.

nFet is on.

I ≈ μA

Mask set for an n-Fet (circa 1986)

p-

n+

Vd = 1V

n+

Vs = 0Vdielectric

Vg = 0V

I ≈ nA #1: n+ diffusion

Top-down view:

Masks

#3: diff contact#2: poly (gate)

#4: metal

Layers to do p-Fet not shown. Modern processes have 6 to 10 metal layers (or more) (in 1986: 2).

“Design rules” for masks, 1986 ...

#1: n+ diffusion #3: diff contact#2: poly (gate) #4: metal

Poly overhang. So that if

masks are misaligned, we still get

channel.

Minimum gate length. So that the source and drain depletion regions

do not meet!

length

Metal rules: Contact

separation from channel, one fixed

contact size, overlap rules with

metal, etc ...

How a fab uses a mask set to make an IC

p-

n+

Vd = 1V

n+

Vs = 0Vdielectric

Vg = 1V

#1: n+ diffusionTop-down view: Masks

#3: diff contact#2: poly (gate)

#4: metal

Vg

Vd

Vs

Ids

I ≈ μA

Start with an un-doped wafer ...

Steps

p-

#1: dope wafer p-

#5: place positive poly mask and expose with UV.

UV hardens exposed resist. A wafer wash leaves only hard resist.

#2: grow gate oxide

oxide

#3: deposit polysilicon

#4: spin on photoresist

Wet etch to remove unmasked ...

p-

oxide

HF acid etches through poly and oxide, but not hardened resist.

p-

oxide

After etch and resist removal

Use diffusion mask to implant n-type

p-

oxide

accelerated donor atoms

n+ n+Notice how donor atoms are blocked by gate and do not

enter channel.

Thus, the channel is “self-aligned”, precise mask

alignment is not needed!

UC Regents Fall 2013 © UCBCS 250 L1: Fab/Design Interface

Metallization completes device

p-

oxiden+ n+

Grow a thick oxide on top

of the wafer.

p-

oxiden+ n+

Mask and etch to make contact

holes

p-

oxiden+ n+

Put a layer of metal on chip.

Be sure to fill in the holes!

Final product ...

Top-down view:

p-

oxiden+ n+

Vd Vs “The planar process”

Jean Hoerni, Fairchild

Semiconductor 1958

Lithography

‣ Current state-of-the-art photolithography tools use deep ultraviolet (DUV) light with wavelengths of 248 and 193 nm, which allow minimum feature sizes below 50 nm. Moving to extreme ultraviolet (EUV) with wavelength of 13.5nm.

desired (drawn)

modified mask

exposure

‣ Optical proximity correction (OPC) is an enhancement technique commonly used to compensate for image errors due to diffraction or process effects.

Latest Modern Process

Transistor channel is a raised fin.Gate controls channel from sides and top.

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CMOS Transistors – State-of-the-Art

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State of the art‣ 7nm

‣ 5nm

‣ 3.5nm

* From Wikipedia

As of September 2018, mass production of 7 nm devices has begun. The first mainstream 7 nm mobile processor intended for mass market use, the Apple A12 Bionic, was released at their September 2018 event. Although Huawei announced its own 7 nm processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips are manufactured by TSMC. AMD is currently working on their "Rome" workstation processors, which are based on the 7 nanometer node and feature up to 64 cores.

The 5 nm node was once assumed by some experts to be the end of Moore's law.

Transistors smaller than 7 nm will experience quantum tunnelling through the gate oxide layer. Due to the costs involved in development, 5 nm is predicted to take longer to reach market than the two years estimated by Moore's law. Beyond 7 nm, it was initially claimed that major technological advances would have to be made to produce chips at this small scale. In particular, it is believed that 5 nm may usher in the successor to the FinFET, such as a gate-all-around architecture.Although Intel has not yet revealed any specific plans to manufacturers or retailers, their 2009 roadmap projected an end-user release by approximately 2020. In early 2017, Samsung announced production of a 4 nm node by 2020 as part of its revised roadmap. On January 26th 2018, TSMC announced production of a 5 nm node by 2020 on its new fab 18. In October 2018, TSMC disclosed plans to start risk production of 5 nm devices in April 2019.

3.5 nm is a name for the first node beyond 5 nm. In 2018, IMEC and Cadence had taped out 3 nm test chips.

Also, Samsung announced that they plan to use Gate-All-Around technology to produce 3 nm FETs in 2021.

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CMOS Transistors

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Transistor Strength and Symmetry

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2. MOS transistors are symmetrical devices (Source and drain are interchangeable). But usually designed to be used in one direction.

Source is the node w/ the lowest voltage for (N-FET), in general the source node is connected to power rail.

1. Transistor “strength” proportional to W/L. In digital circuits, L is almost always minimal allowed by process.

Circuit Layout Examples‣ 2-input NAND

from Ji Li

NAND gate layout from Lecture 3: CMOS Technology and Logic Gates. (Image by Professors Arvind and Asanovic.)

Finfet layout

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MOS Transistor as a Resistive Switch

|VGS|

MOS Transistor

|VGS| ≥ |VT|

S D

Ron

A Switch!

S D

G

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Let’s look beneath the abstraction: origins of VT and Ron

MOSFET Threshold Voltage

I dsVs

Vd

V g

0.25 ≈ Vt

Ioff = 0 ???

Transistor “turns on” when Vgs is > Vt.

V gs

I ds

0.7 = Vdd

1.2 mA = IonVds = Vdd

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Transistor “resistance”❑ Actually, nonlinear I/V characteristic:

❑ But, linearizing makes all delay and power calculations simple (usually just 1st order ODEs):

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VDS

IDS

S

D

G IDS VDS

VGS

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ON/OFF Switch Model of MOS Transistor

|VGS|

S D

G

|VGS| < |VT|

Ron

S D S D

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|VGS| ≥ |VT|

Plot on a “Log” Scale to See “Off” Current

I dsVs

Vd

V g I ds

Ioff ≈ 10 nA

Process engineers can: increase Ion by lowering Vt - but that raises Ioff decrease Ioff by raising Vt - but that lowers Ion.

0.25 ≈ Vt

1.2 mA = Ion

0.7 = VddV gs

Latest Modern Process

Vg

s

IdsIntel 22nm Process Transistor channel is a raised fin.

Gate controls channel from sides and top.

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A More Realistic Switch

|VGS|

S D

G

|VGS| < |VT| |VGS| > |VT|

Ron

S DRoff

S D

Transistors in the sub 100 nm age

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A Logic Perspective

VGS > 0

S D

GNMOS Transistor

Y=Z if X=1

Y ZRonX

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A Complementary Switch

VGS < 0

S D

GPMOS Transistor

Y=Z if X=0

Y ZRonX

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Source is the node w/ the highest voltage!

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The CMOS Inverter: A First Glance

Vin VoutCL

VDD

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s

s

dd

g

g

Represents the sum of all the capacitance at the output of the inverter and everything to which it connects: (drains, interconnections gate capacitance of next gate(s))

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The Switch InverterFirst-Order DC Analysis*

VOL = 0 VOH = VDD

VDD VDD

Vin = VDD Vin = 0

VoutVout

Rn

Rp

36*First-order means we will ignore Capacitance.

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Switch logic

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Static Logic Gate▪ At every point in time (except during the switching transients) each

gate output is connected to either VDD or VGND via a low resistive path.

▪ The output of the gate assumes at all times the value of the Boolean function implemented by the circuit (ignoring, once again, the transient effects during switching periods).

Example: CMOS Inverter

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Vin V out

CL

VDD

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Building logic from switches (NMOS)

Y = X if A OR BOR

Y = X if A AND B

AND

(output undefined if condition not true)

X Y

Parallel

Series A B

X Y

A

B

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Logic using inverting switches (PMOS)

A B

X YSeries

Parallel X Y

A

B

NOR

NAND

Y = X if A AND B = A + B

Y = X if A OR B = AB

(output undefined if condition not true)

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Example Gate: NAND

❑ PDN: G = AB ⇒ Conduction to GND ❑ PUN: F = A + B = AB ⇒ Conduction to VDD

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Static Complementary CMOSVDD

F(In1,In2,…InN)

In1In2InN

In1In2InN

PUN and PDN are dual logic networks: series connections in the PUN are parallel connections in the PDN parallel connections in the PUN are series connection sin the PDN

PUN and PDN functions are complements: guarantees they are mutually exclusive, under all input values, one or the other is conductive, but never both!

……

Inverting switches

Non-Inverting switches

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Pull-up Network

Pull-down Network

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Example Gate: NOR

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Complex CMOS Gate

DA

B C

D

AB

C

OUT = D + A • (B + C) OUT = D • A + B • C

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OUT

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Graph Models for Duals

45http://people.ee.duke.edu/~krish/teaching/Lectures/CMOScircuits_2011.pdf

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Non-inverting logic

VDD

F(In1,In2,…InN)

In1In2InN

In1In2InN

PUN

PDN

PUN and PDN are dual logic networks PUN and PDN functions are complementary

……

Inverting switches

Non-Inverting switchesWhy is this a bad idea?

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Switch Limitations

0 → VDD - VTnCL

VDD

VDD

VDD → |VTp|CL

S

D

VGS

S

D

VGS

Bad 1

Bad 0

VDD

0 → VDDCL

S

D

VDD → 0CLVDD

S

D

Good 1

Good 0

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Tough luck …

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“Static” CMOS gatesVDD

F(In1,In2,…InN)

In1In2InN

In1In2InN

……

Inverting switches (PMOS transistors)

Non-Inverting switches (NMOS transistors)

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Pull-up Network

Pull-down Network

❑ Static CMOS gates are always inverting

AND = NAND + INV

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Complimentary CMOS Properties

❑ Full rail-to-rail swing ❑ Besides leakage (due to Ioff), no static power

dissipation ❑ Direct path current during switching

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Transmission Gate❑ Transmission gates are the way to build ideal “switches” in CMOS. ❑ In general, both transistor types are needed:

❑ nFET to pass zeros. ❑ pFET to pass ones.

❑ The transmission gate is bi-directional (unlike logic gates).

❑ Does not directly connect to Vdd and GND, but can be combined with logic gates or buffers to simplify many logic structures.

A B

if en==1 then A connects to B

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Transmission-gate Multiplexor2-to-1 multiplexor: c = sa + s’b

s

s’b

a

c

Switches simplify the implementation:

Compare the cost to logic gate implementation.

c

s

a

b

Care must be taken to not string together many pass-transistor stages. Occasionally, need to “rebuffer” with static gate.

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4-to-1 Transmission-gate Mux❑ The series connection of pass-

transistors in each branch effectively forms the AND of s1 and s0 (or their complement).

❑ Compare cost to logic gate implementation

Any alternate solutions?

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Alternative 4-to-1 Multiplexor❑ This version has less

delay from in to out.

❑ In both versions, care must be taken to avoid turning on multiple paths simultaneously (shorting together the inputs).

decoder

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CMOS Implementation

transmission gate provide the isolation: usually designed this way

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Tri-state Buffers

“high impedance” (output disconnected)

Tri-state Buffer:

Inverting buffer Inverted enable

Variations:

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Tri-state Buffers

Tri-state buffers are used when multiple circuits all connect to a common node or wire. Only one circuit at a time is allowed to drive the bus. All others “disconnect” their outputs, but can “listen”.

Tri-state buffers enable “bidirectional” connections.

= 1

= 0

=> 0

=> 1

=0

=0

=1

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Tri-state Based MultiplexorTransistor Circuit for inverting-multiplexor:Multiplexor:

If s=1 then c=a else c=b

b

a

s out

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Latches and Flip-flopsPositive Level-sensitive latch:

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clk’

clk

clk

clk’

Latch Implementation:

Positive edge-triggered flip-flop

D Q A flip-flop “samples” right before the edge, and then “holds” value.

Spring 2003 EECS150 – Lec10-Timing Page 14

Delay in Flip-flops

• Setup time results from delay

through first latch.

• Clock to Q delay results from

delay through second latch.

D

clk

Q

setup time clock to Q delay

clk

clk’

clk

clk

clk’

clk’

clk

clk’

Sampling circuit

Spring 2003 EECS150 – Lec10-Timing Page 14

Delay in Flip-flops

• Setup time results from delay

through first latch.

• Clock to Q delay results from

delay through second latch.

D

clk

Q

setup time clock to Q delay

clk

clk’

clk

clk

clk’

clk’

clk

clk’

Holds value

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Sensing: When clock is low

D QA flip-flop “samples” right before the

edge, and then “holds” value.

Spring 2003 EECS150 – Lec10-Timing Page 14

Delay in Flip-flops

• Setup time results from delay

through first latch.

• Clock to Q delay results from

delay through second latch.

D

clk

Q

setup time clock to Q delay

clk

clk’

clk

clk

clk’

clk’

clk

clk’

Sampling circuit

Spring 2003 EECS150 – Lec10-Timing Page 14

Delay in Flip-flops

• Setup time results from delay

through first latch.

• Clock to Q delay results from

delay through second latch.

D

clk

Q

setup time clock to Q delay

clk

clk’

clk

clk

clk’

clk’

clk

clk’

Holds value

Spring 2003 EECS150 – Lec10-Timing Page 14

Delay in Flip-flops

• Setup time results from delay

through first latch.

• Clock to Q delay results from

delay through second latch.

D

clk

Q

setup time clock to Q delay

clk

clk’

clk

clk

clk’

clk’

clk

clk’

Spring 2003 EECS150 – Lec10-Timing Page 14

Delay in Flip-flops

• Setup time results from delay

through first latch.

• Clock to Q delay results from

delay through second latch.

D

clk

Q

setup time clock to Q delay

clk

clk’

clk

clk

clk’

clk’

clk

clk’

clk = 0 clk’ = 1

Will capture new value on posedge.

Outputs last value captured.

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Capture: When clock goes high

D QA flip-flop “samples” right before the

edge, and then “holds” value.

Spring 2003 EECS150 – Lec10-Timing Page 14

Delay in Flip-flops

• Setup time results from delay

through first latch.

• Clock to Q delay results from

delay through second latch.

D

clk

Q

setup time clock to Q delay

clk

clk’

clk

clk

clk’

clk’

clk

clk’

Sampling circuit

Spring 2003 EECS150 – Lec10-Timing Page 14

Delay in Flip-flops

• Setup time results from delay

through first latch.

• Clock to Q delay results from

delay through second latch.

D

clk

Q

setup time clock to Q delay

clk

clk’

clk

clk

clk’

clk’

clk

clk’

Holds value

Spring 2003 EECS150 – Lec10-Timing Page 14

Delay in Flip-flops

• Setup time results from delay

through first latch.

• Clock to Q delay results from

delay through second latch.

D

clk

Q

setup time clock to Q delay

clk

clk’

clk

clk

clk’

clk’

clk

clk’

Spring 2003 EECS150 – Lec10-Timing Page 14

Delay in Flip-flops

• Setup time results from delay

through first latch.

• Clock to Q delay results from

delay through second latch.

D

clk

Q

setup time clock to Q delay

clk

clk’

clk

clk

clk’

clk’

clk

clk’

clk = 1 clk’ = 0

Remembers value just captured.

Outputs value just captured.

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Tri-state-Inverter Latch

d q

clk

clk

❑ Commonly used in standard cell flip-flops. ❑ More transistors than pass-transistor

version, but more robust. ❑ Lays out well with modern layout rules.

Positive Level-sensitive latch: