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EE 577B: VLSI Design Projects ClassEE 577B: VLSI Design Projects Class

Lecture 4: Intro to VerilogLecture 4: Intro to Verilog

Dr. Jef Draper,Ming Hsieh Department o Electrical Engineering

University o Southern Caliornia

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06/15/16 EE 577B 2

Course AnnouncementsCourse Announcements

Homewor ! "ue now# $an % 5'm

(10 minute grace period, -10 points at 5:10 and every

10 minutes afterards!

Homewor % assigne" to"a(

"ue #e$ 6, 5pm

Course we) site

%ttp://&uscden&net

Emai' )/*entor if you %ave any pro$'ems

http://www.uscden.net/http://www.uscden.net/

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06/15/16 EE 577B +

Course AnnouncementsCourse AnnouncementsHomewor % 'oste" on we) site to"a(

"ue 5pm, #e$ 6et started ear'y to sta$i'ie your .eri'og environment

efer to tutoria's on course e$ site

#o''o instructions on e'ectronic su$missionEmai' )/*entor it% any uestions

*A: A"it(a Des+'an"e# am"es+'a,usc-e"u

.entor: Har'reet B+atia# +)+atia,usc-e"u

Last "a( to a""/"ro' wit+out 'enalt( is 0ri"a(#

0e)ruar( !

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EE577B 1ra"e 2*entati3eEE577B 1ra"e 2*entati3e

Homewor: % 6 %5 25 8or eac+ assignment

Project Part !: ! 6 !5Project Part %: !5 6 %

Project Part 9: %5

Project Part 4: !

Project Presentation: !

ote: Project will 'ro)a)l( re;uire teaming into %6'erson teams 2start consi"ering teammate c+oices

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*entati3e Semester Sc+e"ule*entati3e Semester Sc+e"ule

Assignment Assignment Date Due Date

H=! 2577A re3iew $an !> $an %&

H=% 2Verilog $an %& 0e) >

H=9 2.ore Verilog 0e) > 0e) %

H=4 2S(nt+esis 0e) % 0e) %7

P! 2Verilog 0e) %7 .ar !9

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06/15/16 EE 577B 606/15/16 EE 577B 6

Potential In8o 8or Career 0airPotential In8o 8or Career 0air

Sills an" tools (ou will use in t+is class

specification in .eri'og3ynopsys: "esign 4ompi'er (synt%esis!, rimetime

(static timing ana'ysis!

4adence: 4-3im (simu'ation!, #irst Encounter

(p'aceroute!, 4onforma' ('ogica' euiva'ence

c%ec8ing!

Project can"i"ates:ipe'ined processor, netor8-on-c%ip router,pipe'ined #9, pipe'ined mu'ti-media

etension unit, mu'ti-core processor, etc

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Lecture Plan 8or ne?t 8ew weesLecture Plan 8or ne?t 8ew wees

*o"a(@s lecture: Intro to Verilogeeded for remaining %omeor8 assignments

and first p%ase(s! of pro;ect

.ore Verilog conce'ts/sources

Semester Project Intro

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% !

.'r

P(

Be+a3ioral .o"eling E?am'le: 0S.Be+a3ioral .o"eling E?am'le: 0S.

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06/15/16 EE 577B 5

Be+a3ioral .o"eling E?am'le: 0S.Be+a3ioral .o"eling E?am'le: 0S.

State mac+ine gui"elines

"eve'op separate $'oc8s for:

3tate memory

et-state 'ogic

Futput 'ogica8e care of reset appropriate'y

9se parameters for state assignments

Be+a3ioral Co"ing E?am'le: 0S.Be+a3ioral Co"ing E?am'le: 0S.

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06/15/16 EE 577B 55

Be+a3ioral Co"ing E?am'le: 0S.Be+a3ioral Co"ing E?am'le: 0S.

mo"ule 0S. 2rst# cl# 8smin# 8smout

in'ut rst# cl# 8smin

out'ut 8smoutreg 8smout

'arameter SEE M !@)# SEE! M !@)!

reg state# ne?tstate

// state memor( )localwa(s ,2'ose"ge cl

i8 2rst

state M SEE

else

state M ne?tstate

// ne?t state logic )loc

alwa(s ,28smin

case 28smin

!@)!: ne?tstate M SEE!

!@): ne?tstate M SEE

"e8ault: ne?tstate M

state

en"case

// out'ut logic )loc

alwa(s ,2statecase 2state

SEE: 8smout M !@)

SEE!: 8smout M !@)!

"e8ault: 8smout M !@)?

en"case

SEE

8smout M

8smin M

SEE!

8smout M !

8smin M !8smin M

8smin M !

EE 577B Course esourcesEE 577B Course esources

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06/15/16 EE 577B 56

EE 577B Course esourcesEE 577B Course esources

Some ot+er Verilog resources

`uic8 reference and eamp'es from previous

semesters (courtesy of estor artanis!

%ttp://-scf&usc&edu/Dee577/cadtoo's&%tm'

Course Plan 8or ne?t 8ew weesCourse Plan 8or ne?t 8ew wees

http://www-scf.usc.edu/~ee577/cad_tools.htmlhttp://www-scf.usc.edu/~ee577/cad_tools.html

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Course Plan 8or ne?t 8ew weesCourse Plan 8or ne?t 8ew wees

Lectures

*ore .eri'og concepts#'oating-point arit%metic tutoria'

ro;ect description

Homewor % "ue 0e) >Homewor 9 2more Verilog conce'ts will )e

assigne" 0e) >

Ruic *ools DemoRuic *ools Demo

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Ruic *ools DemoRuic *ools Demo

*A A"it(a Des+'an"e will 'ro3i"e a ;uic

tools "emo 8or t+e remain"er o8 to"a(@s lecturetime