Lec31-LogicGateCMOS

8/10/2019 Lec31-LogicGateCMOS

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DIGITAL CIRCUITS AND

Electronic & Communication Engineering

Danang University of Technology


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Logic value 1

Undefined

Voltage

VDD

V1,min

- Positive/Negative logicsystem-V0,max: max. voltage level that

a logic circuit recognizes as low- V1,min: min. voltage level that alogic circuit recognizes as high

Voltage Levels

Logic value 0

V0,max

VSS (Gnd)

Logic values as voltage levels.

- Exact V0,max ,V1,min valuesdepend on used technology,normally 40% VDD and 60% VDD


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DrainSource

x = "low" x = "high"

(a) A simple switch controlled by the input x

Gate

- Most popular used transistoris MOSFET: NMOS & PMOS

- 4 electrical terminals. In logiccircuits the substrateterminal isconnected to Gn for NMOS

NMOS

NMOS transistor as a switch.

VDVS

(b) NMOS transistor

(c) Simplified symbol for an NMOS transistor

VG

Substrate (Body)

- No physical differencebetween sourceand drainterminals

- By convention, the sourceterminal is the node with lowervoltage for NMOS


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- Silicon is an electrical semiconductor.- A transistor is fabricated by creating areas in the siliconsubstrate that have an excess of either positive or negative

electrical charge.- The gate terminal is made of poly-silicon which ispreferable to metal as it can be fabricated with extremely

Remarks

.- The gate is electrically isolated from the rest of transistor bya layer of SiO2.- Transistors operation is governed by electrical fields caused

by voltages applied to its terminal


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SiO2

VS

0 V=

V G 0 V=

VD

NMOS off

NMOS transistor when turned off: back-to-back diodes representvery high resistance (1012 ohm) between drain & source

++++++ ++++ ++++++ +++ ++++++++++++ ++++++ ++++++

+++++++++ +++++++++

+++++++++++ +++++++++++

Drain (type n)Source (type n)

Substrate (type p)

(a) WhenVGS

= 0 V, the transistor is off

++++++

++++++++++++

++++++


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SiO2

VDD

VD

0 V=

VG 5 V=

VS

0 V=

NMOS on

++++++ ++++++

+++++++++ +++++++++++++++++++++ +++++++++++++++++

Channel (type n)

(b) WhenVGS= 5 V, the transistor is on

++ +++++++

NMOS transistor when turned on: If the gate-to-source

voltage VGS is greater than a certain minimum positive voltage,called VT (typically 0,2 VDD), then the switch is closed.


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-The positive voltage on the gate attracts free electronsexisting in the type-n source and drain terminals & otherareas of the transistor towards the gate. Because of SiO2

layer, electrons gather in region of the substrate betweensource & drain terminals, which results into channelconnecting source & drain.

Channel

- The size of channel is determined by length L & width W

+

+

(a) Small transistor

L

W1

L

W2

(b) Larger transistor


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Gate

x = "high" x = "low"

(a) A switch with the opposite behavior

Drain Source

- Most popular used transistoris MOSFET: NMOS & PMOS

- 4 electrical terminals. In logiccircuits the substrateterminal isconnected to to VDDfor PMOS

PMOS

PMOS transistor as a switch.

VG

VDVS

(b) PMOS transistor

(c) Simplified symbol for a PMOS transistor

Substrate (Body) - o p ys ca erencebetween sourceand drainterminals- By convention, the sourceterminal is the node with highervoltage for PMOS


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(a) NMOS transistor

VG

VD

VS= 0 V

Closed switchwhenVG = VDD

VD = 0 V

Open switchwhenVG = 0 V

VD

- When the NMOS transistor isturned on, its drain is pulleddown to Gnd

Operations

NMOS and PMOS transistors in logic circuits.

VS= VDD

VD

VG

Open switch

whenVG = VDD

VD

VDD

Closed switch

whenVG = 0 V

VD = VDD

VDD

(b) PMOS transistor

- When the PMOS transistor isturned on, its drain is pulled up

to to VDD


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Vx

Vf

R

+

-

5 V

Vx

Vf

VDD

R

- VX=0V, tr is turned off -->Vf=5V

- When VX=5V, tr is turnedon, its drain is pulled downto Gnd --> V =0V

NMOS NOT

A NOT gate built using NMOStechnology.

x f

(c) Graphical symbols

x f

(a) Circuit diagram (b) Simplified circuit diagram

- Exact Vf depends on R &tr., typically is 0.2V

- R is used to limit thecurrent during turning on oftr. (problem?)


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Vf

VDD

0

0

1

1

0

1

0

1

1

1

1

0

x1

x2

f

Vx2

Vx1

- Series connection of NMOS tocreate the logic AND function- V

X1= V

X2=5V, tr is turned off --

> Vf=5V- When VX=5V, trs are turnedon their drains are ulled down

NMOS NAND

NMOS realization of a NANDgate.

(a) Circuit


(b) Truth table

f f

x1

x2

x1

x2

to Gnd --> Vf will be closed to0V

- If only one of trs is turned off,then Vf will be pulled up to 5V- R is used to limit the currentduring turning on of tr.

(problem?)


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Vx1Vx2

Vf

VDD

0

0

1

1

0

1

0

1

1

0

0

0

x1

x2 f

- Parallel connection ofNMOS to create the logic

NOR function- Either VX1= 5V or VX2=5V,Vf will be closed to 0V

NMOS NOR

NMOS realization of a NORgate.

(a) Circuit


(b) Truth table

f f

x1

x2

x1

x2

- -- f be pulled up to 5V


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0 0 0

x1 x2 f

Vf

VDD

AVx1

V

VDD

- AND realization by following aNAND gate with an Inverter

NMOS AND

NMOS realization of an AND gate.

(a) Circuit


(b) Truth table

f f

0

11

1

01

0

01

x1

x2

x1

x2


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0

0

1

1

0

1

0

1

0

1

1

1

x1

x2 f

Vf

VDD

Vx2Vx1

VDD

- OR realization byfollowing a NOR gate withan Inverter

NMOS OR

NMOS realization of an OR gate.

(a) Circuit


(b) Truth table

f fx

1

x2

x1

x2


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Vf

VDD

- All mentioned structures can be

characterized by a block diagramwith PDN (pull-down network)

PDN Structure

Structure of an NMOS circuit.

Pull-down networkVx1

Vxn

(PDN)


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VDD

T1

Vx

Vf

VDD

R- When Vx= 0V, T1 is ON &T2 is OFF, Vf= 5V. Since T2

is OFF, no current flowsthrough trs.- When Vx= 5V, T2 is ON &

CMOS NOT

CMOS realization of a NOT gate.

(b) Truth table and transistor states

on

off

off

on

1

0

0

1

fx T1 T2

(a) Circuit

VfVx

T2

NMOS realization of NOT gate

,f= .

is OFF, no current flowsthrough trs.- KEY: no current flows in

CMOS Inverter


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VDD

T1

T2

2121 xxxxf +==Logic expression of NAND gate:Look at Truth Table, f=1 when eitherx1 orx2= 0, thus PUN must

be active in this case (pull up Vf to 1), and two PMOS transistors

must be connected in parallel.

The PDN must implement the complement off:

Since !f=1 when both x1 and x2 = 1, PDN must

have two NMOS trs. connected in series.

21xxf =

CMOS realization of a NAND gate.(a) Circuit

Vf


on

on

on

off

0

1

0

0

1

1

0

1

off

off

on

off

off

on

f

off

on

1

1

1

0

off

off

on

on

Vx1

Vx2

T 3

T 4

x1 x2 T 1 T 2 T 3 T 4


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VDD

Vx1

Vx2

T1

T 2

2121 xxxxf =+=

CMOS NOR

(a) Circuit

Vf


on

on

on

off

0

1

0

0

1

1

0

1

off

off

on

off

off

on

f

off

on

1

0

0

0

off

off

on

on

T 3 T 4

x1 x2 T 1 T 2 T 3 T 4

CMOS realization of a NOR gate.

21! xxf +=


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Vf

VDDVDD

CMOS AND

CMOS realization of an AND gate:connecting a NAND gate to an Inverter

Vx1

Vx2


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Consider the following function:

Since all variables appear in theircomplemented form, we can directly

derive the PUN: 1 PMOS tr. controlled by Vf

VDD

321 xxxf +=

Example 3.1

x1

n para e w a ser es com na on o

2 PMOS trs. controlled byx2 &x3

For PDN, take complemented form offwhich leads to result as shown in Fig.

Vx1

Vx2

Vx3

( )321321 xxxxxxf +=+=


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Consider the following function :

Build a circuit using CMOS to implement this functionality( 4321 xxxxf ++=

Example 3.2


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Consider the following function :

Step 1: Build PUNVf

VDD

( 4321 xxxxf ++=

Example 3.2

Step 2: Build PDN

Vx1

Vx2

Vx3

Vx4

( ) 4321 xxxxf ++=

( )4321! xxxxf +=


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V

VDD

V V V

Voltage Levels

Voltage levels in the NAND gate

(a) Circuit (b) Voltage levels

L

H

L

L

H

H

L

H

H

H

H

L

Vx1

Vx2

x1 x2


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Positive logic system: higher voltages represent logic

(a) Positive logic truth table and symbol of NAND gate

f00

1

1

01

0

1

11

1

0

x1 x2 f

x1

x2

Voltage Levels

Negative logic systems: the association betweenvoltages and logic values is reversed

(b) Negative logic truth table and symbol of NAND gate

1

1

0

0

1

0

1

0

0

0

0

1

x1 x2 f

fx1

x2


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Large variety of chips that implement various functions that are

useful in the design of digital hardware

The chips range from very simple ones with low functionality to

extremely complex chips Eg. A digital hardware product may require a P to perform

some arithmetic operations, memory chips to provide storage

Integrated Circuit Chips

capability, and interface chips that allow easy connection to inputand output devices

Three main types of chips:

Standard chips

Programmable logic devices

Custom chips


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Circuit ComplexityGives measure of number of transistors or

gatesWithin single package

Four general categories

Characterizing Standard Chips: Digital ICs

characterized several ways as follows:

- ma ca e< 12 gates or soMSI - Medium Scale IC

< 100 gates or so

LSI - Large Scale IC< 1000 gates or so

VLSI Very Large Scale IC

> 1000 gates or so


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Circuit Topology

Describes the input and output structure of the deviceThree general categoriesTTL - Transistor Transistor Logic

Bipolar transistors on input and output

Output section looks like described circuitReferred to as totem pole output

ECL - Emitter Coupled LogicBipolarLogic done in emitter circuitry rather than

collectorHigh speed

MOS - Metal Oxide Semiconductors

MOS transistors on input and output


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a Dual-inline acka e

Standard Chip Examples- 74LS00 is built by TTL tech.

- 74HC00 is fabricated by CMOStechnology- Most popular chips used today

are the CMOS variants

A 7400-series chip.

(b) Structure of 7404 chip

VDD

Gnd


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VDD

7404

An implementation of

x1

x2

x3

f

7408 7432

3221 xxxxf +=


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Pin

12

Pin

14

Pin

16

Pin

18

Pin

11

Pin

13

Pin

15

Pin

17

Pin

19

- Because of their low logic capacity, the standard

chips are seldom used in practice.- One exception: many modern products includestandard chips containing buffers (logic gates thatare usually used to improve the circuit speed)

The 74244 buffer chip comprises 8 tri-state

buffers

Pin

2

Pin

4

Pin

6

Pin

8

Pin

1

Pin

3

Pin

5

Pin

7

Pin

9

Buffer


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Vf

VDD

Vx

- When a logic gate has to drive a largecapacitive load, buffers are often usedto improve performance: f = x

- Buffers can be created with differentamounts of drive capability, dependingon the sizes of the transistors (will be

Buffer

A non-inverting buffer

(a) Implementation of a buffer

x f

(b) Graphical symbol

scusse ater - As used for driving higher-than-normal capacitive loads, buffers havetrs. that are larger than normal

- Not only for high speed performance,buffers are also used when highcurrent flow is needed to drive externaldevices (e.g. use buffer to control LED)


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-Inverting buffer produces the same output as an inverter butis built with relatively large transistors- As shown in figure, for large values of n an inverting buffer

could be used for the inverter labeled as N1

Inverting Buffer

Inverter that drives n other inverters

xf

n

To inputs of

n other inverters

N1


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Tri-state buffer hasadditional controlinput, called enable e

x f

e

a A tri-state buffer b E uivalent circuit

x f

e = 0

e = 1

x f

(c) Truth table

0

0

1

1

0

1

0

1

Z

Z

0

1

fe x

Four types of tri-state buffers.

x f

e

(b)

x f

e

(a)

x f

e

(c)

x f

e

(d)


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( ) ( ) 212112212121212121 ),,(

sxxsxxxsxxxs

xsxxxsxxsxxsxxsf

+=+++=

+++=

From Truth Table, derive canonical SOP form

Multiplexer


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An application of tri-state buffers: Multiplexer

fx1

x2

s

Multiplexer based on Logic gates


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Z

x

0

1

fs

fx

s

s

- A transmission gate: switch that connects xto f

- A switch is turned on by setting VS = 5V & V!S = 0V.+ Vx= 0V: NMOS isturned on, Vf = 0 (drain is

pulled down to Gnd source)+ Vx= 5V: PMOS is

(b) Truth table

s 0=

s 1=

x

x

f = Z

f = x

(c) Equivalent circuit

(a) Circuit

(d) Graphical symbol

fx

s

s

, f =

is pulled up to VDDsource)

fx

e

(e) Implementation

f fe x


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x1 fx1

Truth table: Transmission gate

Zx01

fs

Truth table: Tri-state buffer

0

01

1

0

10

1

Z

Z0

1

fe x

A 2-to-1 multiplexer builtusing transmission gates.

x2

f

s

x2

s

A 2-to-1 multiplexer builtusing tri-state buffers.

XOR G


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x1

x2

f x x=

0

0

11

0

1

01

0

1

10

x1 x2 f x1 x2=

XOR Gate

CMOS implementation

CMOS Exclusive-OR (XOR) gate.


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(a) Truth table

00

1

1

01

0

1

01

1

0

x1 x2 f x1 x2=

(b) Graphical symbol

x1

x2f x1 x2=

Logic gate based Exclusive-OR (XOR) gate.

(c) Sum-of-products implementation

f x1 x2=

x1x2

PLD


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VDD

VDD VDD VDD

S1

NOR plane

x1 x2 x3

PLD

An example of a NOR-NOR PLA.

VDD

S2

S3

NOR plane f1 f2


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x1 x2 xn PLA


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Input buffers

invertersand

1 2 n

x1 x1 xn xn

-Be realized in Sum-Of-Products form- Each Pk is configured to implement

any AND function of xi- Each fm is configured to implementan OR function of P

PLA

General structure of a PLA (Programmable Logic Array).

f1

AND plane OR plane

P1

Pk

fm

x1 x2 x3xxxxxxxf ++=


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P1

P2

OR plane

Programmableconnections

32131211 xxxxxxxf ++=

Gate-level diagram of a PLAHow to implement ?

f1 f2

AND plane

P3

P4

x1 x2 x3


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P1

P2

1 2 3

OR plane

- Customary schematic for the PLA in previous Figure- Constraint: size of AND plane (only 4 product terms)

f1 f2

AND plane

P3

P4

x1 x2 x3PAL


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f1

P1

P2

PAL

- Programmable switches present 2 difficulties in manufacturing

- PAL (Programmable Array Logic): programmable AND plane,fixed OR plane -> less flexibility than PLA

f2

AND plane

P3

P4

SelectEnable


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f1

D Q

Clock

Enable

Flip-flop

Extra circuitry added to OR-gate to provide additional functionality

To AND plane

FF represent a memory element, depend on signal clockthat the OR gate output will be hold at certain time point

Multiplexer selects output either from OR gate or from Qoutput of the D-FF.


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A SPLD programming unit (courtesy of Data IO Corp).


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CPLD Section


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PAL-like block (details not shown)

PAL-like block- A CPLD consists ofmany PAL-like blocks

CPLD Section

A section of the CPLD

D Q

D Q

D Q

nterconnecte v a

switches-A commercial CPLD has2-100 PAL-like blocks

- Each PAL-l.b. has 3macrocells.- Each macrocell someOR gates .


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(a) CPLD in a Quad Flat Pack (QFP) package

To computer

CPLD packaging and programming.

Printed

circuit board

(b) JTAG programming

FPGA


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-FPGA differ from CPLD (noAND OR gates)

- Use logic blocks toimplement required functions- 3 main resources: lo ic

FPGA

A field-programmable gate array (FPGA).

blocks, I/O blocks,interconnect. wires &switches- LB: 2-d array

- Interconnection: h. & v.routing channels

LUT (Look-Up Table)


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A two-input lookup table (LUT)

LUT (Look Up Table)

- Each L.B. typically has a small number of inputs & outputs.

- The most commonly used L.B. is LUT (lookup table) whichcontains storage cells. The stored values (0/1) is produced asthe output of the storage cell.- LUTs have various sizes which are defined by number ofinputs

Gate Multiplexer


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( ) ( ) 212112212121212121 ),,(

sxxsxxxsxxxs

xsxxxsxxsxxsxxsf

+=+++=

+++=

From Truth Table, derive canonical SOP form

p

x1 LUT Multiplexer


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(a) Circuit for a two-input LUT

x2

f

0/1

0/1

0/1

0/1

0

0

1

1

0

1

0

1

1

0

0

1

x1

x2

(b) f 1 x1x2 x1x2+=

f 1

p

A two-input lookup table (LUT).(c) Storage cell contents in the LUT

x1

x2

1

0

0

1

f 1

- A two-variable TT has 4 rows

needs 4 cells.

- Three multiplexers controlled by

x1 & x2

- Explain principle ?

Example


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0/1

0/1

0/1

0/1

x2

x1

Try to check its function by

using Truth Table

p

A three-input LUT.

0/10/1

0/1

0/1

x3

LUT Extra Circuit


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Out

Select

Flip-flopIn1

Inclusion of a flip-flop in an FPGA logic block.

D Q

Clock

In2

In3LUT

- The FF is used to store the value of its D input under control of

its clock input.

x3 f

LUT in FPGA


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01

0

0

00

0

1

x1

x2

x2

x3

f 1 f 2

x1

x2

- Two-input LUTs

- Four wires in each

routing channel- Fig. shows

programmed states of

the L.Bs. & switches

Section of a programmed FPGA.

0

1

1

1

f1

f 2

f

+ Blue switches: ON

+ Black switches: OFF

21

322

211

fff

xxf

xxf

+=

=

=


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A sea-of-gates gate array

f 1


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x1

x2

The logic function f1 = x2x3+x1x3 in the gate array

x3

Lec31-LogicGateCMOS

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