Lec-MIPS Instruction Set Processor.pdf

8/10/2019 Lec-MIPS Instruction Set Processor.pdf

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Instruction Set Processor

Ajit Pal

ProfessorDepartment of Computer Science and Engineering

Indian Institute of Technology Kharagpur

INDIA-721302

Computer Architecture and Organization Introduction

Starting point: The specification of the MIPS instruction set drives the design of the

hardware. Will restrict design to integer type instructions

Identify common functions to all instructions, and within instructionclasses easy to do in a RISC architecture Instruction fetch Access one or more registers Use ALU

Asserted signals a high or low levelof a signal which implies a logicallytrue condition an action level. The text will only assert a logicallyhigh level, ie., a 1.

Clocking Assume edge triggered clocking (as opposed to level sensitive). A storage circuit or flip-flop stores a value on the clock transition

edge. Model is flip-flops with combinational logic between them Propagation delay through combinations logic between storage

elements determines clock cycle length. Single clock cycle vs. multi-clock cycle design approach

Single Versus Multi-clock Cycle Design

Start out with a single long clock cycle for each instruction .

Entire instruction gets executed in a single clock pulse

Controller is pure combinational logic

Design is simple

You would think that a single clock cycle per instructionexecution would give us super high performance but not so:

Slowest instruction determines speed of all instructions.

Because various phases of the instructions need the samehardware resource, and all is needed at the same time (clockpulse)

Some hardware is redundant another disadvantage of

single phaseExamples:2 memories: instruction and data memory2 adders and an ALU

Design Summary

Has a performance bottleneck The clock cycle time is determined by the longest path

in the machine The simple jmp instruction will take as long as the load

word (lw)

The instruction which uses the longest data pathdictates the time for all others.

What about a variable time clock design? Still a single clock Clock pulse interval is a function of the opcode Average time for instruction theoretically improves

But

It difficult to implement - lots of overhead to overcome

Lets start simple with a single clock cycle design forsimplicity reasons and later convert to multi-clock cycle.


2/30

Basic Abstract View of the Data Path

Shows common functions for most instructions

Registers

Register #

Data

Register #

Data

memory

Address

Data

Register #

PC Instruction ALU

Instructionmemory

Address

Data Path for Instruction Fetching

PC

Instruction

memory

Readaddress

Instruction

4

Add

Basic Data Path for R-type Instruction

Red lines are for control signalsgenerated by the controller

InstructionRegisters

Writeregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Zero

RegWrite

ALU operation3

Adding the Data Path for lw & sw Instruction

Implements:

lw $t1, offset_value($t2)sw $t1, offset_value($t2)The offset value is a 16-bit signed immediatefield & must be sign extended to 32 bits

Immediateoffset data

Instruction

16 32

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Datamemory

Writedata

Readdata

Writedata

Sign

extend

ALUresult

Zero

ALU

Address

MemRead

MemWrite

RegWrite

ALU operation3


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4/30

Ajit Pal, IIT Kharagpur

Animating the Datapath

lw rt, offset(rs)

R[rt]


5/30


Animating the Datapath: R-typeInstruction

add rd,rs,rt5 516

RD1

RD2

RN1 RN2 WN

WD

RegWrite

Register File

Operation

ALU

3

EXT

ND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDR

MemWrite

5

Instruction

32

M

UX

MUXALUSrc

MemtoReg


Animating the Datapath:Load Instruction

lw rt,offset(rs)5 516

RD1

RD2

RN1 RN2 WN

WD

RegWrite

Register File

Operation

ALU

3

EXT

ND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDR

MemWrite

5

Instruction

32

M

UX

MUXALUSrc

MemtoReg


Animating the Datapath:Store Instruction

sw rt,offset(rs)5 516

RD1

RD2

RN1 RN2 WN

WD

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDR

MemWrite

5

nstruct on

32

M

UX

MUXALUSrc

MemtoReg


MIPS Datapath II: Single-Cycle

PC

Instructionmemory

Readaddress

Instruction

16 32

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

ALUresult

Zero

Datamemory

Address

Writedata

Readdata

Mux

4

Add

Mux

ALU

RegWrite

ALU operation3

MemRead

MemWrite

ALUSrcMemtoReg

Adding instruction fetch

Separate instruction memoryas instruction and data read

occur in the same clock cycle

Separate adder as ALU operations and PCincrement occur in the same clock cycle


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Datapath Executingbeq

beq r1,r2,offset

5 516

RD1

RD2

RN1 RN2 WN

WD

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDR

MemWrite

5

Instruction

32

M

U

X

ALUSrc

MemtoReg

ADD


8/30


Setting ALU Control Bits

Instruction AluOp Instruction Funct Field Desired ALU

control

opcode operation ALU action input

LW 00 load word xxxxxx add 010

SW 00 store word xxxxxx add 010

Branch eq 01 branch eq xxxxxx subtract 110

R-type 10 add 100000 add 010

R-type 10 subtract 100010 subtract 110

R-type 10 AND 100100 and 000

R-type 10 OR 100101 or 001

R-type 10 set on less 101010 set on less 111

Truth table for ALU control bits

*

ALUOp Funct field Operation

ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F00 0 X X X X X X 010

0 1 X X X X X X 110

1 X X X 0 0 0 0 010

1 X X X 0 0 1 0 110

1 X X X 0 1 0 0 000

1 X X X 0 1 0 1 001

1 X X X 1 0 1 0 111

Setting ALU Control Bits


Designing the Main Control

Observations about MIPS instruction format opcode is always in bits 31-26

two registers to be read are always rs (bits 25-21) and rt

(bits 20-16)

base register for load/stores is always rs (bits 25-21)

16-bit offset for branch equal and load/store is always

bits 15-0

destination register for loads is in bits 20-16 (rt) while forR-type instructions it is in bits 15-11 (rd) (will require

multiplexor to select)

31-26 25-21 20-16 15-11

10-6 5-0

31-26 25-21 20-16 15-0

opcode

opcode

rs

rs

rt

rt address

rd shamt functR-type

Load/storeor branch


Datapath with Control-I

MemtoReg

MemRead

MemWrite

ALUOp

ALUSrc

RegDst

PC

Instructionmemory

Readaddress

Instruction[310]

Instruction [20 16]

Instruction [25 21]

Add

Instruction [50 ]

RegWrite

4

16 32Instruction [15 0]

0

Registers

Writeregister

Writedata

Writedata

Readdata 1

Readdata 2

Read

register 1Readregister 2

Signextend

ALUresult

Zero

Datamemory

Address Readdata

Mux

1

0

Mux

1

0

Mux

1

0

Mux

1

Instruction [15 11]

ALUcontrol

Shift

left 2

PCSrc

ALU

Add ALUresult

Adding control to the MIPS Datapath III (and a new multiplexor to select field tospecify destination register): what are the functions of the 9 control signals?

Newmultiplexor


9/30


10/30


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R t I t ti St 4


12/30


R-type Instruction: Step 4add $t1, $t2, $t3 (active = bold)

PC

Instructionmemory

Readaddress

Instruction[310]

Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

RegDst

ALUSrc

Instruction [31 26]

4


0

0Mux

0

1

ALUcontrol

Control

Shiftleft 2

Add ALUresult

Mux

0

1


Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1

Instruction [15 11]

ALU

Address

Write result to register


Single-cycle Implementation Notes

The steps are not really distinctas each instruction completes

in exactly one clock cycle they simply indicate the sequence

of data flowing through the datapath

The operation of the datapath during a cycle is purely

combinational nothing is stored during a clock cycle

Therefore, the machine is stable in a particular state at the

start of a cycle and reaches a new stable state only at the end

of the cycle

Very important for understanding single-cycle computing


1. Fetch instruction and increment PC

2. Read base register from the register file: the base

register ($t2) is given by bits 25-21 of the instruction

3. ALU computes sum of value read from the registerfile and the sign-extended lower 16 bits (offset) of

the instruction

4. The sum from the ALU is used as the address for the

data memory

5. The data from the memory unit is written into the

register file: the destination register ($t1) is given bybits 20-16 of the instruction

Load Instruction Stepslw $t1, offset($t2)


Load Instructionlw $t1, offset($t2)

PC

Instructionmemory

Readaddress

Instruction[310]

Instruction [1511]

Instruction [2016]

Instruction [2521]

Add

Instruction [50]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

RegDst

ALUSrc

Instruction [3126]

4


0

0Mux

0

1

ALUcontrol

Control

Shiftleft 2

Add ALUresult

Mux

0

1


Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Sign

extend

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1

ALU

Address


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Multicycle Approach Multicycle Approach


15/30


Break up the instructions into steps each step takes one clock cycle balance the amount of work to be done in each step/cycle so

that they are about equal

restrict each cycle to use at most once each major functionalunit so that such units do not have to be replicated

functional units can be shared between different cycles withinone instruction

Between steps/cycles At the end of one cycle store data to be used in later cycles of

the same instruction need to introduce additional internal(programmer-invisible)

registers for this purpose

Data to be used in later instructions are stored in programmer-visible state elements: the register file, PC, memory

Multicycle Approach


Note particularities of multicyle vs. single-

diagrams single memory for

data and instructions single ALU, no extra

adders

extra registers tohold data betweenclock cycles

Multicycle Approach

PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Shift

left 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

Zero

ALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

Add

PC

Memory

Address

Instructionor data

Data

Instructionregister

Registers

Register #

Data

Register #

Register #

ALU

Memory

data register

A

B

ALUOut

Single-cycle datapath

Multicycle datapath (high-level view)


Multicycle Datapath

Shift

left 2

PC

Memory

MemData

Writedata

Mux

0

1


Writedata

Readdata 1

Read

data 2

Readregister 1

Readregister 2

M

u

x

0

1

Mux

0

1

4

Instruction[150]

Sign

extend

3216

Instruction[2521]

Instruction[2016]

Instruction[150]

Instruction

register1M

ux

0

3

2

Mux

ALUresult

ALU

Zero

Memory

data

register

Instruction

[1511]

A

B

ALUOut

0

1

Address

Basic multicycle MIPS datapath handles R-type instructions and load/stores:

new internal register in red ovals, new multiplexors in blue ovals


Our goal is to break up the instructions into steps

so that

each step takes one clock cycle

the amount of work to be done in eachstep/cycle is about equal

each cycle uses at most once each major

functional unit so that such units do not have to

be replicated

functional units can be shared between

different cycles within one instruction Data at end of one cycle to be used in next must

be stored!!

Breaking instructions into steps


16/30

Step 4: Memory access or R-type

Step 5: Memory Read Completion (WB)


17/30


Again dependingon instruction type:

Loads and stores access memory loadMDR = Memory[ALUOut]; store (instruction completes)Memory[ALUOut] = B;

R-type (instructions completes)

Reg[IR[15-11]] = ALUOut;

Step 4: Memory access or R typeInstruction Completion(MEM)


Again dependingon instruction type:

Load writes back (instruction completes)

Reg[IR[20-16]]= MDR;

Important: There is no reason from a datapath (orcontrol) point of view that Step 5 cannot beeliminated by performing

Reg[IR[20-16]]= Memory[ALUOut];

for loads in Step 4. This would eliminate the MDRas well.

The reason this is not done is that, to keep stepsbalanced in length, the design restriction is to alloweach step to contain at most one ALU operation, orone register access, or one memory access.

Step 5: Memory Read Completion (WB)


Summary of Instruction Execution

Step name

Action for R-type

instructions

Action for memory-reference

instructions

Action for

branches

Action for

jumps

Instruction fetch IR = Memory[PC]

PC = PC + 4

Instruction A = Reg [IR[25-21]]

decode/register fetch B = Reg [IR[20-16]]

ALUOut = PC + (sign-extend (IR[15-0 ])


18/30


Multicycle Execution Step (2):Instruction Decode & Register Fetch

A = Reg[IR[25-21]]; (A = Reg[rs])

B = Reg[IR[20-15]]; (B = Reg[rt])

ALUOut = (PC + sign-extend(IR[15-0])


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Jump InstructionPC = PC[31-28] concat (IR[25-0]


20/30


21/30


22/30

Multicycle Execution Steps (5)Memory Read Completion (lw)

Implementing Control


23/30


Memory Read Completion (lw)

Reg[IR[20-16]] = MDR;

1

0

0

X0

0

X0 X

X

XXX

0

5 5

RD1

RD2

RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

Memory

ADDRMemWrite

5

Instruction I

32

ALUSrcB


24/30


g

Memory access

instructions(Figure 5.38)

R-type instructions(Figure 5.39)

Branch instruction(Figure 5.40)

Jump instruction(Figure 5.41)

Instruction fetch/decode and register fetch(Figure 5.37)

Start

ALUSrcA = 0ALUSrcB = 11

ALUOp = 00

MemReadALUSrcA = 0

IorD = 0IRWrite

ALUSrcB = 01ALUOp = 00

PCWritePCSource = 00

Instruction fetchInstruction decode/

Register fetch

(Op='LW

')or(Op

='SW') (Op=

R-type

)

(Op

='B

EQ')

(Op='JMP')

01

Start

Memory reference FSM(Figure 5.38)

R-type FSM(Figure 5.39)

Branch FSM(Figure 5.40)

Jump FSM(Figure 5.41)

High-level view of FSM control

Instruction fetch and decode steps of every instruction is identical

Asserted signalsshown insidestate circles


MemWrite

IorD = 1

MemRead

IorD = 1

ALUSrcA = 1

ALUSrcB = 10

ALUOp = 00

RegWrite

MemtoReg = 1RegDst = 0

Memory address computation

(Op = 'LW') or (Op = 'SW')

Memoryaccess

Write-back step

(Op

='SW')

(Op='LW')

4

2

53

From state 1

To state 0

(Figure 5.37)

Memoryaccess

FSM control formemory-reference

has 4 states


FSM Control: R-type Instruction

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 10

RegDst = 1

RegWrite

MemtoReg = 0

Execution

R-type completio

6

7

(Op = R-type)

From state 1

To state 0

(Figure 5.37)

FSM control to implement R-type instructions has 2 states


FSM Control: Branch Instruction

Branch completion

8

(Op = 'BEQ')

From state 1

To state 0

(Figure 5.37)

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 01PCWriteCond

PCSource = 01

FSM control to implement branches has 1 state

FSM Control: Jump Instruction FSM Control: Complete View


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Jump completion

9

(Op = 'J')

From state 1

To state 0(Figure 5.37)

PCWritePCSource = 10

FSM control to implement jumps has 1 state


PCWrite

PCSource = 10

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 01

PCWriteCondPCSource = 01

ALUSrcA =1

ALUSrcB = 00ALUOp= 10

RegDst = 1RegWrite

MemtoReg = 0

MemWrite

IorD = 1

MemRead

IorD = 1

ALUSrcA = 1

ALUSrcB = 10ALUOp = 00

RegDst=0

RegWrite

MemtoReg=1

ALUSrcA = 0

ALUSrcB = 11

ALUOp = 00

MemRead

ALUSrcA = 0

IorD = 0

IRWriteALUSrcB = 01

ALUOp = 00PCWrite

PCSource = 00

Instruction fetchInstruction decode/

register fetch

Jumpcompletion

BranchcompletionExecution

Memory address

computation

Memoryaccess

Memoryaccess R-type completion

Write-back step

(Op='LW')or(O

p='SW'

) (Op=

R-type

)

(Op

='BEQ')

(Op='J')

(Op

='SW')

(Op='LW')

4

01

9862

753

Start

The complete FSM control for the multicycle MIPS datapath:refer Multicycle Datapath with Control II

Labels on arcs are conditionsthat determine next state

IF ID

EX

MEM

WB


Example: CPI in a multicycle CPU

Assume the control design of the previous slide An instruction mix of 22% loads, 11% stores, 49% R-type

operations, 16% branches, and 2%jumps

What is the CPI assuming each step requires 1 clock cycle?

Solution: Number of clock cycles from previous slide for each

instruction class: loads 5, stores 4, R-type instructions 4, branches 3,

jumps 3 CPI = CPU clock cycles / instruction count

= (instruction countclass i CPIclass i) / instructioncount

= (instruction countclass I/ instruction count) CPIclassI

= 0.22 5 + 0.11 4 + 0.49 4 + 0.16 3 + 0.02 3 = 4.04


FSM Control: Implementation

High-level view of FSM implementation: inputs to the combinational logic block arethe current state number and instruction opcode bits; outputs are the next state

number and control signals to be asserted for the current state

PCWrite

PCWriteCond

IorD

MemtoReg

PCSource

ALUOp

ALUSrcB

ALUSrcA

RegWrite

RegDst

NS3

NS2

NS1

NS0

Op5

Op4

Op3

Op2

Op1

Op0

S3

S2

S1

S0

State register

IRWrite

MemRead

MemWrite

Instruction register

opcode field

Outputs

Control logic

Inputs

Four state bits are required for 10 states


26/30

Microprogramming Control Microprogram


27/30


The Sequencing field value determines the execution

order of the microprogram

value Seq: control passes to the sequentially next

microinstruction

value Fetch : branch to the first microinstruction to begin

the next MIPS instruction, i.e., the first microinstruction in

the microprogram

value Dispatch i: branch to a microinstruction based on

control input and a dispatch table entry (called

dispatching):

Dispatching is implemented by means of creating a table,

called dispatch table, whose entries are microinstruction

labels and which is indexed by the control input. There may

be multiple dispatch tables the value Dispatch iin the

sequencing field indicates that the ith dispatch table is to be

used


The microprogram corresponding to the FSM control

shown graphically earlier:

Label

ALU

control SRC1 SRC2

Register

control Memory

PCWrite

control Sequencing

Fetch Add PC 4 Read PC ALU Seq

Add PC Extshft Read Dispatch 1Mem1 Add A Extend Dispatch 2

LW2 Read ALU Seq

Write MDR Fetch

SW2 Write ALU Fetch

Rformat1 Func code A B Seq

Write ALU Fetch

BEQ1 Subt A B ALUOut-cond Fetch

JUMP1 Jump address Fetch

Dispatch ROM 1

Dispatch ROM 2Op Opcode name Value

Op Opcode name Value000000 R-format Rformat1

100011 lw LW2000010 jmp JUMP1

101011 sw SW2000100 beq BEQ1

100011 lw Mem1

101011 sw Mem1

Microprogram containing 10 microinstructions

Dispatch Table 2

Dispatch Table 1


Microcode: Trade-offs

Specification advantages

easy to design and write

typically manufacturer designs architecture and microcode in

parallel

Implementation advantages

easy to change since values are in memory (e.g., off-chip ROM)

can emulate other architectures

can make use of internal registers

Implementation disadvantages

control is implemented nowadays on same chip as processor so

the advantage of an off-chip ROM does not exist

ROM is no longer faster than on-board cache

there is little need to change the microcode as general-purpose

computers are used far more nowadays than computers

designed for specific applications

Instruction RegDst RegWrite ALUSrc MemRea

d

MemWri

te

MemToReg PCSrc ALU

operation

R-format 1 1 0 0 0 0 0 0000

(and)

0001

(or)

0010

(add)

0110

(sub)

lw 0 1 1 1 0 1 0 0010

(add)

sw X 0 1 0 1 X 0 0010

(add)

beq x 0 0 0 0 X 1 or 0 0110

(sub)

Control Control Unit


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We next add the control unit that generates

write signal for each state element control signals for each multiplexer

ALU control signal

Input to control unit: instruction opcode and function

code

Divided into two parts

Main Control Unit

Input: 6-bit opcode

Output: all control signals for Muxes, RegWrite,

MemRead, MemWrite and a 2-bit ALUOp signal

ALU Control Unit

Input: 2-bit ALUOp signal generated from Main

Control Unit and 6-bit instruction function codeOutput: 4-bit ALU control signal

Truth Table for Main Control Unit Main Control Unit

ALU Control Unit ALU Control bits


29/30

Must describe hardware to compute 4-bit ALUcontrol input given

2-bit ALUOp signal from Main Control Unit

function code for arithmetic

Describe it using a truth table (can turn into gates):

0010

0010

0110

0010

0110

0000

0001

0111

Putting It All Together Again

PC

Instructionmemory

Readaddress

Instruction[310]

Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

RegDst

ALUSrc

Instruction [31 26]

4


0

0Mux

0

1

Control

Add ALUresult

Mux

0

1


Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

PCSrc

Datamemory

Writedata

Readdata

Mux

1

Instruction [15 11]

ALUcontrol

Shiftleft 2

ALUAddress

Use this for R-type, memory, & beq instructions scenarios.

Addition of the Unconditional Jump

We now add one more op code to our single cycle design: Op code 2: j The format is op field 28-31 is a 2 Remaining 26 low bits is the immediate target address

The full 32 bit target address is computed by concatenating: Upper 4 bits of PC+4 26 bit immediate field of the jump instruction Bits 00 in the lowest positions (word boundary) See text chapter 3, p. 150

An additional control line from the main controller will have tobe generated to select this new instruction

A two bit shifter is also added to get the two low order zeros

Final Design with jump Instruction


30/30

Shiftleft2

PC

Instruction

memory

Readaddress

Instruction[310]

Datamemory

Readdata

Writedata


Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Instruction[15 11]

Instruction[20 16]

Instruction[25 21]

Add

ALUresult

Zero

Instruction[5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

JumpRegDst

ALUSrc

Instruction[31 26]

4

Mux

Instruction[25 0] Jumpaddress[31 0]

PC+4 [31 28]

Signextend

16 32Instruction[15 0 ]

1

Mux

1

0

Mux

0

1

Mux

0

1

ALUcontrol

Control

Add ALUresult

Mux

0

1 0

ALU

Shiftleft 2

26 28

Address


Thanks!

Lec-MIPS Instruction Set Processor.pdf

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