CMOS Digital Integrated Circuits1

CMOS Digital Integrated Circuits

Lec 9

Super Buffer Design

CMOS Digital Integrated Circuits2

Supper Buffer

Given a large capacitance load Cload

• How many stages are needed to minimize the delay?

• How to size the inverters?

Supper Buffer

Cload

1 2 N1

Cg Cd Cg 2CgCd 2Cd NCg NCd Cload

Equiv INV

N: number of inverter stages

: optimal stage scale factor

CMOS Digital Integrated Circuits3

Supper Buffer (Cont.)

where• Cg: the input capacitance of the first stage inverter.

• Cd: the drain capacitance of the first stage inverter.

• Each inverter is scaled up by a factor of per stage.

• Cload = N+1Cg

• All inverters have identical delay of 0(Cd+Cg)/(Cd+Cg) which 0 is per gate delay for Equiv INV in ring oscillator circuit with load capacitance = Cg+Cd

CMOS Digital Integrated Circuits4

Supper Buffer Design

• Consider N stages, each inverter has same delay 0(Cd+Cg)/(Cd+Cg).

Therefore,

CC

CCNgd

gdtotal

01

1 2 N1

Cg Cd Cg 2CgCd 2Cd NCg NCd Cload

Equiv INV

dd dd

CMOS Digital Integrated Circuits5

Supper Buffer Design (Cont.)

• Goal: Choose and N to minimize total.

» By Cload = N+1Cg, we have

» Plug the above equation into total, we get

» To minimize total:

ln

ln

1

C

C

Ng

load

CC

CCCC

d g

gdg

load

total

0

ln

ln

0

ln

1

ln

1

ln 20

CC

CCC

CC

C

C

d g

g

d g

gd

g

loadtotal

C

C

g

doptopt 1ln

CMOS Digital Integrated Circuits6

Supper Buffer Design (Con.)

» For the special case Cd=0 ln(opt)=0 opt = e. However, in reality the drain parasitics cannot be ignored.

• Example: For Cd=0.5 fF, Cg=1 fF, determine opt and N for Cload = 50 pF.

opt (ln opt -1) = 0.5 opt = 3.18

The Super Buffer Design which minimizes total for Cload = 50 pF is N=7 Equiv INV stages, and opt = 3.18

36.6

118.3ln/101/1050ln

1ln//ln

ln

/ln1

1412

optgload

opt

gload

CCN

CCN

CMOS Digital Integrated Circuits7

CMOS Ring Oscillator Circuit• Oscillation period T is equal to

T=PHL1+PLH1+PHL2+PLH2+PHL3+PLL3

=2p+2p+2p

=3·2p=6p

• For arbitrary odd number (n) of cascade-connected invertes, we have

f=1/T=1/(2·n·p)

• Also, we can write

p=1/(2·n·f)

V1

Cload,1 Cload,2 Cload,3

V2 V3

1 2 3

CMOS Digital Integrated Circuits8

Voltage Waveforms of Ring Oscillator

τPHL2

Vout

VOH

V50%

tVOL

τPLH3 τPHL1 τPLH2 τPHL3 τPLH1

V2 V1 V3 V2 V1 V3

T