Lec. 7: Successive Approximation Register ADC...
Transcript of Lec. 7: Successive Approximation Register ADC...
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Lec. 7:
Successive Approximation Register ADC
(SAR)
Lecturer: Hooman Farkhani
Department of Electrical Engineering
Islamic Azad University of Najafabad
Feb. 2016.
Email: [email protected]
In The Name of Almighty
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SAR ADC: Based on Binary Search Algorithm
Binary search algorithm → N*Tclk to complete N bits
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Implementation: DAC-Based SAR ADC
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Binary Search Algorithm
– 4 –
• DAC output gradually approaches the input voltage
• Comparator differential input gradually approaches zero
VDAC
t
Vi
0
VFS
1 0 0 1 1 0
MSB LSBTclk
VFS
2
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Charge Redistribution SA ADC
– 5 –
• 4-bit binary-weighted capacitor array DAC
• Capacitor array samples input when Φ1 is asserted (bottom-plate)
SAR
Do
Φ1e
VX
2C C C8C 4C
VR
Vi
Φ1 Φ1 Φ1 Φ1 Φ1
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Charge Redistribution (MSB)
– 6 –
SAR
Do
Φ1e
VX
2C C C8C 4C
VR
Vi
Φ1 Φ1 Φ1 Φ1 Φ1
R i Ri R X 4 X 3 2 1 0 X i
V 8C- V 16C VV 16C = V - V C - V C +C +C +C V - V
16C 2
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Comparison (MSB)
– 7 –
• If VX < 0, then Vi > VR/2, and MSB = 1, C4 remains connected to VR
• If VX > 0, then Vi < VR/2, and MSB = 0, C4 is switched to ground
VX
t0
1
MSBSample
1
iR
X V2
V V:TEST MSB
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Charge Redistribution (MSB-1)
– 8 –
R ii R X X X R i
V 12C V 16C 3V 16C V V 12C V 4C V V V
16C 4
SAR
Do
Φ1e
VX
2C C C8C 4C
VR
Vi
Φ1 Φ1 Φ1 Φ1 Φ1
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Comparison (MSB-1)
– 9 –
• If VX < 0, then Vi > 3VR/4, and MSB-1 = 1, C3 remains connected to VR
• If VX > 0, then Vi < 3VR/4, and MSB-1 = 0, C3 is switched to ground
X R i
3MSB-1 TEST : V V V
4
VX
t0
1 0
MSBSample
1 2
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Charge Redistribution (Other Bits)
– 10 –
Test completes when all four bits are determined w/ four charge r
edistributions and comparisons
SAR
Do
Φ1e
VX
2C C C8C 4C
VR
Vi
Φ1 Φ1 Φ1 Φ1 Φ1
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After Four Clock Cycles…
– 11 –
• Usually, half Tclk is allocated for charge redistribution and half for
comparison + digital logic
• VX always converges to 0 (Vos if comparator has nonzero offset)
VX
t0
1 0 0 1
MSB LSBSample
1 2 3 4
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Summing-Node Parasitics
– 12 –
• If Vos = 0, CP has no effect eventually; otherwise, CP attenuates VX
• Auto-zeroing can be applied to the comparator to reduce offset
SAR
Do
Φ1e
2C C C8C 4C
VR
Vi
Φ1 Φ1 Φ1 Φ1 Φ1
CP
Vos
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SAR Logic
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SAR Advantages
Useful for signals from 1Hz to 1MHz:
- Internal clock must be faster than signal depending on the
resolution
Very Power efficient and can be implemented very accurately:
- less power with same resolution and BW than other converters
(see ISSCC)- only comparator consumes DC power.
Does not need internal opamps: Only uses a single comparator
Lower KT/C noise: No input referred noise from other stages
(no additional S/H: in some architectures)
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SAR Challenges
Every single bit acquired must be accurate to the resolution of
the system:
- DAC non-linearity limits the INL and DNL of the SA ADC N-bit precision requires N-bit matching from the cap array
Calibration can be performed to remove mismatch errors (Lee, JSSC’84
)
- Comparator Offset
- S/H offset and linearity (If the architecture has S/H)
Comparator must respond to large changes (In some SAR archit
ectures)
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SAR Challenges
Bandwidth limitation:
- For N-bit resolution, N bit cycles are required, reducing the
effective sampling frequency by N
- Conversion speed is limited by comparator, DAC, and digital
logic (successive approximation register or SAR)
Binary search is sensitive to intermediate errors made during se
arch – if an intermediate decision is wrong, the digitization pro
cess cannot recover
DAC must settle into ±½ LSB bound within the time allowed
Comparator offset must be constant (no hysteresis or time-dependent of
fset)
Non-binary search algorithm can be used (Kuttner, ISSCC’02)
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References
Professor Boris Murmann Course slides 2012,
Stanford University- EE315B course
Professor Y. Chiu course slides, Fall 2014.
(University of Texas, Dallas)