© LDPC Codes With Minimum Distance Proportional to Block SizeThese codes offer both low decoding thresholds and low error floors.NASA’s Jet Propulsion Laboratory, Pasadena, California

Low-density parity-check (LDPC) codescharacterized by minimum Hamming dis-tances proportional to block sizes havebeen demonstrated. Like the codes men-tioned in the immediately preceding arti-cle, the present codes are error-correctingcodes suitable for use in a variety of wire-less data-communication systems that in-clude noisy channels.

The previously mentioned codes havelow decoding thresholds and reasonablylow error floors. However, the minimumHamming distances of those codes donot grow linearly with code-block sizes.Codes that have this minimum-distanceproperty exhibit very low error floors.Examples of such codes include regularLDPC codes with variable degrees of atleast 3. Unfortunately, the decodingthresholds of regular LDPC codes arehigh. Hence, there is a need for LDPCcodes characterized by both low decod-ing thresholds and, in order to obtainacceptably low error floors, minimumHamming distances that are propor-tional to code-block sizes.

The present codes were developed tosatisfy this need. The minimum Ham-ming distances of the present codes havebeen shown, through consideration ofensemble-average weight enumerators,to be proportional to code block sizes.As in the cases of irregular ensembles,the properties of these codes are sensi-tive to the proportion of degree-2 vari-able nodes. A code having too few suchnodes tends to have an iterative decod-ing threshold that is far from the capac-ity threshold. A code having too manysuch nodes tends not to exhibit a mini-mum distance that is proportional toblock size.

Results of computational simulationshave shown that the decoding thresh-olds of codes of the present type arelower than those of regular LDPC codes.Included in the simulations were a fewexamples from a family of codes charac-terized by rates ranging from low to highand by thresholds that adhere closely totheir respective channel capacity thresh-olds; the simulation results from these

examples showed that the codes in ques-tion have low error floors as well as lowdecoding thresholds.

As an example, the illustration showsthe protograph (which represents theblueprint for overall construction) ofone proposed code family for coderates greater than or equal to 1⁄2. Anysize LDPC code can be obtained bycopying the protograph structure Ntimes, then permuting the edges. Theillustration also provides Field Pro-grammable Gate Array (FPGA) hard-ware performance simulations for thiscode family. In addition, the illustrationprovides minimum signal-to-noise ra-tios (Eb/No) in decibels (decodingthresholds) to achieve zero error ratesas the code block size goes to infinityfor various code rates. In comparisonwith the codes mentioned in the pre-ceding article, these codes have slightlyhigher decoding thresholds.

The present codes offer one main dis-advantage with respect to the codes de-scribed previously: These codes do not

Accumulate-Repeat-Jagged-Accumulate (ARJA) LDPC Code Family is illustrated as follows: (a) protograph, (b) performance of FPGA hardware decoder, and(c) decoding thresholds.

30 NASA Tech Briefs, October 2009

https://ntrs.nasa.gov/search.jsp?R=20090035896 2018-07-08T20:06:05+00:00Z

lend themselves to computationally effi-cient structures that can be imple-mented in high-speed encoder hard-ware. However, high-speed encoderimplementation can be expected to be asubject of future research.

This work was done by Dariush Divsalar,Christopher Jones, Samuel Dolinar, and Je-

remy Thorpe of Caltech for NASA’s Jet Propul-sion Laboratory.

In accordance with Public Law 96-517,the contractor has elected to retain title to thisinvention. Inquiries concerning rights for itscommercial use should be addressed to:

Innovative Technology Assets ManagementJPL

Mail Stop 202-2334800 Oak Grove DrivePasadena, CA 91109-8099(818) 354-2240E-mail: iaoffice@jpl.nasa.gov

Refer to NPO-42063, volume and numberof this NASA Tech Briefs issue, and thepage number.

© Constructing LDPC Codes From Loop-Free Encoding ModulesHigh-speed iterative decoders can readily be implemented in hardware.NASA’s Jet Propulsion Laboratory, Pasadena, California

A method of constructing certain low-density parity-check (LDPC) codes byuse of relatively simple loop-free codingmodules has been developed. The sub-classes of LDPC codes to which themethod applies includes accumulate-re-peat-accumulate (ARA) codes, accumu-late-repeat-check-accumulate codes, andthe codes described in “Accumulate-Re-peat-Accumulate-Accumulate Codes”(NPO-41305), NASA Tech Briefs, Vol. 31,No. 9 (September 2007), page 90. All ofthe affected codes can be characterizedas serial/parallel (hybrid) concatena-tions of such relatively simple modulesas accumulators, repetition codes, differ-entiators, and punctured single-paritycheck codes. These are error-correctingcodes suitable for use in a variety of wire-less data-communication systems that in-clude noisy channels. These codes canalso be characterized as hybrid turbolikecodes that have projected graph or pro-tograph representations (for examplesee figure); these characteristics make itpossible to design high-speed iterativedecoders that utilize belief-propagationalgorithms.

The present method comprises tworelated submethods for constructingLDPC codes from simple loop-free mod-ules with circulant permutations. Thefirst submethod is an iterative encodingmethod based on the erasure-decodingalgorithm. The computations requiredby this method are well organized be-cause they involve a parity-check matrixhaving a block-circulant structure.

The second submethod involves theuse of block-circulant generator matri-ces. The encoders of this method arevery similar to those of recursive convo-lutional codes. Some encoders accord-ing to this second submethod have beenimplemented in a small field-program-mable gate array that operates at a speedof 100 megasymbols per second.

By use of density evolution (a compu-tational-simulation technique for analyz-ing performances of LDPC codes), it hasbeen shown through some examplesthat as the block size goes to infinity, lowiterative decoding thresholds close tochannel capacity limits can be achievedfor the codes of the type in question hav-ing low maximum variable node de-

grees. The decoding thresholds in theseexamples are lower than those of thebest-known unstructured irregularLDPC codes constrained to have thesame maximum node degrees. Further-more, the present method enables theconstruction of codes of any desired ratewith thresholds that stay uniformly closeto their respective channel capacitythresholds.

This work was done by Dariush Divsalar,Samuel Dolinar, Christopher Jones, JeremyThorpe, and Kenneth Andrews of Caltech forNASA’s Jet Propulsion Laboratory.

In accordance with Public Law 96-517,the contractor has elected to retain title to thisinvention. Inquiries concerning rights for itscommercial use should be addressed to:

Innovative Technology Assets ManagementJPLMail Stop 202-2334800 Oak Grove DrivePasadena, CA 91109-8099(818) 354-2240E-mail: iaoffice@jpl.nasa.govRefer to NPO-42042, volume and number

of this NASA Tech Briefs issue, and thepage number.

ARA Cod ing With Repeat 3, Rate 1/2 Protog raph

Systemati c Bits to Channel

2 2Output

Puncture Rep i^

4X0 3 i punctureπ 00x i 0 0 1 1Puncture Rep

^0X

i 3 -D 3

D AccumulationJ Repeat 3 Threshold 0.51 6 d B

Accumulation Permutation (Interleavin g)

A Simple Rate-1/2 ARA Code is depicted here with its protograph representation as an example of codes to which the present method applies. An encoderfor this code includes a precoder in the form of a punctured accumulator.

NASA Tech Briefs, October 2009 31