LD2 08.ppt - Universitatea din Craiova · 2020-05-18 · Title: Microsoft PowerPoint - LD2_08.ppt...
Transcript of LD2 08.ppt - Universitatea din Craiova · 2020-05-18 · Title: Microsoft PowerPoint - LD2_08.ppt...
LOGICAL DESIGN 2
Course titular:DUMITRAŞCU Eugen
SYNTHESIS OF DIGITAL SYSTEMS
CHAPTER 8
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CONTENT
Synthesis stages of a digital system ASM charts Synthesis methods of CCS VHDL synthesis of a CCS
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SYNTHESIS STAGES OF A DIGITAL SYSTEM
Definitions It's called digital system any system that receives to the
input a set of sizes (quantities) with binary values that represent numbers (operands) or commands used for processing, maintenance and transmission and offers to the output the results also represented in binary form.
DSinputs(external data)
results
m n
Status information
DSinputs
(external data)results
m n
k
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SYNTHESIS STAGES OF A DIGITAL SYSTEM
A detailed analysis of inputs shows that these can be divided into: External command inputs specify the function that must
realize the system at a time. Operands - data that the system must process them to obtain
a certain result. Status information – feedback (reaction) from the outputs of
the scheme, used to allow the control of own functioning.
We will consider a digital system any collection of combinational or sequential digital circuits that interact based on an algorithm for achieving well defined objectives.
operands
external commands
results
DS
Status information
nm1
m2
k
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SYNTHESIS STAGES OF A DIGITAL SYSTEM
Structure of digital system: Execution scheme (ES) performs processing operands on an
algorithm and could be a combinational or sequential. Command and control scheme (CCS) or controller
materializes the algorithm of processing operands. The controller is a Sequential Logic Scheme.
internal commands
CCS ES
CLOCK
external commands
operands
results
status information
n
k
p
q
m
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SYNTHESIS STAGES OF A DIGITAL SYSTEM
Synthesis stages of a digital systemS1) Starting from the needs expressed by beneficiary it is
composed project specification that contains detailed functions that must be performed by the system, specific working conditions, duration, sequence, the activation level, signal output voltage values, etc.
S2) If the original system must realize many relatively independent functions or the control algorithm is too complicated it goes to emphasize some simpler subsystems through a decomposition process that ensures each subsystem to carry out one or more logical functions connected naturally.
S3) Proceed to implement each of the considered subsystems by dividing into CCS and ES.
S4) Based on the catalogs of components is specified the required resources to implement ES .
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SYNTHESIS STAGES OF A DIGITAL SYSTEM
S5) Only after this step you can specify all the signals that provide the interaction between CCS and ES and all logical and electrical characteristics of these signals.
S6) For each highlighted CCS is specified through known methods the control and command algorithm. The methods for specifying the algorithm can be divided into two broad categories: a) graphical methods (eg ASM – Algorithm State Machine charts/diagram )b) hardware description languages (eg VHDL and Verilog HDL language).
S7) The CCS is synthesized by one of the convenient methods.
S8) It is analyzed the functioning of ES and CCS in order to highlight any abnormal performance.
S9) It is tested by computer simulation the overall functioning of the system design.
S10) Proceed to implement and test the system under real conditions.
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CONTENT
Synthesis stages of a digital system ASM charts Synthesis methods of CCS VHDL synthesis of a CCS
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ASM CHARTSSymbols
Si S0
START#
C1,C2# C1,C2#
state initial state
unconditional outputs block conditional outputs block
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ASM CHARTS
conditional block
XY# X,Y#FF TT
TFFTc)
XF
T a)
F
T b)
XF
T
A
XF
T
A
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ASM CHARTS
A
XF
Y#
T
C1 C2#
CB
C1 C2#
T F
INIT#
t
state A state Astate B
CLOCK
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ASM CHARTS
A
XF
Y#
T
C1 C2#
CB
C1 C2#
T F
INIT#
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CONTENT
Synthesis stages of a digital system ASM charts Synthesis methods of CCS VHDL synthesis of a CCS
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SYNTHESIS METHODS OF CCSDirect synthesis
A
XF
Y#
T
C1 C2#
CB
C1 C2#
T F
INIT#y1y2
00
01 11
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SYNTHESIS METHODS OF CCS1)Y#(XC1 BA
1)Y#(XC2# CA
2121 )Y#(XC1 yyyy
2121 )Y#(XC2# yyyy
R R
CLOCK
INIT#
D DQ Q
CLK CLK
D1 D2y1 y2
Q Qy1 y2
S0
PS
...Su1
Suk
NS
... ... ...
Transition condition
)(XY#D1 21 yyX)Y#XY#(XD2 2121 yyyy
y1y2 D1D2
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SYNTHESIS METHODS OF CCSSynthesis with VEM diagram
A
XF
Y#
T
C1 C2#
CB
C1 C2#
T F
INIT#y1y2
00
01 11
XY#
01
-
y1
y20 1
0
1
C1
X Y#
01
-
y1
y20 1
0
1
C2#
)Y#(XyyyC1 221
)XY#(yyyC2# 221
XY#
00
-
y1
y20 1
0
1
D1
XY#+XY#
00
-
y1
y20 1
0
1
D2
)(XY#yD1 2
(X)y)XY#Y#(XyD2 22
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SYNTHESIS METHODS OF CCSSynthesis with MUX
Y
S1
S0
I0 I3I2I1y1
y2
C1
0 01XY#
Y
S1
S0
I0 I3I2I1y1
y2
D1
0 0XY#
Y
S1
S0
I0 I3I2I1y1
y2
0 01XY#
Y
S1
S0
I0 I3I2I1y1
y2
D2
0 00X
C2#
0
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SYNTHESIS METHODS OF CCSSynthesis with memory modules
MemoryState RegD1-Dn
Out RegA0-Ak-1
Ak-Ak+n-1
Short outputs
y0-yn-1
CLOCK
Test variables
Long outputs
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SYNTHESIS METHODS OF CCS
A0
A4
A3
A2
A1
CE
O0
O6
O5
O3
O2
O1
O7
O4 O3
D1
D2
C2#NC
NC
NC
NC
x
x
x
x
D0
D3
D2
D1
O2
O0
O1
y1
y2
C1C1*
C2#*
X
Y#
MEM
S0
S1
“1”
CLOCK
CLK
INIT#
CLR#
SN74194
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SYNTHESIS METHODS OF CCSA40
stare O0O1O2O3O4O5O6O7A0A1A2A300001000000
A0 000010001000 000011100100 000000111100 00001100000
B0 000011001000 000011000100 000011001100 000000000010 00000000101
-0 000000000110 000000001110 00000000001
C0 000000001010 000000000110 000000001111 00000000000
-1 000000001001 000000000101 000000001101 00000000000
-1 000000001001 000000000101 000000001101 00000000001
-1 000000001011 000000000111 000000001111 00000000001
-1 000000001011 000000000111 00000000111
y1 C2#C1D2D1Y#Xy2
00001111000011110000111100001111
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SYNTHESIS METHODS OF CCSONE-HOT method
S0
NS
...Sp1
Spm
PS
... ... ...
Transition condition
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SYNTHESIS METHODS OF CCS
S RR
INIT#
DA DCDBA CB
D DD QQQ
CLOCK CLK CLKCLK
1)Y#(XC1 BA
1)Y#(XC2# CA
CBXADA
Y#AXDB
AXY#DC
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CONTENT
Synthesis stages of a digital system ASM charts Synthesis methods of CCS VHDL synthesis of a CCS
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VHDL SYNTHESIS OF CCS
A
XF
Y#
T
C1 C2#
CB
C1 C2#
T F
INIT#y1y2
00
01 11
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VHDL SYNTHESIS OF CCS
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VHDL SYNTHESIS OF CCS
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VHDL SYNTHESIS OF CCS
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VHDL SYNTHESIS OF CCS
QUESTIONS?