LCD Monitor Technical Training1/28* Model; Analog M series LCD monitor- L1510SM- L1710SM- L1910SM- L1515SM - L1715SM - L1520BM- L1720BM- L1920BM- L1530SM- L1730SM- L1930SMContent2/281. I/F Circuit operation Description1) Block diagram2) Signal Input block3) Suppl y Voltage regulation block4) Scaler Block5) Micro controller Block2. LIPS block operation description 1) Block diagram2) SMPS Block3) Inverter Block3. Appendix ; Operation principle of LCD Monitor1.1. Block diagram3/28D-SUBMST9111Aincluding(ADC /LVDS )MCULCD ModuleR,G,B differential LLowoltirntilinlin)SCLSDALIPS5VAVDD 3.3VDVDD 3.3V5VAC InputAVDD 2.5VDVDD 2.5V3.3VReg.AVDD3.3VDVDD3.3V2.5VReg.AVDD2.5VDVDD2.5V5V5V12VR,G,B, H/V Sync5V1. I/F Circuit operation Description4/281.2. Signal input Bl ock This is a signal input circuit diagram.This block consist of R,G,B, H-sync,V-sync,SCL and SDA signals.*1) This is a circuit for protection against the ESD.*2) This is a circuit which is used for impedance matching.75 ohm resistors on the R,G,B line are used for impedance matching .*3) Some Video card output is not stabilized. In this case, unexpected noisemay be seen. So this circuit is used for stability of H-sync ,V-sync.*4) ST-DET pin is used to realize the connection of the d-SUB signal cable.This pin is always low(GND) when D-SUB signal cable is connected.In case of disconnection with D-SUB cable, this pin come to be high(5V). Sheel GND 15 SOL14 V Sync 13 H Sync12 SDA 11 D0 (GND)10 GND (Diqital) 9 5V8. GND ( Siqnal Blue) 7 GND (Siqnal Green)6 GND (Siqnal RED) 5 S.T(GND)4 D2 (GND) 3 Blue2 Green 1 Red*1*1*1*1*2*3*4DSUB PN Descripion1. I/F Circuit operation Description5/281.3. Suppl y Voltage regulation block This is a supply voltage regulation block.This block consist of 3.3V regulator, 2.5V regulator, panel Vcc voltage switching circuit.*1) This is a voltage regulation circuit for 3.3V output.*2) This is a voltage regulation circuit for 2.5V output. *3) This is voltage TR switching circuit which is for panel Vcc power sequence. This circuit is used for 1517Model except for 17AU,19*4) This is voltage FET switching circuit which is for panel Vcc power sequence. This circuit is used for 17AU,19Model.*1*2*3*41. I/F Circuit operation Description6/281.4. Scaler block MST9011B (15 ), MST 9111B(17 ,19 )1. Manufacturer : M star2. Fully integrated ADC , PLL andscaler, LVDS3. Input sampling rate :- MST9011B : 85MHz - MST9111B : 135Mhz4. Input Format : - MST9011B : Analog RGB up to XGA (1024 * 768 @75Hz)- MST9111B : Analog RGB up to SXGA (1280 * 1024 @75Hz)5. Output Format : 8 or 6-bit panelsOne (15) or Two(17,19) pixel output format*1*2* Input and output signal*1) Input block- R,G,B input ,- H-sync,V-sync, - DDC line (D-SDA,D-SCL)*2) Output block- LVDS output (5 channel) including ClockThis Scaler amplifies the level of video signal for the digital conversion and converts from the analog video signal to the digital video signal using a pixel clock and outputs 8-bit R, G, B signal to transmitter.The pixel clock for each mode is generated by the PLL.The range of the pixel clock is from 25MHz to 135MHz. 1. I/F Circuit operation Description7/281.5. micro-controller block This block consists of u-controller, EEPROM IC which stores control data, and Reset IC*1) U-controllerThe u-controller distinguishes polarity and frequency of the H/V sync are supplied from signal cable.And u-controller control Inverter on, LCD power on, Lamp current Adjustand communication with scaler.*2) EEPROMThe controlled data of each modes is stored in EEPROM.*3) Reset blockThe reset of the u-controller is active HighKIA7042 reset ICs output is low until 5V come to be over 4.2V so that u-controller can have stable reset operation. *1*2*31.I/F Circuit operation Description2.1. Block diagram2. LIPS block operation description8/282.2. SMPS Block 2.LIPS block operation description*3*1 *2*5*6*49/282.2. SMPS Block 2.LIPS block operation descriptionThis block is SMPS block.*1) EMI componentThis block construct Low pass filter for.*2) Input rectifier and smoothing filterThis block change AC input voltage to high DC voltage*3) PWM control circuitControl PWM oscillator frequency and drive switching MOSFET.*4) Energy transfer TransformerChange high voltage on primary side to low voltage on secondary side and meet the output voltage spec.*5) Output rectifier and filter- Through rectifier diode, get the DC voltage 12V,5V .- Construct filter to get more approach DC voltage.*6) Feedback circuitConstruct feedback circuit to control U101 wavy duty.10/282.3. INVERTER Block 2.LIPS block operation description*1*2*3*411/282.3. Inverter Block 2.LIPS block operation descriptionThis block is Inverter block.*1) Reset circuitThis block is for voltage detecting. When input 5V is less than 5VDC, U302 KIA7042 will shut down U301(OZ960). U301 (OZ960) will be reset if the voltage is recovered 5VDC.*2) PWM controllerU301 (OZ960) is the PWM output controller to drive CCFL .*3) Drive networkDual MOSFET for switch direct network to drive transformer.*4) Feedback and OVP circuit.Detect kick off voltage from transformer and transfer this feedback voltage to pin 2 of U301.If the feedback voltage is over 2V, U301(OZ960) will be shut down. 12/2813/281) LCD Monitor Block diagram2) Video signal Timing 3) Analog to Digital Converter 4) ADC Calibration5) Pixel sampling6) Output TTL Timing7) LVDS8) Power sequence for panelAppendixOperation principle of LCD Monitor(Analog)1. LCD Monitor Block diagram14/28ScalerA/DConverterPre-Amp.ClockGeneratorR/G/B R/G/BMicro-ControllerH/V SyncDigitalH SyncH SyncClockLVDSTX LCD ModuleR/G/B24 bitAnalogR/G/B24 bitDclk/H/V/DEInverterSignal FlowAppendix2.1. Timing formula- Dclk (Mhz) = Htotal * Vtotal * Vsync(Refresh Rate) - Dclk =1 / Tpixel ==Htotal * Hsync - Hsync =Vtotal * Vsync Vsync =Refresh RateHsync =Horizontal FrequencyDclk =Pixel clockFront porchVideoH-syncH-sync widthBack porchBlanking ActiveHtotal2. Video signal Timing 15/28Appendix2. Video signal Timing ActiveVideo AreaH SyncV SyncV StartH StartHsyncTotal Dot = Total ClockClock2.2. Timing configuration on Display16/28Appendix3. Analog to Digital Converter DividerLoop FilterVCOHsyncADC ClockPLL BlockAmp(0.7:1)R/G/BPre amp BlockCut offAD ConverterR/G/BAnalog to Digital Converter Block8 bit R/G/B data1V=255 : 11111111:0V=0 : 0000000017/28Appendix4. ADC Calibration 4.1. ADC Calibration Procedure18/28Each channel ol he ADC mus be calibraed belore i can be used.1. CFFSET1 is used o remove DC bias ollses in he ADC pah. 2. CFFSET2 is used o rim he ADC o he black level characerisics ol he FGB source.3. GAN is used o aliqn he lull scale volaqe swinq ol he exernal sourceo he maximum inpu ol he ADC.CFFSET and GAN calibraion should be done wih he real video source source.while capurinq a lull scale inpu.Calibraion is perlormed hrouqh lirmware rouines.Appendix4. ADC Calibration 4.2. Offset1 Calibration19/28 Cllse1 Compensae lor inernal DC ollse ol he inpu saqe olhe onchip rack and lold. To compensae he chip o chip variaion . Therelore. he reouiremen is o perlorm onl, once(a Facor,).Procedure is Se video inpu volaqe lor 0.0v. se qain o minimum read ADC oupus Se qain o maximum read ADC oupus Adus ollse 1 unil ADC oupus a minimum and maximum are he same (wihin i olerance)Appendix4.3. Offset2 Calibration4. ADC Calibration 20/28 Cllse2 Compensae lor inernal DC ollse ol he 2nd saqe ol he onchip rack and lold. When used wih ollse1. make he overall ADC ollse eoual o zero and independen ol he ADC qain seinq. deall, perlormed usinq acual analoq inpu wih lull ranqe values lrom qraphics source.Procedure is Se video inpu volaqe lor 0.0v. Decrease Cllse2 o lirs insance where ADC underllow llaqs are seAppendix4.4. Gain Calibration4. ADC Calibration 21/28 Gain Used o adus lull ranqe inpu o produce lull swinqADC codes (lrom 00h o FFh) someime. called auo color auo whie level auo balance Feouire a lull ranqe inpu source o be perlormed correcl, Procedure is Se video inpu volaqe lor 0.73v (or 0.7v lor some model). ncrease qain o lirs insance where ADC 0verllow llaqs are seAppendix4.5. Effect of incorrect ADC calibration4. ADC Calibration 22/28 l ADC calibraion is perlormed incorrecl,. hen lollowinq various arilacs miqh be happened. Sauraed Whie dilleren shades close o peak whie value can be dillereniaed. Unblack black dilleren shades ol black close o black lloor can be dillereniaed or black doesn black enouqh. Feduced apparen conrasAppendix5. Pixel sampling5.1. Pixel sampling Pointdeal deal deal deal Accepable Accepable Accepable Accepable No qood No qood No qood No qoodInput ClockInput dataStable Clock/Data Sampling Point23/28Appendix5. Pixel sampling5.2. How to find best pixel sampling point' '

'P2 P2 P2 P2P1 P1 P1 P1P3 P3 P3 P3P4 P4 P4 P4P1 P1 P1 P1P2 P2 P2 P2 P3 P3 P3 P3P4 P4 P4 P4h iAB24/28 Sum ol pixel dillerence Sum ol pixel dillerence Sum ol pixel dillerence Sum ol pixel dillerence For auo phase adusmen. sum ol pixel dillerence mehod is used. The pixel sum is hiqhes a bes phase poin. wohzlGdG OwKTwK6:P To lind bes phase poin is done b, lirmware rouine.Appendix! ! ! ! Oela++ l+m+nq oesci+pl+on oelween C+ock ano Oala Fa+++nq |alch Oela++ l+m+nq oesci+pl+on oelween C+ock ano Oala Fa+++nq |alch Oela++ l+m+nq oesci+pl+on oelween C+ock ano Oala Fa+++nq |alch Oela++ l+m+nq oesci+pl+on oelween C+ock ano Oala Fa+++nq |alchOalaC+ockOC/Msync/Vsync Oala Selup TOScTUP Oala selup l1me oefcie a!!1nq Edqe cf C!cck Oala Mc!d TDMO|D Oala Mc!d up l1me aflei a!!1nq Edqe cf C!cck OE/Msync/Vsync Selup T8cTUP OE/Msync/Vsync selup l1me oefcie a!!1nq Edqe cf C!cck / OE/Msync/Vsync Mc!d TMO|D OE/Msync/Vsync Mc!d up l1me aflei a!!1nq Edqe cf C!cckDDDDDDDDDDDDDDDTOScTUP TOMO|OTScTUPTMO|OC!cck and dala TPcR1OOTM10MT|OWDDD6. Output timing25/28Appendix? ? ? ? Oulpul TT| S+qna+ oesci+pl+on measuieo al Pane+ s+oe Oulpul TT| S+qna+ oesci+pl+on measuieo al Pane+ s+oe Oulpul TT| S+qna+ oesci+pl+on measuieo al Pane+ s+oe Oulpul TT| S+qna+ oesci+pl+on measuieo al Pane+ s+oe Veil1ca! icnl Pcich Veil1ca! Sync W1dlh Veil1ca! Back Pcich / Veil1ca! Tcla! Acl1ve |1ne Veil1ca! Bank Pcich Veil1ca! icnl Pcich[ Mci1zcnla! icnl Pcich [ Mci1zcnla! Sync W1dlh Mci1zcnla! Back Pcich [ Mci1zcnla! Tcla! Acl1ve P1xe! Mci1zcnla! Back Pcich Mci1zcnla! icnl Pcich Acl1ve |1ne Acl1ve |1ne Oala) Acl1ve Oala Acl1ve P1xe! OalaVsyncOEMsync /[ )AA B!cck Oela1!OEMsyncC!cck[ [ Oulpul sync s1qna! T1m1nq 6. Output timing26/28Appendix7. LVDS7.1. 7.1. 7.1. 7.1.LVD8 Low vollaqe dllerenlal sqnalnq) LVD8 Low vollaqe dllerenlal sqnalnq) LVD8 Low vollaqe dllerenlal sqnalnq) LVD8 Low vollaqe dllerenlal sqnalnq) Conver TTL siqnal o Low volaqe dillerenial siqnal.27/28Panel side I /F SystemAppendix8. Power sequence for Panel28/28Notes : 1. Please avoid floating state of interface signal at invalid period.2. When the interface signal is invalid, be sure to pull down the power supply for LCD VCCto 0V.Invalid signal with Vcc for a long period of time, causes permanent damage to LCD panel.3. Lamp power must be turn on after power supply for LCD and interface signals are valid.Parameter UnitsMin.ValuesTyp. Max.T 1T 2T 3T 4T 5T 6T 7msmsmsmsmsmssW0.012002000.01-1WWWWWWW1050WW5010W10%90% 90%10%T1 T2 T5 T6 T7T3 T4Valid dataLamp on0VOFF OFFPower supply for LCDVccInterface signalPower for LAMP10% 10%0VAppendix